Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100601913	1			T1	160757		T3	160155		T13	15194
all_pins[1]	100601913	1			T1	160757		T3	160155		T13	15194
all_pins[2]	100601913	1			T1	160757		T3	160155		T13	15194

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301053275	1			T1	481813		T3	480020		T13	45445
values[0x1]	752464	1			T1	458		T3	445		T13	137
transitions[0x0=>0x1]	750970	1			T1	458		T3	445		T13	137
transitions[0x1=>0x0]	751000	1			T1	458		T3	445		T13	137

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100095765	1			T1	160299		T3	159710		T13	15057
all_pins[0]	values[0x1]	506148	1			T1	458		T3	445		T13	137
all_pins[0]	transitions[0x0=>0x1]	506131	1			T1	458		T3	445		T13	137
all_pins[0]	transitions[0x1=>0x0]	58	1			T170	9		T171	3		T117	1
all_pins[1]	values[0x0]	100601838	1			T1	160757		T3	160155		T13	15194
all_pins[1]	values[0x1]	75	1			T170	9		T171	3		T116	1
all_pins[1]	transitions[0x0=>0x1]	63	1			T170	9		T171	3		T117	1
all_pins[1]	transitions[0x1=>0x0]	246229	1			T14	3395		T27	404		T28	1348
all_pins[2]	values[0x0]	100355672	1			T1	160757		T3	160155		T13	15194
all_pins[2]	values[0x1]	246241	1			T14	3395		T27	404		T28	1348
all_pins[2]	transitions[0x0=>0x1]	244776	1			T14	3366		T27	404		T28	1348
all_pins[2]	transitions[0x1=>0x0]	504713	1			T1	458		T3	445		T13	137