Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339517 |
1 |
|
|
T1 |
305 |
|
T3 |
300 |
|
T13 |
133 |
auto[1] |
3254 |
1 |
|
|
T13 |
16 |
|
T14 |
22 |
|
T18 |
8 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
306676 |
1 |
|
|
T1 |
305 |
|
T3 |
300 |
|
T13 |
67 |
auto[1] |
36095 |
1 |
|
|
T13 |
82 |
|
T14 |
125 |
|
T18 |
43 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329356 |
1 |
|
|
T1 |
305 |
|
T3 |
300 |
|
T13 |
114 |
auto[1] |
13415 |
1 |
|
|
T13 |
35 |
|
T14 |
57 |
|
T18 |
31 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13415 |
1 |
|
|
T13 |
35 |
|
T14 |
57 |
|
T18 |
31 |
sw_kmac_invalid_sideload |
329356 |
1 |
|
|
T1 |
305 |
|
T3 |
300 |
|
T13 |
114 |
app_valid_sideload |
13415 |
1 |
|
|
T13 |
35 |
|
T14 |
57 |
|
T18 |
31 |
app_invalid_sideload |
329356 |
1 |
|
|
T1 |
305 |
|
T3 |
300 |
|
T13 |
114 |