Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99589974	1			T1	454904		T2	449592		T3	462606
all_values[1]	99589974	1			T1	454904		T2	449592		T3	462606
all_values[2]	99589974	1			T1	454904		T2	449592		T3	462606

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

508142

1

T1

3

T2

7

T3

21

auto[1]

298261780

1

T1

136470

T2

134876

T3

138779

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297245757

1

T1

135446

T2

133852

T3

137764

auto[1]

1524165

1

T1

10251

T2

10254

T3

10173

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	167785	1			T1	1		T3	5		T13	3
all_values[0]	auto[0]	auto[1]	1988	1			T1	2		T3	6		T13	4
all_values[0]	auto[1]	auto[0]	98914134	1			T1	451486		T2	446174		T3	459210
all_values[0]	auto[1]	auto[1]	506067	1			T1	3415		T2	3418		T3	3385
all_values[1]	auto[0]	auto[0]	177631	1			T3	1		T13	7		T14	16
all_values[1]	auto[0]	auto[1]	1542	1			T3	2		T13	5		T14	3
all_values[1]	auto[1]	auto[0]	98904288	1			T1	451487		T2	446174		T3	459214
all_values[1]	auto[1]	auto[1]	506513	1			T1	3417		T2	3418		T3	3389
all_values[2]	auto[0]	auto[0]	157549	1			T2	5		T3	3		T13	3
all_values[2]	auto[0]	auto[1]	1647	1			T2	2		T3	4		T13	4
all_values[2]	auto[1]	auto[0]	98924370	1			T1	451487		T2	446169		T3	459212
all_values[2]	auto[1]	auto[1]	506408	1			T1	3417		T2	3416		T3	3387