Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99589974	1			T1	454904		T2	449592		T3	462606
all_pins[1]	99589974	1			T1	454904		T2	449592		T3	462606
all_pins[2]	99589974	1			T1	454904		T2	449592		T3	462606

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297935227	1			T1	136129		T2	134535		T3	138443
values[0x1]	834695	1			T1	3415		T2	3418		T3	3385
transitions[0x0=>0x1]	832620	1			T1	3415		T2	3418		T3	3385
transitions[0x1=>0x0]	832641	1			T1	3415		T2	3418		T3	3385

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99083907	1			T1	451489		T2	446174		T3	459221
all_pins[0]	values[0x1]	506067	1			T1	3415		T2	3418		T3	3385
all_pins[0]	transitions[0x0=>0x1]	506046	1			T1	3415		T2	3418		T3	3385
all_pins[0]	transitions[0x1=>0x0]	51	1			T183	2		T184	4		T120	1
all_pins[1]	values[0x0]	99589902	1			T1	454904		T2	449592		T3	462606
all_pins[1]	values[0x1]	72	1			T183	2		T184	4		T120	2
all_pins[1]	transitions[0x0=>0x1]	65	1			T183	2		T184	4		T120	2
all_pins[1]	transitions[0x1=>0x0]	328549	1			T18	260		T23	10678		T24	20831
all_pins[2]	values[0x0]	99261418	1			T1	454904		T2	449592		T3	462606
all_pins[2]	values[0x1]	328556	1			T18	260		T23	10678		T24	20831
all_pins[2]	transitions[0x0=>0x1]	326509	1			T18	260		T23	10599		T24	20698
all_pins[2]	transitions[0x1=>0x0]	504041	1			T1	3415		T2	3418		T3	3385