Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	617	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5283	1			T15	6		T18	5		T23	12
len_601_800	11987	1			T15	7		T18	18		T23	29
len_401_600	7919	1			T15	8		T18	12		T23	18
len_201_400	16195	1			T1	251		T2	251		T3	251
len_65_200	73842	1			T1	680		T2	680		T3	680
len_min_for_xof_require_squeeze	1011	1			T1	10		T2	10		T3	10
len_keccak_block_sizes[72]	743	1			T1	5		T2	5		T3	5
len_keccak_block_sizes[104]	753	1			T1	5		T2	5		T3	5
len_keccak_block_sizes[136]	765	1			T1	5		T2	5		T3	5
len_keccak_block_sizes[144]	282	1			T1	5		T2	5		T3	5
len_keccak_block_sizes[168]	289	1			T1	5		T2	5		T3	5
len_datapath_width	14089	1			T1	5		T2	5		T3	5
len_2_63	214945	1			T1	1329		T2	1329		T3	1329
len_1	49	1			T25	1		T199	1		T200	2