Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100866297	1			T1	21524		T2	23886		T3	220653
all_values[1]	100866297	1			T1	21524		T2	23886		T3	220653
all_values[2]	100866297	1			T1	21524		T2	23886		T3	220653

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417884

1

T1

159

T2

148

T3

35

auto[1]

302181007

1

T1

64413

T2

71510

T3

661924

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301072596

1

T1

63882

T2

70953

T3

660225

auto[1]

1526295

1

T1

690

T2

705

T3

1734

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	150844	1			T1	51		T3	3		T12	45
all_values[0]	auto[0]	auto[1]	1975	1			T1	2		T3	4		T12	6
all_values[0]	auto[1]	auto[0]	100206688	1			T1	21243		T2	23651		T3	220072
all_values[0]	auto[1]	auto[1]	506790	1			T1	228		T2	235		T3	574
all_values[1]	auto[0]	auto[0]	127302	1			T1	51		T2	147		T3	1
all_values[1]	auto[0]	auto[1]	1458	1			T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[0]	100230230	1			T1	21243		T2	23504		T3	220074
all_values[1]	auto[1]	auto[1]	507307	1			T1	228		T2	234		T3	576
all_values[2]	auto[0]	auto[0]	134807	1			T1	51		T3	15		T12	2396
all_values[2]	auto[0]	auto[1]	1498	1			T1	2		T3	10		T12	6
all_values[2]	auto[1]	auto[0]	100222725	1			T1	21243		T2	23651		T3	220060
all_values[2]	auto[1]	auto[1]	507267	1			T1	228		T2	235		T3	568