Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
371156 |
1 |
|
|
T1 |
304 |
|
T2 |
310 |
|
T3 |
2 |
auto[1] |
319626 |
1 |
|
|
T3 |
778 |
|
T12 |
322 |
|
T13 |
298 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173312 |
1 |
|
|
T1 |
74 |
|
T2 |
70 |
|
T3 |
206 |
lower_val |
170544 |
1 |
|
|
T1 |
86 |
|
T2 |
69 |
|
T3 |
198 |
zero_val |
1748 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346306 |
1 |
|
|
T1 |
156 |
|
T2 |
148 |
|
T3 |
420 |
lower_val |
344466 |
1 |
|
|
T1 |
148 |
|
T2 |
162 |
|
T3 |
360 |
zero_val |
10 |
1 |
|
|
T140 |
2 |
|
T141 |
2 |
|
T142 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46507 |
1 |
|
|
T1 |
40 |
|
T2 |
28 |
|
T12 |
3 |
higher_val |
higher_val |
auto[1] |
40363 |
1 |
|
|
T3 |
112 |
|
T12 |
21 |
|
T13 |
35 |
higher_val |
lower_val |
auto[0] |
46157 |
1 |
|
|
T1 |
34 |
|
T2 |
42 |
|
T12 |
1 |
higher_val |
lower_val |
auto[1] |
40282 |
1 |
|
|
T3 |
94 |
|
T12 |
49 |
|
T13 |
38 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T140 |
1 |
|
T141 |
1 |
|
T142 |
1 |
lower_val |
higher_val |
auto[0] |
45806 |
1 |
|
|
T1 |
40 |
|
T2 |
32 |
|
T12 |
5 |
lower_val |
higher_val |
auto[1] |
39579 |
1 |
|
|
T3 |
115 |
|
T12 |
32 |
|
T13 |
32 |
lower_val |
lower_val |
auto[0] |
45503 |
1 |
|
|
T1 |
46 |
|
T2 |
37 |
|
T12 |
2 |
lower_val |
lower_val |
auto[1] |
39655 |
1 |
|
|
T3 |
83 |
|
T12 |
49 |
|
T13 |
34 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T143 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
655 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
216 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T17 |
6 |
zero_val |
lower_val |
auto[0] |
682 |
1 |
|
|
T2 |
2 |
|
T12 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
195 |
1 |
|
|
T3 |
1 |
|
T12 |
2 |
|
T17 |
8 |