Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100866297	1			T1	21524		T2	23886		T3	220653
all_pins[1]	100866297	1			T1	21524		T2	23886		T3	220653
all_pins[2]	100866297	1			T1	21524		T2	23886		T3	220653

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301798757	1			T1	64344		T2	71423		T3	661385
values[0x1]	800134	1			T1	228		T2	235		T3	574
transitions[0x0=>0x1]	798337	1			T1	228		T2	235		T3	574
transitions[0x1=>0x0]	798367	1			T1	228		T2	235		T3	574

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100359507	1			T1	21296		T2	23651		T3	220079
all_pins[0]	values[0x1]	506790	1			T1	228		T2	235		T3	574
all_pins[0]	transitions[0x0=>0x1]	506778	1			T1	228		T2	235		T3	574
all_pins[0]	transitions[0x1=>0x0]	56	1			T153	3		T154	3		T155	5
all_pins[1]	values[0x0]	100866229	1			T1	21524		T2	23886		T3	220653
all_pins[1]	values[0x1]	68	1			T153	3		T154	3		T155	5
all_pins[1]	transitions[0x0=>0x1]	54	1			T153	3		T154	3		T155	5
all_pins[1]	transitions[0x1=>0x0]	293262	1			T18	48		T29	1830		T23	4552
all_pins[2]	values[0x0]	100573021	1			T1	21524		T2	23886		T3	220653
all_pins[2]	values[0x1]	293276	1			T18	48		T29	1830		T23	4552
all_pins[2]	transitions[0x0=>0x1]	291505	1			T18	48		T29	1829		T23	4520
all_pins[2]	transitions[0x1=>0x0]	505049	1			T1	228		T2	235		T3	574