Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	613	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5259	1			T1	28		T2	25		T12	24
len_601_800	12078	1			T1	59		T2	49		T12	50
len_401_600	7918	1			T1	27		T2	35		T12	29
len_201_400	16428	1			T1	16		T2	23		T12	15
len_65_200	73960	1			T1	14		T2	14		T12	12
len_min_for_xof_require_squeeze	1004	1			T2	1		T17	10		T37	9
len_keccak_block_sizes[72]	745	1			T17	5		T37	9		T40	5
len_keccak_block_sizes[104]	753	1			T17	5		T37	9		T40	5
len_keccak_block_sizes[136]	761	1			T17	5		T37	9		T40	5
len_keccak_block_sizes[144]	287	1			T17	5		T40	5		T167	5
len_keccak_block_sizes[168]	286	1			T17	5		T40	5		T167	5
len_datapath_width	13978	1			T1	1		T2	1		T12	6
len_2_63	214079	1			T1	4		T2	3		T3	390
len_1	49	1			T2	1		T12	1		T168	1