Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10496269 |
1 |
|
|
T1 |
25670 |
|
T2 |
24903 |
|
T3 |
2730 |
auto[1] |
25360390 |
1 |
|
|
T1 |
36638 |
|
T2 |
35690 |
|
T3 |
19500 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
35738144 |
1 |
|
|
T1 |
62198 |
|
T2 |
60481 |
|
T3 |
22230 |
triple_byte_access |
39498 |
1 |
|
|
T1 |
34 |
|
T2 |
45 |
|
T12 |
31 |
halfword_access |
39677 |
1 |
|
|
T1 |
43 |
|
T2 |
37 |
|
T12 |
35 |
byte_access |
39340 |
1 |
|
|
T1 |
33 |
|
T2 |
30 |
|
T12 |
31 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10377754 |
1 |
|
|
T1 |
25560 |
|
T2 |
24791 |
|
T3 |
2730 |
auto[0] |
triple_byte_access |
39498 |
1 |
|
|
T1 |
34 |
|
T2 |
45 |
|
T12 |
31 |
auto[0] |
halfword_access |
39677 |
1 |
|
|
T1 |
43 |
|
T2 |
37 |
|
T12 |
35 |
auto[0] |
byte_access |
39340 |
1 |
|
|
T1 |
33 |
|
T2 |
30 |
|
T12 |
31 |
auto[1] |
word_access |
25360390 |
1 |
|
|
T1 |
36638 |
|
T2 |
35690 |
|
T3 |
19500 |