Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102001093	1			T1	19343		T2	271		T13	288
all_values[1]	102001093	1			T1	19343		T2	271		T13	288
all_values[2]	102001093	1			T1	19343		T2	271		T13	288

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

560477

1

T1

936

T2

6

T13

12

auto[1]

305442802

1

T1

57093

T2

807

T13

852

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304469775

1

T1

57456

T2

765

T13

819

auto[1]

1533504

1

T1

573

T2

48

T13

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	199148	1			T1	371		T18	331		T19	1
all_values[0]	auto[0]	auto[1]	2032	1			T1	4		T18	2		T19	2
all_values[0]	auto[1]	auto[0]	101290777	1			T1	18781		T2	255		T13	273
all_values[0]	auto[1]	auto[1]	509136	1			T1	187		T2	16		T13	15
all_values[1]	auto[0]	auto[0]	174402	1			T1	556		T2	5		T15	6
all_values[1]	auto[0]	auto[1]	1585	1			T1	5		T2	1		T15	1
all_values[1]	auto[1]	auto[0]	101315523	1			T1	18596		T2	250		T13	273
all_values[1]	auto[1]	auto[1]	509583	1			T1	186		T2	15		T13	15
all_values[2]	auto[0]	auto[0]	181796	1			T13	10		T14	1		T15	22
all_values[2]	auto[0]	auto[1]	1514	1			T13	2		T15	2		T18	3
all_values[2]	auto[1]	auto[0]	101308129	1			T1	19152		T2	255		T13	263
all_values[2]	auto[1]	auto[1]	509654	1			T1	191		T2	16		T13	13