Summary for Variable key_len
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for key_len
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Key128] |
66616 |
1 |
|
|
T1 |
17 |
|
T14 |
6 |
|
T15 |
42 |
auto[Key192] |
66555 |
1 |
|
|
T1 |
22 |
|
T14 |
3 |
|
T15 |
43 |
auto[Key256] |
80902 |
1 |
|
|
T1 |
104 |
|
T2 |
9 |
|
T13 |
9 |
auto[Key384] |
65973 |
1 |
|
|
T1 |
20 |
|
T14 |
8 |
|
T15 |
37 |
auto[Key512] |
66314 |
1 |
|
|
T1 |
31 |
|
T14 |
9 |
|
T15 |
34 |
Summary for Variable kmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
312571 |
1 |
|
|
T1 |
102 |
|
T14 |
15 |
|
T15 |
47 |
auto[1] |
33789 |
1 |
|
|
T1 |
92 |
|
T2 |
9 |
|
T13 |
9 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
67460 |
1 |
|
|
T1 |
4 |
|
T14 |
1 |
|
T15 |
28 |
auto[Shake] |
241833 |
1 |
|
|
T1 |
71 |
|
T14 |
5 |
|
T15 |
19 |
auto[CShake] |
37067 |
1 |
|
|
T1 |
119 |
|
T2 |
9 |
|
T13 |
9 |
Summary for Variable msg_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for msg_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173223 |
1 |
|
|
T1 |
100 |
|
T2 |
4 |
|
T13 |
4 |
auto[1] |
173137 |
1 |
|
|
T1 |
94 |
|
T2 |
5 |
|
T13 |
5 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336759 |
1 |
|
|
T1 |
147 |
|
T2 |
9 |
|
T13 |
9 |
auto[1] |
9601 |
1 |
|
|
T1 |
47 |
|
T14 |
5 |
|
T18 |
24 |
Summary for Variable state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173004 |
1 |
|
|
T1 |
113 |
|
T2 |
5 |
|
T13 |
3 |
auto[1] |
173356 |
1 |
|
|
T1 |
81 |
|
T2 |
4 |
|
T13 |
6 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
139394 |
1 |
|
|
T1 |
79 |
|
T2 |
6 |
|
T13 |
6 |
auto[L224] |
19876 |
1 |
|
|
T1 |
4 |
|
T15 |
10 |
|
T16 |
1 |
auto[L256] |
158539 |
1 |
|
|
T1 |
111 |
|
T2 |
3 |
|
T13 |
3 |
auto[L384] |
15872 |
1 |
|
|
T15 |
5 |
|
T16 |
3 |
|
T66 |
310 |
auto[L512] |
12679 |
1 |
|
|
T15 |
8 |
|
T16 |
6 |
|
T18 |
1 |
Summary for Variable xof_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for xof_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
327121 |
1 |
|
|
T1 |
168 |
|
T2 |
9 |
|
T14 |
32 |
auto[1] |
19239 |
1 |
|
|
T1 |
26 |
|
T13 |
9 |
|
T14 |
12 |
Summary for Cross kmac_cross
Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for kmac_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
33789 |
1 |
|
|
T1 |
92 |
|
T2 |
9 |
|
T13 |
9 |
Summary for Cross cshake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for cshake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
37067 |
1 |
|
|
T1 |
119 |
|
T2 |
9 |
|
T13 |
9 |
Summary for Cross shake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for shake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
241833 |
1 |
|
|
T1 |
71 |
|
T14 |
5 |
|
T15 |
19 |
Summary for Cross sha3_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for sha3_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
67460 |
1 |
|
|
T1 |
4 |
|
T14 |
1 |
|
T15 |
28 |