Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
314748 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T13 |
18 |
auto[1] |
380392 |
1 |
|
|
T1 |
386 |
|
T2 |
16 |
|
T19 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174302 |
1 |
|
|
T1 |
122 |
|
T2 |
9 |
|
T13 |
4 |
lower_val |
171930 |
1 |
|
|
T1 |
94 |
|
T2 |
4 |
|
T14 |
24 |
zero_val |
1808 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347456 |
1 |
|
|
T1 |
224 |
|
T2 |
10 |
|
T13 |
4 |
lower_val |
347672 |
1 |
|
|
T1 |
164 |
|
T2 |
8 |
|
T13 |
14 |
zero_val |
12 |
1 |
|
|
T135 |
2 |
|
T69 |
2 |
|
T163 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
39434 |
1 |
|
|
T13 |
1 |
|
T14 |
13 |
|
T15 |
42 |
higher_val |
higher_val |
auto[1] |
47423 |
1 |
|
|
T1 |
63 |
|
T2 |
5 |
|
T19 |
59 |
higher_val |
lower_val |
auto[0] |
39534 |
1 |
|
|
T2 |
1 |
|
T13 |
3 |
|
T14 |
9 |
higher_val |
lower_val |
auto[1] |
47908 |
1 |
|
|
T1 |
59 |
|
T2 |
3 |
|
T19 |
77 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T163 |
1 |
|
T164 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T69 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
38931 |
1 |
|
|
T14 |
14 |
|
T15 |
58 |
|
T16 |
32 |
lower_val |
higher_val |
auto[1] |
47300 |
1 |
|
|
T1 |
51 |
|
T2 |
2 |
|
T19 |
64 |
lower_val |
lower_val |
auto[0] |
38723 |
1 |
|
|
T14 |
10 |
|
T15 |
58 |
|
T16 |
22 |
lower_val |
lower_val |
auto[1] |
46972 |
1 |
|
|
T1 |
43 |
|
T2 |
2 |
|
T19 |
48 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T163 |
1 |
|
T164 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T69 |
1 |
|
T165 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
645 |
1 |
|
|
T1 |
1 |
|
T14 |
1 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
285 |
1 |
|
|
T19 |
4 |
|
T38 |
2 |
|
T116 |
1 |
zero_val |
lower_val |
auto[0] |
644 |
1 |
|
|
T2 |
1 |
|
T13 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
234 |
1 |
|
|
T116 |
1 |
|
T22 |
2 |
|
T84 |
1 |