Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102001093	1			T1	19343		T2	271		T13	288
all_pins[1]	102001093	1			T1	19343		T2	271		T13	288
all_pins[2]	102001093	1			T1	19343		T2	271		T13	288

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	305235173	1			T1	57842		T2	797		T13	849
values[0x1]	768106	1			T1	187		T2	16		T13	15
transitions[0x0=>0x1]	766571	1			T1	187		T2	16		T13	15
transitions[0x1=>0x0]	766595	1			T1	187		T2	16		T13	15

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101491957	1			T1	19156		T2	255		T13	273
all_pins[0]	values[0x1]	509136	1			T1	187		T2	16		T13	15
all_pins[0]	transitions[0x0=>0x1]	509120	1			T1	187		T2	16		T13	15
all_pins[0]	transitions[0x1=>0x0]	45	1			T173	3		T174	3		T175	3
all_pins[1]	values[0x0]	102001032	1			T1	19343		T2	271		T13	288
all_pins[1]	values[0x1]	61	1			T173	3		T174	3		T175	3
all_pins[1]	transitions[0x0=>0x1]	50	1			T173	3		T174	3		T175	3
all_pins[1]	transitions[0x1=>0x0]	258898	1			T27	128		T22	1035		T46	881
all_pins[2]	values[0x0]	101742184	1			T1	19343		T2	271		T13	288
all_pins[2]	values[0x1]	258909	1			T27	128		T22	1035		T46	881
all_pins[2]	transitions[0x0=>0x1]	257401	1			T27	128		T22	1029		T46	880
all_pins[2]	transitions[0x1=>0x0]	507652	1			T1	187		T2	16		T13	15