Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101771147	1			T1	220910		T2	9252		T13	287
all_values[1]	101771147	1			T1	220910		T2	9252		T13	287
all_values[2]	101771147	1			T1	220910		T2	9252		T13	287

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

543422

1

T1

14

T2

819

T13

12

auto[1]

304770019

1

T1

662716

T2

26937

T13

849

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303785703

1

T1

661008

T2

27513

T13

819

auto[1]

1527738

1

T1

1722

T2

243

T13

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	170220	1			T2	528		T13	8		T15	338
all_values[0]	auto[0]	auto[1]	1996	1			T2	4		T13	4		T15	6
all_values[0]	auto[1]	auto[0]	101091681	1			T1	220336		T2	8643		T13	265
all_values[0]	auto[1]	auto[1]	507250	1			T1	574		T2	77		T13	10
all_values[1]	auto[0]	auto[0]	171735	1			T1	4		T14	2		T15	37
all_values[1]	auto[0]	auto[1]	1498	1			T1	3		T14	1		T15	2
all_values[1]	auto[1]	auto[0]	101090166	1			T1	220332		T2	9171		T13	273
all_values[1]	auto[1]	auto[1]	507748	1			T1	571		T2	81		T13	14
all_values[2]	auto[0]	auto[0]	196421	1			T1	4		T2	285		T14	2
all_values[2]	auto[0]	auto[1]	1552	1			T1	3		T2	2		T14	1
all_values[2]	auto[1]	auto[0]	101065480	1			T1	220332		T2	8886		T13	273
all_values[2]	auto[1]	auto[1]	507694	1			T1	571		T2	79		T13	14