Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
351032 |
1 |
|
|
T1 |
780 |
|
T2 |
2 |
|
T13 |
18 |
auto[1] |
341110 |
1 |
|
|
T2 |
178 |
|
T17 |
500 |
|
T49 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173188 |
1 |
|
|
T1 |
197 |
|
T2 |
52 |
|
T13 |
4 |
lower_val |
170789 |
1 |
|
|
T1 |
178 |
|
T2 |
41 |
|
T13 |
8 |
zero_val |
1807 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T13 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
343710 |
1 |
|
|
T1 |
360 |
|
T2 |
76 |
|
T13 |
10 |
lower_val |
348420 |
1 |
|
|
T1 |
420 |
|
T2 |
104 |
|
T13 |
8 |
zero_val |
12 |
1 |
|
|
T158 |
2 |
|
T159 |
2 |
|
T160 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43360 |
1 |
|
|
T1 |
93 |
|
T13 |
3 |
|
T14 |
96 |
higher_val |
higher_val |
auto[1] |
42520 |
1 |
|
|
T2 |
22 |
|
T17 |
43 |
|
T49 |
67 |
higher_val |
lower_val |
auto[0] |
44250 |
1 |
|
|
T1 |
104 |
|
T13 |
1 |
|
T14 |
95 |
higher_val |
lower_val |
auto[1] |
43052 |
1 |
|
|
T2 |
30 |
|
T17 |
59 |
|
T49 |
86 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T158 |
1 |
|
T161 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
4 |
1 |
|
|
T159 |
1 |
|
T160 |
1 |
|
T162 |
2 |
lower_val |
higher_val |
auto[0] |
42979 |
1 |
|
|
T1 |
99 |
|
T13 |
3 |
|
T14 |
91 |
lower_val |
higher_val |
auto[1] |
41880 |
1 |
|
|
T2 |
18 |
|
T17 |
57 |
|
T49 |
97 |
lower_val |
lower_val |
auto[0] |
43386 |
1 |
|
|
T1 |
79 |
|
T13 |
5 |
|
T14 |
99 |
lower_val |
lower_val |
auto[1] |
42542 |
1 |
|
|
T2 |
23 |
|
T17 |
75 |
|
T49 |
81 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T161 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T159 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
668 |
1 |
|
|
T1 |
1 |
|
T13 |
1 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
246 |
1 |
|
|
T2 |
1 |
|
T17 |
3 |
|
T88 |
1 |
zero_val |
lower_val |
auto[0] |
664 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T4 |
1 |
zero_val |
lower_val |
auto[1] |
229 |
1 |
|
|
T2 |
1 |
|
T17 |
2 |
|
T88 |
1 |