Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101771147	1			T1	220910		T2	9252		T13	287
all_pins[1]	101771147	1			T1	220910		T2	9252		T13	287
all_pins[2]	101771147	1			T1	220910		T2	9252		T13	287

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	304545050	1			T1	662156		T2	27679		T13	851
values[0x1]	768391	1			T1	574		T2	77		T13	10
transitions[0x0=>0x1]	766806	1			T1	574		T2	77		T13	10
transitions[0x1=>0x0]	766832	1			T1	574		T2	77		T13	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101263897	1			T1	220336		T2	9175		T13	277
all_pins[0]	values[0x1]	507250	1			T1	574		T2	77		T13	10
all_pins[0]	transitions[0x0=>0x1]	507240	1			T1	574		T2	77		T13	10
all_pins[0]	transitions[0x1=>0x0]	85	1			T139	2		T36	4		T37	6
all_pins[1]	values[0x0]	101771052	1			T1	220910		T2	9252		T13	287
all_pins[1]	values[0x1]	95	1			T139	2		T36	4		T37	6
all_pins[1]	transitions[0x0=>0x1]	81	1			T139	2		T36	4		T37	6
all_pins[1]	transitions[0x1=>0x0]	261032	1			T17	767		T24	1013		T21	2018
all_pins[2]	values[0x0]	101510101	1			T1	220910		T2	9252		T13	287
all_pins[2]	values[0x1]	261046	1			T17	767		T24	1013		T21	2018
all_pins[2]	transitions[0x0=>0x1]	259485	1			T17	759		T24	1013		T21	2006
all_pins[2]	transitions[0x1=>0x0]	505715	1			T1	574		T2	77		T13	10