Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	645	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5437	1			T2	12		T15	31		T17	39
len_601_800	12308	1			T2	9		T4	1		T15	54
len_401_600	8193	1			T2	15		T4	1		T15	57
len_201_400	16480	1			T2	9		T15	23		T17	29
len_65_200	73657	1			T2	6		T15	18		T17	17
len_min_for_xof_require_squeeze	990	1			T24	1		T112	9		T175	10
len_keccak_block_sizes[72]	751	1			T112	9		T175	5		T133	1
len_keccak_block_sizes[104]	746	1			T15	1		T112	9		T81	1
len_keccak_block_sizes[136]	761	1			T112	9		T175	5		T133	1
len_keccak_block_sizes[144]	285	1			T2	1		T175	5		T177	5
len_keccak_block_sizes[168]	291	1			T15	1		T17	1		T175	5
len_datapath_width	13977	1			T13	3		T17	6		T18	3
len_2_63	214265	1			T1	390		T2	39		T13	6
len_1	39	1			T21	1		T178	1		T179	1