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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.88 95.77 90.51 100.00 67.77 93.67 98.84 96.58


Total test records in report: 1236
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T1065 /workspace/coverage/default/33.kmac_error.1987690631 Jul 14 05:39:54 PM PDT 24 Jul 14 05:40:55 PM PDT 24 3419139512 ps
T1066 /workspace/coverage/default/16.kmac_key_error.1815373569 Jul 14 05:35:31 PM PDT 24 Jul 14 05:35:35 PM PDT 24 691375738 ps
T1067 /workspace/coverage/default/12.kmac_test_vectors_sha3_512.3698812049 Jul 14 05:34:51 PM PDT 24 Jul 14 05:50:48 PM PDT 24 131773536502 ps
T1068 /workspace/coverage/default/38.kmac_alert_test.723419288 Jul 14 05:41:45 PM PDT 24 Jul 14 05:41:46 PM PDT 24 15953492 ps
T1069 /workspace/coverage/default/31.kmac_stress_all.2535712063 Jul 14 05:39:18 PM PDT 24 Jul 14 05:50:24 PM PDT 24 26041771730 ps
T1070 /workspace/coverage/default/36.kmac_test_vectors_sha3_256.902896842 Jul 14 05:40:52 PM PDT 24 Jul 14 06:03:59 PM PDT 24 178146384456 ps
T1071 /workspace/coverage/default/6.kmac_burst_write.629307302 Jul 14 05:34:33 PM PDT 24 Jul 14 05:35:27 PM PDT 24 9622641399 ps
T1072 /workspace/coverage/default/11.kmac_test_vectors_shake_128.743038376 Jul 14 05:34:49 PM PDT 24 Jul 14 06:56:33 PM PDT 24 254182283664 ps
T1073 /workspace/coverage/default/46.kmac_alert_test.963525243 Jul 14 05:45:11 PM PDT 24 Jul 14 05:45:12 PM PDT 24 14231438 ps
T1074 /workspace/coverage/default/5.kmac_burst_write.3775843576 Jul 14 05:34:29 PM PDT 24 Jul 14 05:49:06 PM PDT 24 37444575861 ps
T1075 /workspace/coverage/default/6.kmac_edn_timeout_error.2760626750 Jul 14 05:34:39 PM PDT 24 Jul 14 05:35:16 PM PDT 24 506074801 ps
T1076 /workspace/coverage/default/18.kmac_test_vectors_sha3_384.735196312 Jul 14 05:35:45 PM PDT 24 Jul 14 05:53:57 PM PDT 24 104217065487 ps
T1077 /workspace/coverage/default/41.kmac_app.2241451703 Jul 14 05:42:53 PM PDT 24 Jul 14 05:46:21 PM PDT 24 4052231468 ps
T1078 /workspace/coverage/default/46.kmac_lc_escalation.1401764565 Jul 14 05:45:11 PM PDT 24 Jul 14 05:45:12 PM PDT 24 125516612 ps
T1079 /workspace/coverage/default/47.kmac_test_vectors_shake_256.3900723899 Jul 14 05:45:29 PM PDT 24 Jul 14 06:43:29 PM PDT 24 42951675124 ps
T1080 /workspace/coverage/default/3.kmac_burst_write.1189162869 Jul 14 05:34:10 PM PDT 24 Jul 14 05:38:45 PM PDT 24 10646354129 ps
T1081 /workspace/coverage/default/34.kmac_test_vectors_sha3_224.3769402369 Jul 14 05:40:10 PM PDT 24 Jul 14 06:08:41 PM PDT 24 129365624863 ps
T1082 /workspace/coverage/default/46.kmac_key_error.818556557 Jul 14 05:45:11 PM PDT 24 Jul 14 05:45:15 PM PDT 24 1228196365 ps
T1083 /workspace/coverage/default/32.kmac_test_vectors_sha3_512.818848847 Jul 14 05:39:25 PM PDT 24 Jul 14 05:53:37 PM PDT 24 32796463200 ps
T1084 /workspace/coverage/default/39.kmac_error.1285641060 Jul 14 05:42:02 PM PDT 24 Jul 14 05:42:11 PM PDT 24 1257950716 ps
T1085 /workspace/coverage/default/34.kmac_burst_write.3222961360 Jul 14 05:40:00 PM PDT 24 Jul 14 05:49:59 PM PDT 24 28183753702 ps
T93 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.726524109 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 18109932 ps
T94 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2499648052 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:32 PM PDT 24 206830792 ps
T90 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.421096948 Jul 14 06:40:21 PM PDT 24 Jul 14 06:40:28 PM PDT 24 58453904 ps
T119 /workspace/coverage/cover_reg_top/15.kmac_intr_test.1290639804 Jul 14 06:40:28 PM PDT 24 Jul 14 06:40:36 PM PDT 24 15913972 ps
T120 /workspace/coverage/cover_reg_top/33.kmac_intr_test.2804578815 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:35 PM PDT 24 44903170 ps
T1086 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.412732658 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:17 PM PDT 24 31900043 ps
T91 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3703826751 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:17 PM PDT 24 45908670 ps
T50 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2697616714 Jul 14 06:40:26 PM PDT 24 Jul 14 06:40:35 PM PDT 24 21936934 ps
T51 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.213283110 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:26 PM PDT 24 169491444 ps
T121 /workspace/coverage/cover_reg_top/6.kmac_intr_test.2068583151 Jul 14 06:40:11 PM PDT 24 Jul 14 06:40:17 PM PDT 24 13831412 ps
T165 /workspace/coverage/cover_reg_top/11.kmac_intr_test.2501960750 Jul 14 06:40:21 PM PDT 24 Jul 14 06:40:28 PM PDT 24 14803813 ps
T1087 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3236886492 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:17 PM PDT 24 36976732 ps
T1088 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3959468482 Jul 14 06:40:13 PM PDT 24 Jul 14 06:40:38 PM PDT 24 964615911 ps
T92 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.114141530 Jul 14 06:40:28 PM PDT 24 Jul 14 06:40:37 PM PDT 24 33597691 ps
T1089 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2344556186 Jul 14 06:40:04 PM PDT 24 Jul 14 06:40:07 PM PDT 24 75142546 ps
T1090 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3620320142 Jul 14 06:40:06 PM PDT 24 Jul 14 06:40:12 PM PDT 24 154121074 ps
T95 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1484951105 Jul 14 06:40:17 PM PDT 24 Jul 14 06:40:23 PM PDT 24 22923168 ps
T52 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2152027604 Jul 14 06:40:06 PM PDT 24 Jul 14 06:40:12 PM PDT 24 60359504 ps
T96 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3932636867 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:27 PM PDT 24 128109559 ps
T163 /workspace/coverage/cover_reg_top/47.kmac_intr_test.3068727590 Jul 14 06:40:35 PM PDT 24 Jul 14 06:40:40 PM PDT 24 14543570 ps
T105 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1780666514 Jul 14 06:40:21 PM PDT 24 Jul 14 06:40:28 PM PDT 24 157899327 ps
T166 /workspace/coverage/cover_reg_top/12.kmac_intr_test.510191854 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 13454318 ps
T106 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1446899223 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:32 PM PDT 24 34994199 ps
T129 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.169738033 Jul 14 06:40:18 PM PDT 24 Jul 14 06:40:23 PM PDT 24 241757544 ps
T167 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1845265378 Jul 14 06:40:29 PM PDT 24 Jul 14 06:40:37 PM PDT 24 34685054 ps
T146 /workspace/coverage/cover_reg_top/24.kmac_intr_test.2725102855 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:35 PM PDT 24 12710468 ps
T107 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1967772778 Jul 14 06:40:04 PM PDT 24 Jul 14 06:40:09 PM PDT 24 1856192002 ps
T98 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1981527091 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:31 PM PDT 24 45621333 ps
T108 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1262866949 Jul 14 06:40:21 PM PDT 24 Jul 14 06:40:30 PM PDT 24 202326963 ps
T130 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2025924096 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:33 PM PDT 24 145512821 ps
T1091 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1293278136 Jul 14 06:40:16 PM PDT 24 Jul 14 06:40:21 PM PDT 24 33717360 ps
T164 /workspace/coverage/cover_reg_top/18.kmac_intr_test.2775985700 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:32 PM PDT 24 14102030 ps
T97 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1469067892 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:19 PM PDT 24 185980122 ps
T1092 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1590032778 Jul 14 06:40:13 PM PDT 24 Jul 14 06:40:26 PM PDT 24 136845636 ps
T1093 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.4170408374 Jul 14 06:40:11 PM PDT 24 Jul 14 06:40:18 PM PDT 24 27312511 ps
T1094 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1208573173 Jul 14 06:40:05 PM PDT 24 Jul 14 06:40:19 PM PDT 24 1736451066 ps
T109 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.696831824 Jul 14 06:40:03 PM PDT 24 Jul 14 06:40:06 PM PDT 24 375882017 ps
T1095 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3486629721 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:31 PM PDT 24 31293322 ps
T100 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3239261084 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:27 PM PDT 24 365207393 ps
T131 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1014019216 Jul 14 06:40:29 PM PDT 24 Jul 14 06:40:39 PM PDT 24 335492825 ps
T147 /workspace/coverage/cover_reg_top/14.kmac_intr_test.2531516124 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 130660829 ps
T1096 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2052345495 Jul 14 06:40:08 PM PDT 24 Jul 14 06:40:15 PM PDT 24 16339305 ps
T1097 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.511760612 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 87204730 ps
T1098 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1644707272 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:25 PM PDT 24 232114938 ps
T1099 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2001721182 Jul 14 06:40:05 PM PDT 24 Jul 14 06:40:09 PM PDT 24 15472062 ps
T1100 /workspace/coverage/cover_reg_top/8.kmac_intr_test.4077554411 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:29 PM PDT 24 35762528 ps
T132 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1999033505 Jul 14 06:42:08 PM PDT 24 Jul 14 06:42:13 PM PDT 24 248931730 ps
T142 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2548596086 Jul 14 06:40:11 PM PDT 24 Jul 14 06:40:18 PM PDT 24 58984458 ps
T143 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1528927069 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:38 PM PDT 24 124524810 ps
T1101 /workspace/coverage/cover_reg_top/19.kmac_intr_test.904158389 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:33 PM PDT 24 59908688 ps
T110 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1546929423 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:25 PM PDT 24 579912686 ps
T1102 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1823295146 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:33 PM PDT 24 27346633 ps
T1103 /workspace/coverage/cover_reg_top/2.kmac_intr_test.3810203566 Jul 14 06:40:17 PM PDT 24 Jul 14 06:40:22 PM PDT 24 30124108 ps
T1104 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3368932511 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:33 PM PDT 24 148298203 ps
T99 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3424791655 Jul 14 06:40:15 PM PDT 24 Jul 14 06:40:22 PM PDT 24 245015404 ps
T1105 /workspace/coverage/cover_reg_top/26.kmac_intr_test.3666987963 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:33 PM PDT 24 39661472 ps
T144 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2322887778 Jul 14 06:40:18 PM PDT 24 Jul 14 06:40:23 PM PDT 24 156200960 ps
T1106 /workspace/coverage/cover_reg_top/16.kmac_intr_test.968629065 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:34 PM PDT 24 11302833 ps
T1107 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2984348737 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:32 PM PDT 24 147075473 ps
T126 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2540552957 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:37 PM PDT 24 254946739 ps
T1108 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.241055042 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:36 PM PDT 24 68327948 ps
T111 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3527019462 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:20 PM PDT 24 569243170 ps
T1109 /workspace/coverage/cover_reg_top/30.kmac_intr_test.3910342378 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 43546154 ps
T122 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1045236001 Jul 14 06:40:28 PM PDT 24 Jul 14 06:40:38 PM PDT 24 125169395 ps
T1110 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3936454690 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:17 PM PDT 24 52088954 ps
T145 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3963150047 Jul 14 06:40:18 PM PDT 24 Jul 14 06:40:25 PM PDT 24 208799525 ps
T148 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2971640827 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 26392526 ps
T114 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1592621907 Jul 14 06:40:15 PM PDT 24 Jul 14 06:40:22 PM PDT 24 52668060 ps
T1111 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.4048544384 Jul 14 06:40:13 PM PDT 24 Jul 14 06:40:19 PM PDT 24 34435899 ps
T1112 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1984493809 Jul 14 06:40:03 PM PDT 24 Jul 14 06:40:05 PM PDT 24 60184700 ps
T1113 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3805876597 Jul 14 06:40:29 PM PDT 24 Jul 14 06:40:38 PM PDT 24 35393672 ps
T1114 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1064386117 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:29 PM PDT 24 201934414 ps
T115 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2170881782 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:27 PM PDT 24 34505491 ps
T149 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.4137152973 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:33 PM PDT 24 145621461 ps
T135 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3690006453 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:18 PM PDT 24 51255910 ps
T1115 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3536273232 Jul 14 06:40:04 PM PDT 24 Jul 14 06:40:08 PM PDT 24 46254565 ps
T1116 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1625281929 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:31 PM PDT 24 305077030 ps
T1117 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.562357519 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:24 PM PDT 24 247746612 ps
T1118 /workspace/coverage/cover_reg_top/25.kmac_intr_test.3406035523 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:30 PM PDT 24 51538263 ps
T1119 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1762781218 Jul 14 06:40:08 PM PDT 24 Jul 14 06:40:16 PM PDT 24 753273438 ps
T1120 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2937059756 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:29 PM PDT 24 29227756 ps
T1121 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1806418926 Jul 14 06:40:17 PM PDT 24 Jul 14 06:40:23 PM PDT 24 362594081 ps
T1122 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1694953622 Jul 14 06:40:11 PM PDT 24 Jul 14 06:40:18 PM PDT 24 25114816 ps
T1123 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2264527083 Jul 14 06:40:29 PM PDT 24 Jul 14 06:40:39 PM PDT 24 99946369 ps
T1124 /workspace/coverage/cover_reg_top/28.kmac_intr_test.2205601156 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:32 PM PDT 24 20942964 ps
T1125 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3742220592 Jul 14 06:40:05 PM PDT 24 Jul 14 06:40:11 PM PDT 24 508232829 ps
T171 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1880714704 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:19 PM PDT 24 371009311 ps
T1126 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3683949154 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:34 PM PDT 24 99930626 ps
T169 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2086375485 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:28 PM PDT 24 129567170 ps
T1127 /workspace/coverage/cover_reg_top/22.kmac_intr_test.756716397 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 71163150 ps
T125 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3436231272 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:35 PM PDT 24 69303962 ps
T1128 /workspace/coverage/cover_reg_top/43.kmac_intr_test.1333159914 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:34 PM PDT 24 14257321 ps
T1129 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2671654637 Jul 14 06:40:31 PM PDT 24 Jul 14 06:40:39 PM PDT 24 47676493 ps
T1130 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.722284634 Jul 14 06:40:14 PM PDT 24 Jul 14 06:40:20 PM PDT 24 65064716 ps
T1131 /workspace/coverage/cover_reg_top/36.kmac_intr_test.3425365811 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 41798877 ps
T1132 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2086524010 Jul 14 06:40:21 PM PDT 24 Jul 14 06:40:30 PM PDT 24 33690384 ps
T1133 /workspace/coverage/cover_reg_top/40.kmac_intr_test.326340140 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:33 PM PDT 24 62848046 ps
T1134 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3726000409 Jul 14 06:42:08 PM PDT 24 Jul 14 06:42:10 PM PDT 24 69084982 ps
T1135 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3422954405 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:25 PM PDT 24 28685844 ps
T1136 /workspace/coverage/cover_reg_top/4.kmac_intr_test.1086896309 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:24 PM PDT 24 14237275 ps
T170 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.76245863 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:30 PM PDT 24 1419436788 ps
T118 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2587001755 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:32 PM PDT 24 178199565 ps
T1137 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1674571236 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:32 PM PDT 24 80001385 ps
T1138 /workspace/coverage/cover_reg_top/38.kmac_intr_test.2521297621 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:33 PM PDT 24 23955817 ps
T116 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2991767408 Jul 14 06:40:18 PM PDT 24 Jul 14 06:40:24 PM PDT 24 65698292 ps
T1139 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.741686942 Jul 14 06:40:15 PM PDT 24 Jul 14 06:40:23 PM PDT 24 94502958 ps
T1140 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3718011685 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:16 PM PDT 24 31980395 ps
T1141 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1728841513 Jul 14 06:40:08 PM PDT 24 Jul 14 06:40:25 PM PDT 24 3025032548 ps
T1142 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3466889613 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:34 PM PDT 24 46270397 ps
T1143 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.817503511 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:33 PM PDT 24 24565100 ps
T1144 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1564462142 Jul 14 06:41:57 PM PDT 24 Jul 14 06:42:02 PM PDT 24 27128080 ps
T1145 /workspace/coverage/cover_reg_top/13.kmac_intr_test.2812614402 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:28 PM PDT 24 13494671 ps
T136 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3118360310 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:27 PM PDT 24 28393193 ps
T1146 /workspace/coverage/cover_reg_top/31.kmac_intr_test.1132676617 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:34 PM PDT 24 27141017 ps
T1147 /workspace/coverage/cover_reg_top/7.kmac_intr_test.170751551 Jul 14 06:40:09 PM PDT 24 Jul 14 06:40:15 PM PDT 24 34753900 ps
T1148 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2417921677 Jul 14 06:40:28 PM PDT 24 Jul 14 06:40:37 PM PDT 24 61331613 ps
T1149 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4281732837 Jul 14 06:40:07 PM PDT 24 Jul 14 06:40:13 PM PDT 24 113990684 ps
T1150 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.4272621610 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:30 PM PDT 24 17634181 ps
T1151 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3056457746 Jul 14 06:40:12 PM PDT 24 Jul 14 06:40:19 PM PDT 24 225796718 ps
T1152 /workspace/coverage/cover_reg_top/17.kmac_intr_test.3670889131 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:33 PM PDT 24 48220952 ps
T1153 /workspace/coverage/cover_reg_top/45.kmac_intr_test.189013423 Jul 14 06:40:28 PM PDT 24 Jul 14 06:40:37 PM PDT 24 20377144 ps
T1154 /workspace/coverage/cover_reg_top/5.kmac_intr_test.1786965626 Jul 14 06:40:14 PM PDT 24 Jul 14 06:40:20 PM PDT 24 26150205 ps
T1155 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3561760356 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:32 PM PDT 24 161987996 ps
T137 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.326030452 Jul 14 06:40:05 PM PDT 24 Jul 14 06:40:09 PM PDT 24 141248093 ps
T123 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3907146987 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:26 PM PDT 24 68085315 ps
T1156 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.250243157 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:27 PM PDT 24 33981468 ps
T124 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1920829958 Jul 14 06:40:21 PM PDT 24 Jul 14 06:40:30 PM PDT 24 41141776 ps
T1157 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.84200247 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:25 PM PDT 24 142355416 ps
T138 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.4085259091 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:18 PM PDT 24 413992008 ps
T1158 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.537925186 Jul 14 06:40:28 PM PDT 24 Jul 14 06:40:37 PM PDT 24 41151245 ps
T1159 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2323358369 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:29 PM PDT 24 87350932 ps
T1160 /workspace/coverage/cover_reg_top/27.kmac_intr_test.1563539325 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:35 PM PDT 24 51959005 ps
T1161 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2280825851 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:36 PM PDT 24 3857085942 ps
T1162 /workspace/coverage/cover_reg_top/1.kmac_intr_test.211788986 Jul 14 06:40:09 PM PDT 24 Jul 14 06:40:15 PM PDT 24 26056987 ps
T1163 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2525993540 Jul 14 06:40:30 PM PDT 24 Jul 14 06:40:38 PM PDT 24 21932867 ps
T1164 /workspace/coverage/cover_reg_top/29.kmac_intr_test.3823671848 Jul 14 06:40:30 PM PDT 24 Jul 14 06:40:38 PM PDT 24 14595335 ps
T1165 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2487838695 Jul 14 06:40:17 PM PDT 24 Jul 14 06:40:23 PM PDT 24 159719695 ps
T1166 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3836148758 Jul 14 06:40:15 PM PDT 24 Jul 14 06:40:21 PM PDT 24 89947563 ps
T1167 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3369912586 Jul 14 06:40:12 PM PDT 24 Jul 14 06:40:18 PM PDT 24 41974929 ps
T1168 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.4065994526 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:35 PM PDT 24 44236645 ps
T1169 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3033351871 Jul 14 06:40:29 PM PDT 24 Jul 14 06:40:38 PM PDT 24 47947437 ps
T127 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1613532213 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:32 PM PDT 24 148003351 ps
T1170 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2074399577 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:34 PM PDT 24 315284939 ps
T1171 /workspace/coverage/cover_reg_top/35.kmac_intr_test.3122592951 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:34 PM PDT 24 14682186 ps
T1172 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1303104089 Jul 14 06:40:08 PM PDT 24 Jul 14 06:40:17 PM PDT 24 219053416 ps
T1173 /workspace/coverage/cover_reg_top/44.kmac_intr_test.2718524206 Jul 14 06:40:29 PM PDT 24 Jul 14 06:40:37 PM PDT 24 42570808 ps
T1174 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.640079763 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:33 PM PDT 24 43955282 ps
T1175 /workspace/coverage/cover_reg_top/37.kmac_intr_test.3864228833 Jul 14 06:40:31 PM PDT 24 Jul 14 06:40:38 PM PDT 24 45505389 ps
T1176 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3707163168 Jul 14 06:40:04 PM PDT 24 Jul 14 06:40:08 PM PDT 24 137191470 ps
T1177 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.143263438 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:26 PM PDT 24 1138741218 ps
T1178 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.4293936646 Jul 14 06:40:08 PM PDT 24 Jul 14 06:40:16 PM PDT 24 349490396 ps
T117 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1256325001 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 250849311 ps
T1179 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1327454796 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:32 PM PDT 24 116669882 ps
T1180 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.572765093 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:34 PM PDT 24 38308859 ps
T1181 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.4224425343 Jul 14 06:40:21 PM PDT 24 Jul 14 06:40:30 PM PDT 24 70110820 ps
T1182 /workspace/coverage/cover_reg_top/48.kmac_intr_test.1337356192 Jul 14 06:40:30 PM PDT 24 Jul 14 06:40:38 PM PDT 24 165784877 ps
T1183 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1193352182 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:31 PM PDT 24 106288553 ps
T1184 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1442225730 Jul 14 06:40:12 PM PDT 24 Jul 14 06:40:18 PM PDT 24 15620955 ps
T1185 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3915909018 Jul 14 06:40:03 PM PDT 24 Jul 14 06:40:06 PM PDT 24 38326335 ps
T1186 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1817455966 Jul 14 06:40:17 PM PDT 24 Jul 14 06:40:22 PM PDT 24 20861445 ps
T172 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.379118373 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:33 PM PDT 24 119945196 ps
T1187 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1586513869 Jul 14 06:40:16 PM PDT 24 Jul 14 06:40:23 PM PDT 24 39386772 ps
T1188 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2355172935 Jul 14 06:40:26 PM PDT 24 Jul 14 06:40:34 PM PDT 24 82169407 ps
T1189 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1255218159 Jul 14 06:40:18 PM PDT 24 Jul 14 06:40:24 PM PDT 24 50724379 ps
T1190 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3472737440 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:27 PM PDT 24 42354401 ps
T173 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2008816985 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:34 PM PDT 24 310299749 ps
T1191 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.694078536 Jul 14 06:40:05 PM PDT 24 Jul 14 06:40:11 PM PDT 24 44253393 ps
T1192 /workspace/coverage/cover_reg_top/34.kmac_intr_test.522317067 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:34 PM PDT 24 117576188 ps
T1193 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3619768511 Jul 14 06:40:11 PM PDT 24 Jul 14 06:40:19 PM PDT 24 175785736 ps
T1194 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.613542252 Jul 14 06:40:21 PM PDT 24 Jul 14 06:40:29 PM PDT 24 92006820 ps
T1195 /workspace/coverage/cover_reg_top/39.kmac_intr_test.4156558153 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:35 PM PDT 24 17012552 ps
T1196 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3261553678 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:26 PM PDT 24 207489840 ps
T1197 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3919490265 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:34 PM PDT 24 50115296 ps
T1198 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2659546880 Jul 14 06:40:09 PM PDT 24 Jul 14 06:40:15 PM PDT 24 23909635 ps
T1199 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3684232493 Jul 14 06:40:08 PM PDT 24 Jul 14 06:40:18 PM PDT 24 206279668 ps
T1200 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3912250124 Jul 14 06:40:06 PM PDT 24 Jul 14 06:40:14 PM PDT 24 373921130 ps
T1201 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1117217881 Jul 14 06:40:07 PM PDT 24 Jul 14 06:40:21 PM PDT 24 782417113 ps
T1202 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2919862842 Jul 14 06:40:16 PM PDT 24 Jul 14 06:40:22 PM PDT 24 42656672 ps
T1203 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1176399167 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:26 PM PDT 24 95680511 ps
T1204 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.462757918 Jul 14 06:40:16 PM PDT 24 Jul 14 06:40:35 PM PDT 24 301130045 ps
T1205 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2017004966 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:18 PM PDT 24 351288637 ps
T1206 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.4048141167 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:32 PM PDT 24 14048210 ps
T1207 /workspace/coverage/cover_reg_top/10.kmac_intr_test.1788906074 Jul 14 06:40:20 PM PDT 24 Jul 14 06:40:26 PM PDT 24 18746078 ps
T1208 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2394573909 Jul 14 06:40:25 PM PDT 24 Jul 14 06:40:35 PM PDT 24 78952949 ps
T168 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.909553272 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:36 PM PDT 24 80025837 ps
T1209 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4031547780 Jul 14 06:40:16 PM PDT 24 Jul 14 06:40:30 PM PDT 24 602539801 ps
T1210 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.899512053 Jul 14 06:40:04 PM PDT 24 Jul 14 06:40:08 PM PDT 24 38384834 ps
T1211 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1385110315 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:35 PM PDT 24 274485301 ps
T1212 /workspace/coverage/cover_reg_top/9.kmac_intr_test.2490816584 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 13047450 ps
T1213 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.902576590 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:36 PM PDT 24 55771500 ps
T1214 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2667890550 Jul 14 06:40:03 PM PDT 24 Jul 14 06:40:06 PM PDT 24 43937891 ps
T1215 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3583573666 Jul 14 06:40:27 PM PDT 24 Jul 14 06:40:37 PM PDT 24 140241039 ps
T1216 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.422056179 Jul 14 06:40:10 PM PDT 24 Jul 14 06:40:17 PM PDT 24 75303082 ps
T1217 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3171629740 Jul 14 06:40:13 PM PDT 24 Jul 14 06:40:21 PM PDT 24 297210343 ps
T128 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2561867447 Jul 14 06:40:17 PM PDT 24 Jul 14 06:40:24 PM PDT 24 94644721 ps
T1218 /workspace/coverage/cover_reg_top/46.kmac_intr_test.1311310561 Jul 14 06:40:34 PM PDT 24 Jul 14 06:40:40 PM PDT 24 15564704 ps
T1219 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3407632156 Jul 14 06:40:11 PM PDT 24 Jul 14 06:40:18 PM PDT 24 61005817 ps
T1220 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2388363327 Jul 14 06:40:16 PM PDT 24 Jul 14 06:40:25 PM PDT 24 378362779 ps
T1221 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1483147836 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:25 PM PDT 24 82304309 ps
T1222 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1475351829 Jul 14 06:40:08 PM PDT 24 Jul 14 06:40:15 PM PDT 24 18541341 ps
T1223 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2897695337 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:29 PM PDT 24 42444575 ps
T1224 /workspace/coverage/cover_reg_top/32.kmac_intr_test.2801879795 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 39876028 ps
T1225 /workspace/coverage/cover_reg_top/20.kmac_intr_test.4190716031 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:30 PM PDT 24 20554100 ps
T174 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3104076978 Jul 14 06:40:16 PM PDT 24 Jul 14 06:40:26 PM PDT 24 814015591 ps
T1226 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.283368263 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:35 PM PDT 24 316326223 ps
T1227 /workspace/coverage/cover_reg_top/21.kmac_intr_test.3570828823 Jul 14 06:40:23 PM PDT 24 Jul 14 06:40:31 PM PDT 24 21914315 ps
T1228 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.750031625 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:30 PM PDT 24 107299405 ps
T1229 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2325333558 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:35 PM PDT 24 198816784 ps
T1230 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1085090765 Jul 14 06:40:19 PM PDT 24 Jul 14 06:40:25 PM PDT 24 30243284 ps
T1231 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1027501488 Jul 14 06:40:17 PM PDT 24 Jul 14 06:40:23 PM PDT 24 54398763 ps
T1232 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1005272664 Jul 14 06:40:24 PM PDT 24 Jul 14 06:40:33 PM PDT 24 69795908 ps
T1233 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2030768806 Jul 14 06:40:22 PM PDT 24 Jul 14 06:40:31 PM PDT 24 112264659 ps
T1234 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.4259055793 Jul 14 06:40:17 PM PDT 24 Jul 14 06:40:23 PM PDT 24 17801936 ps
T1235 /workspace/coverage/cover_reg_top/49.kmac_intr_test.2284589814 Jul 14 06:40:31 PM PDT 24 Jul 14 06:40:38 PM PDT 24 11915929 ps
T1236 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2264988657 Jul 14 06:40:15 PM PDT 24 Jul 14 06:40:22 PM PDT 24 103843943 ps

Test location /workspace/coverage/default/39.kmac_stress_all.1244080321
Short name T17
Test name
Test status
Simulation time 42183006720 ps
CPU time 852.08 seconds
Started Jul 14 05:42:02 PM PDT 24
Finished Jul 14 05:56:14 PM PDT 24
Peak memory 347352 kb
Host smart-88d4c0aa-3363-4036-b71d-a8523170b70b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1244080321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1244080321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.213283110
Short name T51
Test name
Test status
Simulation time 169491444 ps
CPU time 2.87 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 223740 kb
Host smart-bffa7acb-6332-468f-bb97-f18459d83078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213283110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.213283
110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.2247276998
Short name T4
Test name
Test status
Simulation time 797054558 ps
CPU time 8.35 seconds
Started Jul 14 05:40:59 PM PDT 24
Finished Jul 14 05:41:08 PM PDT 24
Peak memory 222000 kb
Host smart-d94de3cd-d887-4b7c-a316-23b82f18c044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247276998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2247276998 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2016662025
Short name T10
Test name
Test status
Simulation time 3323205539 ps
CPU time 45.42 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:35:16 PM PDT 24
Peak memory 254752 kb
Host smart-32b562a2-7e02-4388-9684-f8e6a3f1b215
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016662025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2016662025 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/28.kmac_key_error.41541813
Short name T19
Test name
Test status
Simulation time 1234492001 ps
CPU time 6.51 seconds
Started Jul 14 05:38:28 PM PDT 24
Finished Jul 14 05:38:35 PM PDT 24
Peak memory 207280 kb
Host smart-c2d537ef-d086-4b70-bec6-cc38bbd90864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41541813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.41541813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_error.2342837400
Short name T24
Test name
Test status
Simulation time 73228924890 ps
CPU time 417.44 seconds
Started Jul 14 05:36:35 PM PDT 24
Finished Jul 14 05:43:33 PM PDT 24
Peak memory 264856 kb
Host smart-d8aa180e-15c4-4970-8521-3541edb22793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342837400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2342837400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1967772778
Short name T107
Test name
Test status
Simulation time 1856192002 ps
CPU time 2.56 seconds
Started Jul 14 06:40:04 PM PDT 24
Finished Jul 14 06:40:09 PM PDT 24
Peak memory 215588 kb
Host smart-062b9627-ceb1-425d-8b84-5daeacb7b73d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967772778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1967772778 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.57545091
Short name T8
Test name
Test status
Simulation time 269414392 ps
CPU time 19.08 seconds
Started Jul 14 05:35:20 PM PDT 24
Finished Jul 14 05:35:39 PM PDT 24
Peak memory 231968 kb
Host smart-9decbf5a-a62a-44ba-81c3-84ae553e4083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57545091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.57545091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2937059756
Short name T1120
Test name
Test status
Simulation time 29227756 ps
CPU time 1.24 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:29 PM PDT 24
Peak memory 215864 kb
Host smart-38703769-cffd-4488-9448-28641a1f46b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937059756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2937059756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.902275725
Short name T7
Test name
Test status
Simulation time 90315970 ps
CPU time 1.16 seconds
Started Jul 14 05:35:18 PM PDT 24
Finished Jul 14 05:35:20 PM PDT 24
Peak memory 215504 kb
Host smart-f2e3c968-5797-40af-acd8-552514ece304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902275725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.902275725 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.2775985700
Short name T164
Test name
Test status
Simulation time 14102030 ps
CPU time 0.79 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 207056 kb
Host smart-88e140d9-b87c-4637-9abf-b40046b9b017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775985700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2775985700 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/default/34.kmac_alert_test.2550573154
Short name T46
Test name
Test status
Simulation time 49473299 ps
CPU time 0.76 seconds
Started Jul 14 05:40:19 PM PDT 24
Finished Jul 14 05:40:20 PM PDT 24
Peak memory 205228 kb
Host smart-5972945c-f34e-4d92-bcb7-b94225cbfb24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550573154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2550573154 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.548432111
Short name T175
Test name
Test status
Simulation time 246514305147 ps
CPU time 4171.14 seconds
Started Jul 14 05:33:58 PM PDT 24
Finished Jul 14 06:43:30 PM PDT 24
Peak memory 561588 kb
Host smart-a1d036f9-7159-4d61-a48a-67740dbdfc8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=548432111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.548432111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3118360310
Short name T136
Test name
Test status
Simulation time 28393193 ps
CPU time 1.19 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:27 PM PDT 24
Peak memory 215456 kb
Host smart-40e66046-7ce6-42bc-a338-a4b0a2b2dde7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118360310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.3118360310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.788514967
Short name T31
Test name
Test status
Simulation time 50576604 ps
CPU time 1.4 seconds
Started Jul 14 05:46:49 PM PDT 24
Finished Jul 14 05:46:50 PM PDT 24
Peak memory 215516 kb
Host smart-40a914e2-a42e-4aad-bfb3-ea60717da7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788514967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.788514967 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.4052717269
Short name T80
Test name
Test status
Simulation time 238887987 ps
CPU time 1.18 seconds
Started Jul 14 05:34:48 PM PDT 24
Finished Jul 14 05:34:50 PM PDT 24
Peak memory 215520 kb
Host smart-49406b20-aaf7-49f2-a815-83061499ceec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052717269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.4052717269 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3932636867
Short name T96
Test name
Test status
Simulation time 128109559 ps
CPU time 1.31 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:27 PM PDT 24
Peak memory 215988 kb
Host smart-00e4604b-e026-47de-8860-f39db68da32b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932636867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.3932636867 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3527019462
Short name T111
Test name
Test status
Simulation time 569243170 ps
CPU time 3.27 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:20 PM PDT 24
Peak memory 215656 kb
Host smart-c2a9c9d3-b300-4ccf-b3d7-3764a75a6a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527019462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3527019462 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1880714704
Short name T171
Test name
Test status
Simulation time 371009311 ps
CPU time 3.92 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:19 PM PDT 24
Peak memory 215792 kb
Host smart-23bc282a-7b34-4740-9ea9-c3a93dad02bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880714704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.18807
14704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.kmac_error.3367215312
Short name T28
Test name
Test status
Simulation time 14241207388 ps
CPU time 264.44 seconds
Started Jul 14 05:34:24 PM PDT 24
Finished Jul 14 05:38:49 PM PDT 24
Peak memory 256224 kb
Host smart-3119c5a0-c197-4d88-9aba-57033d20e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367215312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3367215312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_burst_write.1229023516
Short name T905
Test name
Test status
Simulation time 17563704604 ps
CPU time 782.22 seconds
Started Jul 14 05:35:03 PM PDT 24
Finished Jul 14 05:48:06 PM PDT 24
Peak memory 233564 kb
Host smart-d7e007be-cf40-4ac2-b1b5-9b1dbc3b2d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229023516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1229023516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.2428503744
Short name T159
Test name
Test status
Simulation time 601380333871 ps
CPU time 3964.13 seconds
Started Jul 14 05:34:51 PM PDT 24
Finished Jul 14 06:40:56 PM PDT 24
Peak memory 554840 kb
Host smart-db52cb73-031f-4f68-8159-b6c58d1abd2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2428503744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2428503744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_stress_all.504043774
Short name T22
Test name
Test status
Simulation time 17974075619 ps
CPU time 1275.08 seconds
Started Jul 14 05:37:00 PM PDT 24
Finished Jul 14 05:58:16 PM PDT 24
Peak memory 359960 kb
Host smart-ecb0627a-0fac-4e3d-a09c-29140db76c13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=504043774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.504043774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.2501960750
Short name T165
Test name
Test status
Simulation time 14803813 ps
CPU time 0.75 seconds
Started Jul 14 06:40:21 PM PDT 24
Finished Jul 14 06:40:28 PM PDT 24
Peak memory 207032 kb
Host smart-3a3db1a5-80c9-4fc2-9aa3-f9f41ba598de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501960750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2501960750 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.222576131
Short name T161
Test name
Test status
Simulation time 19468485845 ps
CPU time 1460.65 seconds
Started Jul 14 05:34:27 PM PDT 24
Finished Jul 14 05:58:49 PM PDT 24
Peak memory 377856 kb
Host smart-57833222-6c3d-4e3b-9387-55a4c9870bb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=222576131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.222576131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2991767408
Short name T116
Test name
Test status
Simulation time 65698292 ps
CPU time 2.17 seconds
Started Jul 14 06:40:18 PM PDT 24
Finished Jul 14 06:40:24 PM PDT 24
Peak memory 223780 kb
Host smart-3d8f2f68-2510-413d-8207-e53ff6d34b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991767408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2991767408 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3415738015
Short name T300
Test name
Test status
Simulation time 14801665424 ps
CPU time 61 seconds
Started Jul 14 05:34:09 PM PDT 24
Finished Jul 14 05:35:11 PM PDT 24
Peak memory 216724 kb
Host smart-1cd02170-cfff-4230-b03e-1d956b5f6924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415738015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3415738015 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/20.kmac_sideload.69004259
Short name T285
Test name
Test status
Simulation time 13499300603 ps
CPU time 328.25 seconds
Started Jul 14 05:36:27 PM PDT 24
Finished Jul 14 05:41:56 PM PDT 24
Peak memory 248436 kb
Host smart-e8c3832e-6c39-4f2c-a3d1-a43b444f2364
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69004259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.69004259 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1014019216
Short name T131
Test name
Test status
Simulation time 335492825 ps
CPU time 2.96 seconds
Started Jul 14 06:40:29 PM PDT 24
Finished Jul 14 06:40:39 PM PDT 24
Peak memory 207416 kb
Host smart-48203668-5a4e-4fe8-967a-2d77f12e93da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014019216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1014
019216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1999033505
Short name T132
Test name
Test status
Simulation time 248931730 ps
CPU time 4.26 seconds
Started Jul 14 06:42:08 PM PDT 24
Finished Jul 14 06:42:13 PM PDT 24
Peak memory 215364 kb
Host smart-6939bb8e-a2c6-4793-9265-817f4fd797af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999033505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1999
033505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/23.kmac_app.821332340
Short name T446
Test name
Test status
Simulation time 13781743531 ps
CPU time 253.38 seconds
Started Jul 14 05:36:54 PM PDT 24
Finished Jul 14 05:41:08 PM PDT 24
Peak memory 241464 kb
Host smart-d3d9e69f-fb37-4e7c-93a9-74ff5b2592fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821332340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.821332340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2587001755
Short name T118
Test name
Test status
Simulation time 178199565 ps
CPU time 2.34 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 223872 kb
Host smart-0b7ebba8-a2c9-4239-8d79-2ae42264dff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587001755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2587001755 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1117217881
Short name T1201
Test name
Test status
Simulation time 782417113 ps
CPU time 9.36 seconds
Started Jul 14 06:40:07 PM PDT 24
Finished Jul 14 06:40:21 PM PDT 24
Peak memory 215532 kb
Host smart-86f0982e-5290-44ea-9213-51a98e51fa8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117217881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1117217
881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3959468482
Short name T1088
Test name
Test status
Simulation time 964615911 ps
CPU time 19.26 seconds
Started Jul 14 06:40:13 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 207488 kb
Host smart-c193772d-baf4-4482-ba72-90205b973408
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959468482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3959468
482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1694953622
Short name T1122
Test name
Test status
Simulation time 25114816 ps
CPU time 0.92 seconds
Started Jul 14 06:40:11 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 207136 kb
Host smart-607fa054-a890-4140-bd55-71d4b8eee26c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694953622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1694953
622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3915909018
Short name T1185
Test name
Test status
Simulation time 38326335 ps
CPU time 2.32 seconds
Started Jul 14 06:40:03 PM PDT 24
Finished Jul 14 06:40:06 PM PDT 24
Peak memory 216724 kb
Host smart-67840bdc-2223-45a0-93ed-6b6c39b90abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915909018 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3915909018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2667890550
Short name T1214
Test name
Test status
Simulation time 43937891 ps
CPU time 1.14 seconds
Started Jul 14 06:40:03 PM PDT 24
Finished Jul 14 06:40:06 PM PDT 24
Peak memory 207344 kb
Host smart-71fd87c7-b125-4ff5-bb05-e23edba19d91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667890550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2667890550 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2001721182
Short name T1099
Test name
Test status
Simulation time 15472062 ps
CPU time 0.8 seconds
Started Jul 14 06:40:05 PM PDT 24
Finished Jul 14 06:40:09 PM PDT 24
Peak memory 207052 kb
Host smart-d44f26be-9c1f-4c7f-aa93-1a486561d136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001721182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2001721182 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3936454690
Short name T1110
Test name
Test status
Simulation time 52088954 ps
CPU time 1.19 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:17 PM PDT 24
Peak memory 215512 kb
Host smart-0ee15553-94ed-417c-9da2-b750e1d6f66a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936454690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3936454690 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.412732658
Short name T1086
Test name
Test status
Simulation time 31900043 ps
CPU time 0.74 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:17 PM PDT 24
Peak memory 207152 kb
Host smart-4bb15e11-11bc-41f3-a224-91f7cfba604a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412732658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.412732658 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3707163168
Short name T1176
Test name
Test status
Simulation time 137191470 ps
CPU time 1.61 seconds
Started Jul 14 06:40:04 PM PDT 24
Finished Jul 14 06:40:08 PM PDT 24
Peak memory 215796 kb
Host smart-66dfb3e0-8e3f-4509-bb2a-8711447eca12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707163168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.3707163168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.422056179
Short name T1216
Test name
Test status
Simulation time 75303082 ps
CPU time 1.4 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:17 PM PDT 24
Peak memory 215948 kb
Host smart-3dcb9bf6-6b04-4b0a-92f2-a60e3aff0ddf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422056179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_e
rrors.422056179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1762781218
Short name T1119
Test name
Test status
Simulation time 753273438 ps
CPU time 2.65 seconds
Started Jul 14 06:40:08 PM PDT 24
Finished Jul 14 06:40:16 PM PDT 24
Peak memory 223628 kb
Host smart-2df8379a-b592-4327-8c53-9c9c783132c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762781218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.1762781218 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1303104089
Short name T1172
Test name
Test status
Simulation time 219053416 ps
CPU time 3.01 seconds
Started Jul 14 06:40:08 PM PDT 24
Finished Jul 14 06:40:17 PM PDT 24
Peak memory 215536 kb
Host smart-35cea61c-7afc-491a-a951-16137e4faf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303104089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1303104089 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.696831824
Short name T109
Test name
Test status
Simulation time 375882017 ps
CPU time 2.8 seconds
Started Jul 14 06:40:03 PM PDT 24
Finished Jul 14 06:40:06 PM PDT 24
Peak memory 215628 kb
Host smart-4fd31bb9-afa2-4919-ba51-df1603b0ffe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696831824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.696831
824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1064386117
Short name T1114
Test name
Test status
Simulation time 201934414 ps
CPU time 4.66 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:29 PM PDT 24
Peak memory 215500 kb
Host smart-f4d2245e-f6f9-4ee8-889a-eb88dfd33936
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064386117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1064386
117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1728841513
Short name T1141
Test name
Test status
Simulation time 3025032548 ps
CPU time 11 seconds
Started Jul 14 06:40:08 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 207472 kb
Host smart-dd801cf0-c549-4ddd-9b27-6595b9ed7aa8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728841513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1728841
513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1027501488
Short name T1231
Test name
Test status
Simulation time 54398763 ps
CPU time 1.05 seconds
Started Jul 14 06:40:17 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 207416 kb
Host smart-a2187214-1891-4e60-8521-f0aaa9e19699
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027501488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1027501
488 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3536273232
Short name T1115
Test name
Test status
Simulation time 46254565 ps
CPU time 1.83 seconds
Started Jul 14 06:40:04 PM PDT 24
Finished Jul 14 06:40:08 PM PDT 24
Peak memory 223720 kb
Host smart-e9b7d92a-6c66-4bb8-8c44-4615f18903a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536273232 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.3536273232 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2052345495
Short name T1096
Test name
Test status
Simulation time 16339305 ps
CPU time 1.11 seconds
Started Jul 14 06:40:08 PM PDT 24
Finished Jul 14 06:40:15 PM PDT 24
Peak memory 215604 kb
Host smart-ee722133-4fcc-4349-a5e3-5771feb6d445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052345495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2052345495 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.211788986
Short name T1162
Test name
Test status
Simulation time 26056987 ps
CPU time 0.78 seconds
Started Jul 14 06:40:09 PM PDT 24
Finished Jul 14 06:40:15 PM PDT 24
Peak memory 207028 kb
Host smart-c0f10ba2-e593-43a2-a641-8a55e7b01b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211788986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.211788986 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3718011685
Short name T1140
Test name
Test status
Simulation time 31980395 ps
CPU time 0.74 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:16 PM PDT 24
Peak memory 207092 kb
Host smart-768d9fc5-a0d8-4465-a5c6-5755fab5c61b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718011685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3718011685
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.741686942
Short name T1139
Test name
Test status
Simulation time 94502958 ps
CPU time 2.39 seconds
Started Jul 14 06:40:15 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 215832 kb
Host smart-256c8f57-5e74-423a-b887-8951173dc174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741686942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_
outstanding.741686942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4281732837
Short name T1149
Test name
Test status
Simulation time 113990684 ps
CPU time 1.11 seconds
Started Jul 14 06:40:07 PM PDT 24
Finished Jul 14 06:40:13 PM PDT 24
Peak memory 215928 kb
Host smart-fec1e331-7dc1-45f0-88b8-4c802105b47f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281732837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.4281732837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3742220592
Short name T1125
Test name
Test status
Simulation time 508232829 ps
CPU time 2.87 seconds
Started Jul 14 06:40:05 PM PDT 24
Finished Jul 14 06:40:11 PM PDT 24
Peak memory 215916 kb
Host smart-0acedf97-ca5a-47a4-b041-37db12fe3160
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742220592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3742220592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2152027604
Short name T52
Test name
Test status
Simulation time 60359504 ps
CPU time 2.47 seconds
Started Jul 14 06:40:06 PM PDT 24
Finished Jul 14 06:40:12 PM PDT 24
Peak memory 215572 kb
Host smart-8fa2d25a-055a-40a6-812a-47576a32ad38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152027604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.21520
27604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1780666514
Short name T105
Test name
Test status
Simulation time 157899327 ps
CPU time 1.54 seconds
Started Jul 14 06:40:21 PM PDT 24
Finished Jul 14 06:40:28 PM PDT 24
Peak memory 215624 kb
Host smart-377a5fe4-3bb0-47dd-875c-3b382d212886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780666514 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1780666514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1625281929
Short name T1116
Test name
Test status
Simulation time 305077030 ps
CPU time 1 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207216 kb
Host smart-d457c74d-000e-46c9-99df-32fa86ff2eb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625281929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1625281929 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.1788906074
Short name T1207
Test name
Test status
Simulation time 18746078 ps
CPU time 0.74 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 207080 kb
Host smart-e1bbaba6-65ea-49cd-bb18-bfae5c865794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788906074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1788906074 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.562357519
Short name T1117
Test name
Test status
Simulation time 247746612 ps
CPU time 1.64 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:24 PM PDT 24
Peak memory 216120 kb
Host smart-9f8e68a1-d1fc-4ffd-9704-611f8f347782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562357519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr
_outstanding.562357519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.572765093
Short name T1180
Test name
Test status
Simulation time 38308859 ps
CPU time 1.3 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 215864 kb
Host smart-93e6467b-4dfc-42d3-931f-ea3058b9cf15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572765093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_
errors.572765093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.750031625
Short name T1228
Test name
Test status
Simulation time 107299405 ps
CPU time 1.6 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 215896 kb
Host smart-2af9a984-8c2e-4402-9c1d-d8a39d3b444d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750031625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac
_shadow_reg_errors_with_csr_rw.750031625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.817503511
Short name T1143
Test name
Test status
Simulation time 24565100 ps
CPU time 1.37 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 217328 kb
Host smart-a7dfcf7a-faa2-4591-961a-cdb16ba14f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817503511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.817503511 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2394573909
Short name T1208
Test name
Test status
Simulation time 78952949 ps
CPU time 2.25 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 216976 kb
Host smart-d7b9a574-53a5-4ad8-8029-81cd15ce5474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394573909 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2394573909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2355172935
Short name T1188
Test name
Test status
Simulation time 82169407 ps
CPU time 0.93 seconds
Started Jul 14 06:40:26 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 207156 kb
Host smart-9776c7da-40cd-456e-93f4-17a416f736e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355172935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2355172935 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2499648052
Short name T94
Test name
Test status
Simulation time 206830792 ps
CPU time 1.53 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 215512 kb
Host smart-e935157f-cf56-427f-a7d0-3b9e9aa09536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499648052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.2499648052 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.640079763
Short name T1174
Test name
Test status
Simulation time 43955282 ps
CPU time 0.96 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 215752 kb
Host smart-2174ed85-5210-4865-adbe-8e4bd04dbfd2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640079763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_
errors.640079763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.143263438
Short name T1177
Test name
Test status
Simulation time 1138741218 ps
CPU time 2.52 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 215900 kb
Host smart-53aca7dd-9e23-4a04-8367-7cef5e27da16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143263438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac
_shadow_reg_errors_with_csr_rw.143263438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1446899223
Short name T106
Test name
Test status
Simulation time 34994199 ps
CPU time 2.09 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 223664 kb
Host smart-2b7473ad-d49e-4984-9050-634da09c27be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446899223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1446899223 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2025924096
Short name T130
Test name
Test status
Simulation time 145512821 ps
CPU time 2.78 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 207368 kb
Host smart-1b1d5306-4e26-47ba-8a37-aeec2c948d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025924096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2025
924096 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3836148758
Short name T1166
Test name
Test status
Simulation time 89947563 ps
CPU time 1.61 seconds
Started Jul 14 06:40:15 PM PDT 24
Finished Jul 14 06:40:21 PM PDT 24
Peak memory 215636 kb
Host smart-82c1c1c3-fd52-48ed-8f1b-c88043fce151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836148758 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.3836148758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3486629721
Short name T1095
Test name
Test status
Simulation time 31293322 ps
CPU time 0.92 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207100 kb
Host smart-5ad68150-1271-48b7-8af7-029c79085006
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486629721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3486629721 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.510191854
Short name T166
Test name
Test status
Simulation time 13454318 ps
CPU time 0.74 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207024 kb
Host smart-fe7ea723-3947-4b43-b3c8-b640830fca28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510191854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.510191854 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.511760612
Short name T1097
Test name
Test status
Simulation time 87204730 ps
CPU time 1.43 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 215536 kb
Host smart-411744ba-3aa8-4f81-b245-0c565131cd62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511760612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr
_outstanding.511760612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1005272664
Short name T1232
Test name
Test status
Simulation time 69795908 ps
CPU time 0.99 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 207504 kb
Host smart-ed86f5d3-b5bb-419d-aa7e-0f3013f3e39f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005272664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1005272664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3583573666
Short name T1215
Test name
Test status
Simulation time 140241039 ps
CPU time 2.83 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 215980 kb
Host smart-85546693-5e2e-4256-913c-8c13bba95c8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583573666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.3583573666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1262866949
Short name T108
Test name
Test status
Simulation time 202326963 ps
CPU time 2.73 seconds
Started Jul 14 06:40:21 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 215532 kb
Host smart-60808547-efe7-4646-b9fa-95cbcde4bbc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262866949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1262
866949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2074399577
Short name T1170
Test name
Test status
Simulation time 315284939 ps
CPU time 2.44 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 223752 kb
Host smart-6c86a247-4e85-43e1-9b85-6c52c73a172c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074399577 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2074399577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.4137152973
Short name T149
Test name
Test status
Simulation time 145621461 ps
CPU time 1.21 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 207380 kb
Host smart-3a6ee15c-edb2-472b-9dc5-09ce89926a56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137152973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.4137152973 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.2812614402
Short name T1145
Test name
Test status
Simulation time 13494671 ps
CPU time 0.81 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:28 PM PDT 24
Peak memory 207056 kb
Host smart-2e490e8c-2446-46d2-b334-ae57af5f71d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812614402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2812614402 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3726000409
Short name T1134
Test name
Test status
Simulation time 69084982 ps
CPU time 1.83 seconds
Started Jul 14 06:42:08 PM PDT 24
Finished Jul 14 06:42:10 PM PDT 24
Peak memory 215664 kb
Host smart-028933ba-1825-41f0-8829-4010860b22f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726000409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3726000409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3472737440
Short name T1190
Test name
Test status
Simulation time 42354401 ps
CPU time 1.16 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:27 PM PDT 24
Peak memory 215992 kb
Host smart-35198a64-19f3-4391-990b-f7134f0fdc41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472737440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3472737440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1483147836
Short name T1221
Test name
Test status
Simulation time 82304309 ps
CPU time 1.93 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 215972 kb
Host smart-b1b1a52c-34bf-4c00-b927-803948eb916f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483147836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.1483147836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1613532213
Short name T127
Test name
Test status
Simulation time 148003351 ps
CPU time 2.37 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 215548 kb
Host smart-536a6aaa-b9cb-44d8-88af-e09421a33697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613532213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1613532213 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2540552957
Short name T126
Test name
Test status
Simulation time 254946739 ps
CPU time 4.63 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 215600 kb
Host smart-34ecedff-92b6-4a94-9c2d-8b2662bb2043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540552957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2540
552957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.613542252
Short name T1194
Test name
Test status
Simulation time 92006820 ps
CPU time 1.63 seconds
Started Jul 14 06:40:21 PM PDT 24
Finished Jul 14 06:40:29 PM PDT 24
Peak memory 223820 kb
Host smart-ad40a185-3eee-49c6-a8c5-4c7e8ffcdce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613542252 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.613542252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.250243157
Short name T1156
Test name
Test status
Simulation time 33981468 ps
CPU time 1.12 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:27 PM PDT 24
Peak memory 207432 kb
Host smart-9d300ba4-1fde-4be8-9df8-9fb9563caa37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250243157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.250243157 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.2531516124
Short name T147
Test name
Test status
Simulation time 130660829 ps
CPU time 0.78 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207024 kb
Host smart-c84840e0-6972-45c6-9414-ea2a6b42743b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531516124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2531516124 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2264527083
Short name T1123
Test name
Test status
Simulation time 99946369 ps
CPU time 2.42 seconds
Started Jul 14 06:40:29 PM PDT 24
Finished Jul 14 06:40:39 PM PDT 24
Peak memory 216008 kb
Host smart-a22e35f3-7b2b-43c1-9760-d7ba24e3d292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264527083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.2264527083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.537925186
Short name T1158
Test name
Test status
Simulation time 41151245 ps
CPU time 1.14 seconds
Started Jul 14 06:40:28 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 215924 kb
Host smart-d48a4bbc-d24f-42f1-aa6f-b0b55af41d7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537925186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_
errors.537925186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1385110315
Short name T1211
Test name
Test status
Simulation time 274485301 ps
CPU time 2.5 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 215964 kb
Host smart-8007224c-9da5-41d7-91f5-56a171e4ba3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385110315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.1385110315 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.283368263
Short name T1226
Test name
Test status
Simulation time 316326223 ps
CPU time 5.15 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 215768 kb
Host smart-02cde6a9-111a-40d3-99ca-ee02751ac2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283368263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.28336
8263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3033351871
Short name T1169
Test name
Test status
Simulation time 47947437 ps
CPU time 1.8 seconds
Started Jul 14 06:40:29 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 223828 kb
Host smart-643d0cee-b1d3-4398-a677-771a8f5091ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033351871 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.3033351871 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.4272621610
Short name T1150
Test name
Test status
Simulation time 17634181 ps
CPU time 1.04 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 215560 kb
Host smart-61ebf38d-6383-4f7f-ab1c-a178e00f09af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272621610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.4272621610 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1290639804
Short name T119
Test name
Test status
Simulation time 15913972 ps
CPU time 0.8 seconds
Started Jul 14 06:40:28 PM PDT 24
Finished Jul 14 06:40:36 PM PDT 24
Peak memory 207064 kb
Host smart-9eeda7be-a1cf-4e55-9281-76de73c417c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290639804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1290639804 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1644707272
Short name T1098
Test name
Test status
Simulation time 232114938 ps
CPU time 1.45 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 215608 kb
Host smart-166e5321-7dfd-4be4-8785-f7d9de535633
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644707272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1644707272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2322887778
Short name T144
Test name
Test status
Simulation time 156200960 ps
CPU time 1.23 seconds
Started Jul 14 06:40:18 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 215912 kb
Host smart-7f5589b2-03e3-4da3-b761-bbfc7334dc85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322887778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.2322887778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1193352182
Short name T1183
Test name
Test status
Simulation time 106288553 ps
CPU time 1.59 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 215920 kb
Host smart-a0a5de89-cf3c-4b91-8bfb-2144c9a71d03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193352182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.1193352182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2170881782
Short name T115
Test name
Test status
Simulation time 34505491 ps
CPU time 1.79 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:27 PM PDT 24
Peak memory 215512 kb
Host smart-08894f7a-592f-4262-8547-57a93f9352dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170881782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2170881782 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2264988657
Short name T1236
Test name
Test status
Simulation time 103843943 ps
CPU time 2.08 seconds
Started Jul 14 06:40:15 PM PDT 24
Finished Jul 14 06:40:22 PM PDT 24
Peak memory 216620 kb
Host smart-8434d079-84ee-420e-bade-e457996b5d45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264988657 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2264988657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2525993540
Short name T1163
Test name
Test status
Simulation time 21932867 ps
CPU time 0.94 seconds
Started Jul 14 06:40:30 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 207012 kb
Host smart-9945a511-2f54-4752-8c0d-3b6409668f4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525993540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2525993540 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.968629065
Short name T1106
Test name
Test status
Simulation time 11302833 ps
CPU time 0.75 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 206976 kb
Host smart-3a07c9c4-2afb-4541-a70d-d56ad476e5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968629065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.968629065 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2417921677
Short name T1148
Test name
Test status
Simulation time 61331613 ps
CPU time 1.6 seconds
Started Jul 14 06:40:28 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 215652 kb
Host smart-6be46e0b-c98e-4274-b07a-db1264dcce7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417921677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.2417921677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1528927069
Short name T143
Test name
Test status
Simulation time 124524810 ps
CPU time 2.86 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 215928 kb
Host smart-1a068660-5145-419a-9338-0a9db42374f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528927069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.1528927069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1327454796
Short name T1179
Test name
Test status
Simulation time 116669882 ps
CPU time 1.68 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 215452 kb
Host smart-2e49c377-5f98-4013-8549-bd66121fc689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327454796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1327454796 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.76245863
Short name T170
Test name
Test status
Simulation time 1419436788 ps
CPU time 4.83 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 215600 kb
Host smart-bdcb55e0-95de-458a-829b-8891b2456f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76245863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.762458
63 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2030768806
Short name T1233
Test name
Test status
Simulation time 112264659 ps
CPU time 1.48 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 223852 kb
Host smart-3561cd00-2c37-4871-92d7-8d519a314bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030768806 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2030768806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.4065994526
Short name T1168
Test name
Test status
Simulation time 44236645 ps
CPU time 0.87 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 207236 kb
Host smart-a8fc7017-90df-4ea3-8046-42d2edfeec3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065994526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.4065994526 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3670889131
Short name T1152
Test name
Test status
Simulation time 48220952 ps
CPU time 0.79 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 207032 kb
Host smart-1617b54b-8f03-467d-a463-ec4e681c9fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670889131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3670889131 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1176399167
Short name T1203
Test name
Test status
Simulation time 95680511 ps
CPU time 1.47 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 215564 kb
Host smart-5361fee2-294e-49c6-9626-dd0ac0572ee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176399167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.1176399167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.902576590
Short name T1213
Test name
Test status
Simulation time 55771500 ps
CPU time 1.44 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:36 PM PDT 24
Peak memory 215932 kb
Host smart-dd9257e0-7982-47c5-a38f-9f117f8f9134
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902576590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_
errors.902576590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.421096948
Short name T90
Test name
Test status
Simulation time 58453904 ps
CPU time 1.78 seconds
Started Jul 14 06:40:21 PM PDT 24
Finished Jul 14 06:40:28 PM PDT 24
Peak memory 215892 kb
Host smart-50f1aee7-d107-411e-96a4-f9d54da522f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421096948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac
_shadow_reg_errors_with_csr_rw.421096948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1256325001
Short name T117
Test name
Test status
Simulation time 250849311 ps
CPU time 1.6 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 215724 kb
Host smart-10ee26cd-de39-4a53-83d5-d0413cd14678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256325001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1256325001 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3436231272
Short name T125
Test name
Test status
Simulation time 69303962 ps
CPU time 2.46 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 218220 kb
Host smart-c0681ed7-729b-48cd-8416-c6a5553c0a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436231272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3436
231272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2086524010
Short name T1132
Test name
Test status
Simulation time 33690384 ps
CPU time 2.4 seconds
Started Jul 14 06:40:21 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 217268 kb
Host smart-8c775f1d-e388-42fc-80d0-4ad7a7e2c747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086524010 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2086524010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2971640827
Short name T148
Test name
Test status
Simulation time 26392526 ps
CPU time 1.03 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207184 kb
Host smart-e2e0b7cb-79f9-419c-ad4c-830d10448a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971640827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2971640827 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3561760356
Short name T1155
Test name
Test status
Simulation time 161987996 ps
CPU time 2.22 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 216108 kb
Host smart-62b09eaf-6823-4b98-a5bc-8fd99e958ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561760356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.3561760356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1564462142
Short name T1144
Test name
Test status
Simulation time 27128080 ps
CPU time 0.9 seconds
Started Jul 14 06:41:57 PM PDT 24
Finished Jul 14 06:42:02 PM PDT 24
Peak memory 206384 kb
Host smart-049954ad-2dff-4704-accd-d3e8eb2ea9e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564462142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1564462142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1674571236
Short name T1137
Test name
Test status
Simulation time 80001385 ps
CPU time 2.12 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 215832 kb
Host smart-d66f8c36-85b2-4833-a9b2-e80d1bd9ad5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674571236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.1674571236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1045236001
Short name T122
Test name
Test status
Simulation time 125169395 ps
CPU time 3.2 seconds
Started Jul 14 06:40:28 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 215572 kb
Host smart-8ad86130-c5e4-4b72-a5fb-8f762a965ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045236001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1045236001 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2008816985
Short name T173
Test name
Test status
Simulation time 310299749 ps
CPU time 5.09 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 215536 kb
Host smart-5ff2f34f-3750-4082-bcf8-fd3e3ffe153a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008816985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2008
816985 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2323358369
Short name T1159
Test name
Test status
Simulation time 87350932 ps
CPU time 1.59 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:29 PM PDT 24
Peak memory 216132 kb
Host smart-da221954-fbd9-4397-8cb5-7497214b3e47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323358369 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2323358369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.4259055793
Short name T1234
Test name
Test status
Simulation time 17801936 ps
CPU time 1.09 seconds
Started Jul 14 06:40:17 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 207452 kb
Host smart-8d6753d5-9c53-4376-bb46-f3903c481538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259055793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4259055793 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.904158389
Short name T1101
Test name
Test status
Simulation time 59908688 ps
CPU time 0.78 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 207024 kb
Host smart-31062ef5-5e5d-453a-9b34-2cb413efc826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904158389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.904158389 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3805876597
Short name T1113
Test name
Test status
Simulation time 35393672 ps
CPU time 2.07 seconds
Started Jul 14 06:40:29 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 215896 kb
Host smart-49a96127-5b01-43bb-944c-b0ac9df3a76c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805876597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.3805876597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1823295146
Short name T1102
Test name
Test status
Simulation time 27346633 ps
CPU time 0.96 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 215724 kb
Host smart-3fd0f5b2-edc0-4216-b440-bf48d84aa789
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823295146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.1823295146 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.114141530
Short name T92
Test name
Test status
Simulation time 33597691 ps
CPU time 1.68 seconds
Started Jul 14 06:40:28 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 215924 kb
Host smart-b65cd7d1-3b4b-4e0c-8e29-f089010bab51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114141530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac
_shadow_reg_errors_with_csr_rw.114141530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.909553272
Short name T168
Test name
Test status
Simulation time 80025837 ps
CPU time 1.4 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:36 PM PDT 24
Peak memory 215628 kb
Host smart-be5af2f2-1bde-4c68-9037-b7773cf98993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909553272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.909553272 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.379118373
Short name T172
Test name
Test status
Simulation time 119945196 ps
CPU time 2.88 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 223744 kb
Host smart-5b0eed3f-d7f1-4dad-a67b-585420ddeb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379118373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.37911
8373 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1590032778
Short name T1092
Test name
Test status
Simulation time 136845636 ps
CPU time 7.86 seconds
Started Jul 14 06:40:13 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 207372 kb
Host smart-3eeba4fb-9a1a-4ec9-b08c-c4938230eed8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590032778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1590032
778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4031547780
Short name T1209
Test name
Test status
Simulation time 602539801 ps
CPU time 9.39 seconds
Started Jul 14 06:40:16 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 207356 kb
Host smart-10473d0a-b96e-48fc-9928-e582706a7544
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031547780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.4031547
780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.4048544384
Short name T1111
Test name
Test status
Simulation time 34435899 ps
CPU time 1.04 seconds
Started Jul 14 06:40:13 PM PDT 24
Finished Jul 14 06:40:19 PM PDT 24
Peak memory 207416 kb
Host smart-924f3c32-5f62-4036-87e2-0d3db946cbf3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048544384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.4048544
384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.899512053
Short name T1210
Test name
Test status
Simulation time 38384834 ps
CPU time 1.55 seconds
Started Jul 14 06:40:04 PM PDT 24
Finished Jul 14 06:40:08 PM PDT 24
Peak memory 215528 kb
Host smart-fb039e4f-1fb8-430b-8531-49e0ff6c6d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899512053 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.899512053 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1984493809
Short name T1112
Test name
Test status
Simulation time 60184700 ps
CPU time 0.92 seconds
Started Jul 14 06:40:03 PM PDT 24
Finished Jul 14 06:40:05 PM PDT 24
Peak memory 207208 kb
Host smart-841b7fb8-128b-47f7-891d-f75c928e30bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984493809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1984493809 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.3810203566
Short name T1103
Test name
Test status
Simulation time 30124108 ps
CPU time 0.73 seconds
Started Jul 14 06:40:17 PM PDT 24
Finished Jul 14 06:40:22 PM PDT 24
Peak memory 207016 kb
Host smart-d88fc358-d323-4ccb-a67a-053965d48f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810203566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3810203566 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.4085259091
Short name T138
Test name
Test status
Simulation time 413992008 ps
CPU time 1.58 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 215560 kb
Host smart-202b018e-efdc-44b3-8c06-75fca9c13aee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085259091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.4085259091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1442225730
Short name T1184
Test name
Test status
Simulation time 15620955 ps
CPU time 0.75 seconds
Started Jul 14 06:40:12 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 207160 kb
Host smart-a6ccd4c2-514e-4ca7-b45e-1d26a4670764
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442225730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1442225730
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2548596086
Short name T142
Test name
Test status
Simulation time 58984458 ps
CPU time 1.56 seconds
Started Jul 14 06:40:11 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 215848 kb
Host smart-6bc3759c-8559-44df-87d1-cf5e4e9007f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548596086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.2548596086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3703826751
Short name T91
Test name
Test status
Simulation time 45908670 ps
CPU time 1.11 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:17 PM PDT 24
Peak memory 215944 kb
Host smart-3502b899-cad4-4b5e-b5cb-97742871c024
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703826751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.3703826751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3239261084
Short name T100
Test name
Test status
Simulation time 365207393 ps
CPU time 2.26 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:27 PM PDT 24
Peak memory 216176 kb
Host smart-2f45b26d-2a86-4f68-a442-eba6950498c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239261084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.3239261084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.694078536
Short name T1191
Test name
Test status
Simulation time 44253393 ps
CPU time 1.5 seconds
Started Jul 14 06:40:05 PM PDT 24
Finished Jul 14 06:40:11 PM PDT 24
Peak memory 215548 kb
Host smart-e79d6af0-fcc8-4307-ad37-9aa131fa6f50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694078536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.694078536 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.4190716031
Short name T1225
Test name
Test status
Simulation time 20554100 ps
CPU time 0.75 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 207128 kb
Host smart-452976a7-eaae-44b8-9fb5-66d8220b090b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190716031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.4190716031 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.3570828823
Short name T1227
Test name
Test status
Simulation time 21914315 ps
CPU time 0.82 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207056 kb
Host smart-f891ffac-18fa-4e07-b45a-d26847248659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570828823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3570828823 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.756716397
Short name T1127
Test name
Test status
Simulation time 71163150 ps
CPU time 0.79 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207028 kb
Host smart-d6840806-049a-4c5d-8429-57acce87f670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756716397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.756716397 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2984348737
Short name T1107
Test name
Test status
Simulation time 147075473 ps
CPU time 0.82 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 207072 kb
Host smart-e3377368-b68b-42d9-82a5-65c39e64f6b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984348737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2984348737 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2725102855
Short name T146
Test name
Test status
Simulation time 12710468 ps
CPU time 0.74 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 207076 kb
Host smart-4643db90-a54c-4690-8211-ece6a30d2a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725102855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2725102855 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.3406035523
Short name T1118
Test name
Test status
Simulation time 51538263 ps
CPU time 0.77 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 207052 kb
Host smart-ba7dec76-f7c0-4474-9760-f4d8c76e714b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406035523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3406035523 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.3666987963
Short name T1105
Test name
Test status
Simulation time 39661472 ps
CPU time 0.76 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 206976 kb
Host smart-4a1cdb33-ea20-4081-9fee-db5891ee1766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666987963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3666987963 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.1563539325
Short name T1160
Test name
Test status
Simulation time 51959005 ps
CPU time 0.76 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 207080 kb
Host smart-4bb8564b-6a1f-4bf5-8b55-e2c28f39dda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563539325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1563539325 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.2205601156
Short name T1124
Test name
Test status
Simulation time 20942964 ps
CPU time 0.8 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 207068 kb
Host smart-270b44d8-9be0-4974-9eed-b786b365d6c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205601156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2205601156 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3823671848
Short name T1164
Test name
Test status
Simulation time 14595335 ps
CPU time 0.78 seconds
Started Jul 14 06:40:30 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 206892 kb
Host smart-917eabd3-76d4-40dc-ba41-0e289d5f8bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823671848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3823671848 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1208573173
Short name T1094
Test name
Test status
Simulation time 1736451066 ps
CPU time 9.5 seconds
Started Jul 14 06:40:05 PM PDT 24
Finished Jul 14 06:40:19 PM PDT 24
Peak memory 207412 kb
Host smart-f3dcc1c8-781c-44b4-ba50-3c9dcacd4a3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208573173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1208573
173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.462757918
Short name T1204
Test name
Test status
Simulation time 301130045 ps
CPU time 14.88 seconds
Started Jul 14 06:40:16 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 207352 kb
Host smart-21e1d633-12c9-4cfc-a37e-fb67dafa7021
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462757918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.46275791
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2344556186
Short name T1089
Test name
Test status
Simulation time 75142546 ps
CPU time 0.89 seconds
Started Jul 14 06:40:04 PM PDT 24
Finished Jul 14 06:40:07 PM PDT 24
Peak memory 207204 kb
Host smart-d5c80b60-ad32-4418-892d-81d22f7ef135
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344556186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2344556
186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3407632156
Short name T1219
Test name
Test status
Simulation time 61005817 ps
CPU time 1.37 seconds
Started Jul 14 06:40:11 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 215564 kb
Host smart-d0e64ded-970c-46ef-9039-ab0f27a10152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407632156 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3407632156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.4170408374
Short name T1093
Test name
Test status
Simulation time 27312511 ps
CPU time 1.17 seconds
Started Jul 14 06:40:11 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 207440 kb
Host smart-fb1e172f-439c-4af0-857c-22fbf456781c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170408374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4170408374 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1817455966
Short name T1186
Test name
Test status
Simulation time 20861445 ps
CPU time 0.81 seconds
Started Jul 14 06:40:17 PM PDT 24
Finished Jul 14 06:40:22 PM PDT 24
Peak memory 207072 kb
Host smart-9d97ffb0-2b9f-44e0-bfd2-1bf54feb82f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817455966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1817455966 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3690006453
Short name T135
Test name
Test status
Simulation time 51255910 ps
CPU time 1.08 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 215692 kb
Host smart-1c9f09da-3b7c-4fa1-8d82-fad6c107abb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690006453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.3690006453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1293278136
Short name T1091
Test name
Test status
Simulation time 33717360 ps
CPU time 0.73 seconds
Started Jul 14 06:40:16 PM PDT 24
Finished Jul 14 06:40:21 PM PDT 24
Peak memory 207160 kb
Host smart-0127987a-8a31-4c6a-88aa-767d047c951a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293278136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1293278136
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3963150047
Short name T145
Test name
Test status
Simulation time 208799525 ps
CPU time 2.56 seconds
Started Jul 14 06:40:18 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 215576 kb
Host smart-b1d40e1b-4b4d-4096-9330-c17fa1d07026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963150047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.3963150047 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.722284634
Short name T1130
Test name
Test status
Simulation time 65064716 ps
CPU time 1.02 seconds
Started Jul 14 06:40:14 PM PDT 24
Finished Jul 14 06:40:20 PM PDT 24
Peak memory 215888 kb
Host smart-933b3f40-f4df-4fd8-82e2-b258fe8c5145
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722284634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.722284634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3424791655
Short name T99
Test name
Test status
Simulation time 245015404 ps
CPU time 2.57 seconds
Started Jul 14 06:40:15 PM PDT 24
Finished Jul 14 06:40:22 PM PDT 24
Peak memory 224032 kb
Host smart-8413b99f-0900-4eca-9950-87bd7a2ce771
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424791655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.3424791655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3619768511
Short name T1193
Test name
Test status
Simulation time 175785736 ps
CPU time 1.73 seconds
Started Jul 14 06:40:11 PM PDT 24
Finished Jul 14 06:40:19 PM PDT 24
Peak memory 215612 kb
Host smart-6ec3afc1-a54a-4f9c-aa0f-15e89e22bccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619768511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3619768511 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3912250124
Short name T1200
Test name
Test status
Simulation time 373921130 ps
CPU time 3.83 seconds
Started Jul 14 06:40:06 PM PDT 24
Finished Jul 14 06:40:14 PM PDT 24
Peak memory 215596 kb
Host smart-ff6b38ad-7bab-48fe-bcb4-21d2bd87a605
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912250124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.39122
50124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.3910342378
Short name T1109
Test name
Test status
Simulation time 43546154 ps
CPU time 0.79 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207092 kb
Host smart-c42d63c8-7c0c-48ad-96cf-7c570a15dafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910342378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3910342378 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.1132676617
Short name T1146
Test name
Test status
Simulation time 27141017 ps
CPU time 0.79 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 207036 kb
Host smart-5e59fb9f-e3c7-4083-8983-f7b9b2f18459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132676617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1132676617 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.2801879795
Short name T1224
Test name
Test status
Simulation time 39876028 ps
CPU time 0.81 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207032 kb
Host smart-288ef851-7142-45a0-b7d5-624c5d897ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801879795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2801879795 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.2804578815
Short name T120
Test name
Test status
Simulation time 44903170 ps
CPU time 0.81 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 207080 kb
Host smart-4121b3b8-ee04-45a3-9af3-97e07d3011bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804578815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2804578815 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.522317067
Short name T1192
Test name
Test status
Simulation time 117576188 ps
CPU time 0.81 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 207056 kb
Host smart-5314c1f8-e1bf-43ff-bc36-c76b67a23f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522317067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.522317067 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3122592951
Short name T1171
Test name
Test status
Simulation time 14682186 ps
CPU time 0.79 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 207004 kb
Host smart-39e860d6-b6a5-4f58-bc20-4c07bbdbcf5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122592951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3122592951 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.3425365811
Short name T1131
Test name
Test status
Simulation time 41798877 ps
CPU time 0.76 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207064 kb
Host smart-97f8c35c-c694-4ee3-93bd-8008f7117f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425365811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3425365811 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.3864228833
Short name T1175
Test name
Test status
Simulation time 45505389 ps
CPU time 0.74 seconds
Started Jul 14 06:40:31 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 207064 kb
Host smart-aff2a078-ac45-42d0-a812-78a8bf007e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864228833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3864228833 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.2521297621
Short name T1138
Test name
Test status
Simulation time 23955817 ps
CPU time 0.78 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 206992 kb
Host smart-6b084e5b-cac4-4ae8-b95f-ed106133d70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521297621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2521297621 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.4156558153
Short name T1195
Test name
Test status
Simulation time 17012552 ps
CPU time 0.75 seconds
Started Jul 14 06:40:27 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 207064 kb
Host smart-f2089238-8252-419d-a6f3-33dfdd77f888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156558153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.4156558153 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3684232493
Short name T1199
Test name
Test status
Simulation time 206279668 ps
CPU time 4.82 seconds
Started Jul 14 06:40:08 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 207392 kb
Host smart-302c20b1-c689-45d1-a8ff-92d4b34de428
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684232493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3684232
493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2280825851
Short name T1161
Test name
Test status
Simulation time 3857085942 ps
CPU time 20.19 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:36 PM PDT 24
Peak memory 207492 kb
Host smart-5de49c61-eff5-4d37-b046-1de4269771e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280825851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2280825
851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3369912586
Short name T1167
Test name
Test status
Simulation time 41974929 ps
CPU time 0.98 seconds
Started Jul 14 06:40:12 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 207196 kb
Host smart-05ec1309-7ee4-4368-b54e-6dc5964e060c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369912586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3369912
586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2487838695
Short name T1165
Test name
Test status
Simulation time 159719695 ps
CPU time 1.49 seconds
Started Jul 14 06:40:17 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 215628 kb
Host smart-53a029de-7505-47a7-922e-5d55fc30ad0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487838695 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2487838695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3236886492
Short name T1087
Test name
Test status
Simulation time 36976732 ps
CPU time 0.95 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:17 PM PDT 24
Peak memory 207212 kb
Host smart-ae9a4397-08e2-4135-a891-dae0ddaa0a86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236886492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3236886492 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.1086896309
Short name T1136
Test name
Test status
Simulation time 14237275 ps
CPU time 0.78 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:24 PM PDT 24
Peak memory 207080 kb
Host smart-8124f52e-6008-48ef-b8ea-1e1a30d527c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086896309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1086896309 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.326030452
Short name T137
Test name
Test status
Simulation time 141248093 ps
CPU time 1.27 seconds
Started Jul 14 06:40:05 PM PDT 24
Finished Jul 14 06:40:09 PM PDT 24
Peak memory 215496 kb
Host smart-5d73a636-58c2-4614-9889-f2a7fb6a7a2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326030452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial
_access.326030452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.4048141167
Short name T1206
Test name
Test status
Simulation time 14048210 ps
CPU time 0.73 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 207144 kb
Host smart-245b5a95-0c59-4890-8b83-2bc1d37f8e03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048141167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.4048141167
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.84200247
Short name T1157
Test name
Test status
Simulation time 142355416 ps
CPU time 2.29 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 215768 kb
Host smart-24400b8a-dcea-4759-9d36-b59eb874305b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84200247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_o
utstanding.84200247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2659546880
Short name T1198
Test name
Test status
Simulation time 23909635 ps
CPU time 1.04 seconds
Started Jul 14 06:40:09 PM PDT 24
Finished Jul 14 06:40:15 PM PDT 24
Peak memory 207548 kb
Host smart-59a1062a-b41b-4704-9207-dc274d03ec4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659546880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.2659546880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3422954405
Short name T1135
Test name
Test status
Simulation time 28685844 ps
CPU time 1.54 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 215952 kb
Host smart-fcb6aa6c-83d5-4a58-b3ba-60c6553577b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422954405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.3422954405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2325333558
Short name T1229
Test name
Test status
Simulation time 198816784 ps
CPU time 2.35 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 215568 kb
Host smart-31c738bb-98f1-4112-a94a-7c0ee6f81c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325333558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.23253
33558 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.326340140
Short name T1133
Test name
Test status
Simulation time 62848046 ps
CPU time 0.75 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 207068 kb
Host smart-76f441d1-64d5-4602-ae64-204725e5fd40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326340140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.326340140 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2671654637
Short name T1129
Test name
Test status
Simulation time 47676493 ps
CPU time 0.77 seconds
Started Jul 14 06:40:31 PM PDT 24
Finished Jul 14 06:40:39 PM PDT 24
Peak memory 207020 kb
Host smart-09b3eed9-1334-460b-b364-5dda271e5475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671654637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2671654637 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1845265378
Short name T167
Test name
Test status
Simulation time 34685054 ps
CPU time 0.75 seconds
Started Jul 14 06:40:29 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 206976 kb
Host smart-7199dc9d-c4f8-472e-a85c-f126b74f3e05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845265378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1845265378 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.1333159914
Short name T1128
Test name
Test status
Simulation time 14257321 ps
CPU time 0.76 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 207072 kb
Host smart-e574f1ef-72be-45b9-8207-35d24ada2727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333159914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1333159914 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.2718524206
Short name T1173
Test name
Test status
Simulation time 42570808 ps
CPU time 0.74 seconds
Started Jul 14 06:40:29 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 207028 kb
Host smart-460d6d35-5163-4794-8ba2-66fb0411b8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718524206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2718524206 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.189013423
Short name T1153
Test name
Test status
Simulation time 20377144 ps
CPU time 0.75 seconds
Started Jul 14 06:40:28 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 207052 kb
Host smart-0cc01ad7-3010-47e9-b690-21480214da09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189013423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.189013423 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1311310561
Short name T1218
Test name
Test status
Simulation time 15564704 ps
CPU time 0.79 seconds
Started Jul 14 06:40:34 PM PDT 24
Finished Jul 14 06:40:40 PM PDT 24
Peak memory 207068 kb
Host smart-ea379b9c-941e-4d64-bae5-aa5193ac1b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311310561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1311310561 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.3068727590
Short name T163
Test name
Test status
Simulation time 14543570 ps
CPU time 0.8 seconds
Started Jul 14 06:40:35 PM PDT 24
Finished Jul 14 06:40:40 PM PDT 24
Peak memory 207072 kb
Host smart-eb6d113c-ac8a-4e7a-8a62-817ebac7c2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068727590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3068727590 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.1337356192
Short name T1182
Test name
Test status
Simulation time 165784877 ps
CPU time 0.73 seconds
Started Jul 14 06:40:30 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 207048 kb
Host smart-f324f4b3-16cf-4239-b25c-d092ab0fb03d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337356192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1337356192 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.2284589814
Short name T1235
Test name
Test status
Simulation time 11915929 ps
CPU time 0.71 seconds
Started Jul 14 06:40:31 PM PDT 24
Finished Jul 14 06:40:38 PM PDT 24
Peak memory 207068 kb
Host smart-987e4980-9438-4946-a078-52ae378ad46b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284589814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2284589814 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3171629740
Short name T1217
Test name
Test status
Simulation time 297210343 ps
CPU time 2.36 seconds
Started Jul 14 06:40:13 PM PDT 24
Finished Jul 14 06:40:21 PM PDT 24
Peak memory 216564 kb
Host smart-90c62a9d-789e-46fd-9bea-5e395aa2836b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171629740 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3171629740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3620320142
Short name T1090
Test name
Test status
Simulation time 154121074 ps
CPU time 1.12 seconds
Started Jul 14 06:40:06 PM PDT 24
Finished Jul 14 06:40:12 PM PDT 24
Peak memory 215592 kb
Host smart-5fb7c37d-225c-466c-8187-1f05ff6bf896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620320142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3620320142 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.1786965626
Short name T1154
Test name
Test status
Simulation time 26150205 ps
CPU time 0.77 seconds
Started Jul 14 06:40:14 PM PDT 24
Finished Jul 14 06:40:20 PM PDT 24
Peak memory 207076 kb
Host smart-47cfd183-2dbd-4e87-a61d-1217fc3db466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786965626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1786965626 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3056457746
Short name T1151
Test name
Test status
Simulation time 225796718 ps
CPU time 1.56 seconds
Started Jul 14 06:40:12 PM PDT 24
Finished Jul 14 06:40:19 PM PDT 24
Peak memory 215628 kb
Host smart-af551f4a-7e40-4d3f-adee-9a397e1a159c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056457746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.3056457746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1484951105
Short name T95
Test name
Test status
Simulation time 22923168 ps
CPU time 1 seconds
Started Jul 14 06:40:17 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 215736 kb
Host smart-e3b0852c-9f49-4116-94ba-d649a066271c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484951105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.1484951105 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1469067892
Short name T97
Test name
Test status
Simulation time 185980122 ps
CPU time 2.63 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:19 PM PDT 24
Peak memory 224136 kb
Host smart-c655c89d-9a6f-4e82-a906-fbd964fbb85a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469067892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.1469067892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2561867447
Short name T128
Test name
Test status
Simulation time 94644721 ps
CPU time 2.72 seconds
Started Jul 14 06:40:17 PM PDT 24
Finished Jul 14 06:40:24 PM PDT 24
Peak memory 215568 kb
Host smart-7d4dc227-b84e-4d34-a12a-4b4aa204d5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561867447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2561867447 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3104076978
Short name T174
Test name
Test status
Simulation time 814015591 ps
CPU time 5.42 seconds
Started Jul 14 06:40:16 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 215588 kb
Host smart-e815e6e5-ef12-48c0-b561-84a3ef589b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104076978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.31040
76978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3907146987
Short name T123
Test name
Test status
Simulation time 68085315 ps
CPU time 2.26 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 217576 kb
Host smart-58cc3ddb-e091-4cf4-bb04-c7f43516e5a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907146987 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3907146987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1475351829
Short name T1222
Test name
Test status
Simulation time 18541341 ps
CPU time 1.08 seconds
Started Jul 14 06:40:08 PM PDT 24
Finished Jul 14 06:40:15 PM PDT 24
Peak memory 207392 kb
Host smart-8da54137-2288-4197-bad6-817afacc0d6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475351829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1475351829 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.2068583151
Short name T121
Test name
Test status
Simulation time 13831412 ps
CPU time 0.75 seconds
Started Jul 14 06:40:11 PM PDT 24
Finished Jul 14 06:40:17 PM PDT 24
Peak memory 207012 kb
Host smart-7f7d41b8-0aa4-4392-bf1b-e3a10e21742f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068583151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2068583151 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3919490265
Short name T1197
Test name
Test status
Simulation time 50115296 ps
CPU time 1.59 seconds
Started Jul 14 06:40:24 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 215824 kb
Host smart-00d159a7-3356-4bc8-a44e-e4095ffd4a3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919490265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.3919490265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1255218159
Short name T1189
Test name
Test status
Simulation time 50724379 ps
CPU time 1.2 seconds
Started Jul 14 06:40:18 PM PDT 24
Finished Jul 14 06:40:24 PM PDT 24
Peak memory 215900 kb
Host smart-9607cce0-837b-4617-8051-6adf9a548161
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255218159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1255218159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.4293936646
Short name T1178
Test name
Test status
Simulation time 349490396 ps
CPU time 2.51 seconds
Started Jul 14 06:40:08 PM PDT 24
Finished Jul 14 06:40:16 PM PDT 24
Peak memory 215916 kb
Host smart-2900014e-0c9f-4727-8ee5-c2520456bcf8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293936646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.4293936646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1592621907
Short name T114
Test name
Test status
Simulation time 52668060 ps
CPU time 3.02 seconds
Started Jul 14 06:40:15 PM PDT 24
Finished Jul 14 06:40:22 PM PDT 24
Peak memory 223776 kb
Host smart-877b1d76-fd5c-42f0-a18e-d0b85f701481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592621907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1592621907 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.4224425343
Short name T1181
Test name
Test status
Simulation time 70110820 ps
CPU time 2.26 seconds
Started Jul 14 06:40:21 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 216752 kb
Host smart-11343a3c-fa24-4c7b-b4f0-4ffbf05eec38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224425343 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.4224425343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2897695337
Short name T1223
Test name
Test status
Simulation time 42444575 ps
CPU time 0.93 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:29 PM PDT 24
Peak memory 207132 kb
Host smart-b378804a-44f0-48f9-aa49-a7ce83c28b08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897695337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2897695337 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.170751551
Short name T1147
Test name
Test status
Simulation time 34753900 ps
CPU time 0.78 seconds
Started Jul 14 06:40:09 PM PDT 24
Finished Jul 14 06:40:15 PM PDT 24
Peak memory 207036 kb
Host smart-121c4c3d-dbc9-410a-81ab-b28879f527eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170751551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.170751551 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3368932511
Short name T1104
Test name
Test status
Simulation time 148298203 ps
CPU time 2.15 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 215972 kb
Host smart-3dcb3afb-7271-4dae-8182-bad3c99d3687
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368932511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3368932511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2919862842
Short name T1202
Test name
Test status
Simulation time 42656672 ps
CPU time 1.17 seconds
Started Jul 14 06:40:16 PM PDT 24
Finished Jul 14 06:40:22 PM PDT 24
Peak memory 215944 kb
Host smart-48ff47e7-eb68-4a09-bc1e-dd5968785580
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919862842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2919862842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2017004966
Short name T1205
Test name
Test status
Simulation time 351288637 ps
CPU time 2.54 seconds
Started Jul 14 06:40:10 PM PDT 24
Finished Jul 14 06:40:18 PM PDT 24
Peak memory 215920 kb
Host smart-007f7a47-76c4-41c0-bd42-d4897fc0ed77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017004966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.2017004966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1546929423
Short name T110
Test name
Test status
Simulation time 579912686 ps
CPU time 1.79 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 215552 kb
Host smart-86889574-3130-46db-8b07-822df31503c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546929423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1546929423 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2388363327
Short name T1220
Test name
Test status
Simulation time 378362779 ps
CPU time 4.47 seconds
Started Jul 14 06:40:16 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 215436 kb
Host smart-1eb87e48-4d14-4747-8c01-fcc0a45f5dee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388363327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.23883
63327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2697616714
Short name T50
Test name
Test status
Simulation time 21936934 ps
CPU time 1.48 seconds
Started Jul 14 06:40:26 PM PDT 24
Finished Jul 14 06:40:35 PM PDT 24
Peak memory 215600 kb
Host smart-9c612410-881f-4a16-bea6-b38d357e12e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697616714 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2697616714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3466889613
Short name T1142
Test name
Test status
Simulation time 46270397 ps
CPU time 1.13 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 215580 kb
Host smart-2b07c83a-0352-45aa-a945-762ef8001232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466889613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3466889613 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.4077554411
Short name T1100
Test name
Test status
Simulation time 35762528 ps
CPU time 0.76 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:29 PM PDT 24
Peak memory 207052 kb
Host smart-defc2f5f-ee14-40b9-ab94-5d1b264a7f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077554411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.4077554411 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.241055042
Short name T1108
Test name
Test status
Simulation time 68327948 ps
CPU time 2.17 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:36 PM PDT 24
Peak memory 215772 kb
Host smart-7b7cd261-d719-4374-80b4-e0703fae9f44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241055042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_
outstanding.241055042 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1981527091
Short name T98
Test name
Test status
Simulation time 45621333 ps
CPU time 2.51 seconds
Started Jul 14 06:40:22 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 223864 kb
Host smart-312ff703-75c6-4abe-b0ae-1e59d4ce570f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981527091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.1981527091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1920829958
Short name T124
Test name
Test status
Simulation time 41141776 ps
CPU time 2.5 seconds
Started Jul 14 06:40:21 PM PDT 24
Finished Jul 14 06:40:30 PM PDT 24
Peak memory 219492 kb
Host smart-b1f7b1c2-49ac-48b7-9c49-30759f837820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920829958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1920829958 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2086375485
Short name T169
Test name
Test status
Simulation time 129567170 ps
CPU time 2.55 seconds
Started Jul 14 06:40:20 PM PDT 24
Finished Jul 14 06:40:28 PM PDT 24
Peak memory 215592 kb
Host smart-a5ac5eae-cca5-4d19-b1a2-20a3498167ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086375485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.20863
75485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.169738033
Short name T129
Test name
Test status
Simulation time 241757544 ps
CPU time 1.53 seconds
Started Jul 14 06:40:18 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 215596 kb
Host smart-2d298a89-af5b-4cbf-9556-2fdd52934098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169738033 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.169738033 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.726524109
Short name T93
Test name
Test status
Simulation time 18109932 ps
CPU time 1.09 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207304 kb
Host smart-db22b5cb-1f88-402f-a2c4-2480ecae2e91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726524109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.726524109 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.2490816584
Short name T1212
Test name
Test status
Simulation time 13047450 ps
CPU time 0.76 seconds
Started Jul 14 06:40:23 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 207024 kb
Host smart-7ae471e1-63ff-4a2d-9ce6-9777a8769b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490816584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2490816584 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3683949154
Short name T1126
Test name
Test status
Simulation time 99930626 ps
CPU time 1.44 seconds
Started Jul 14 06:40:25 PM PDT 24
Finished Jul 14 06:40:34 PM PDT 24
Peak memory 215892 kb
Host smart-41d54ea4-be19-46b4-84e5-545a1bd3a531
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683949154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.3683949154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1085090765
Short name T1230
Test name
Test status
Simulation time 30243284 ps
CPU time 1.1 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:25 PM PDT 24
Peak memory 215952 kb
Host smart-aa2cdac7-87cd-405a-9acd-35fdc1118293
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085090765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.1085090765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1806418926
Short name T1121
Test name
Test status
Simulation time 362594081 ps
CPU time 1.99 seconds
Started Jul 14 06:40:17 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 215924 kb
Host smart-6fc68e4a-6544-4beb-979d-5428d63dd841
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806418926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1806418926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1586513869
Short name T1187
Test name
Test status
Simulation time 39386772 ps
CPU time 2.34 seconds
Started Jul 14 06:40:16 PM PDT 24
Finished Jul 14 06:40:23 PM PDT 24
Peak memory 215568 kb
Host smart-0abcda4e-e0ef-45da-99c0-cbbbc97cefd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586513869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1586513869 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3261553678
Short name T1196
Test name
Test status
Simulation time 207489840 ps
CPU time 3.04 seconds
Started Jul 14 06:40:19 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 215692 kb
Host smart-507561ac-5c28-46d0-a6d7-9ddef112da5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261553678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.32615
53678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.4124648411
Short name T303
Test name
Test status
Simulation time 15487942 ps
CPU time 0.81 seconds
Started Jul 14 05:34:02 PM PDT 24
Finished Jul 14 05:34:04 PM PDT 24
Peak memory 205276 kb
Host smart-f571b113-d067-426c-a8ef-759b547777dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124648411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.4124648411 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.824059235
Short name T587
Test name
Test status
Simulation time 11214585018 ps
CPU time 168.67 seconds
Started Jul 14 05:33:59 PM PDT 24
Finished Jul 14 05:36:49 PM PDT 24
Peak memory 239412 kb
Host smart-0d245d98-ec2e-4380-9fc4-9a4e8d148ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824059235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.824059235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.933870764
Short name T216
Test name
Test status
Simulation time 13607302918 ps
CPU time 169.63 seconds
Started Jul 14 05:34:00 PM PDT 24
Finished Jul 14 05:36:51 PM PDT 24
Peak memory 239296 kb
Host smart-505aaf32-703e-453e-9c06-44e7966cdf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933870764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.933870764 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.1390007496
Short name T534
Test name
Test status
Simulation time 4305531243 ps
CPU time 97.59 seconds
Started Jul 14 05:34:01 PM PDT 24
Finished Jul 14 05:35:39 PM PDT 24
Peak memory 221544 kb
Host smart-aa04fa27-fbc1-4f8c-884f-5b749248826c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390007496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1390007496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.1499519005
Short name T214
Test name
Test status
Simulation time 629591228 ps
CPU time 5.8 seconds
Started Jul 14 05:34:02 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 219816 kb
Host smart-a45f05cd-e6c6-461f-9b87-58a6cbb225e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1499519005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1499519005 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.364915313
Short name T451
Test name
Test status
Simulation time 1746745705 ps
CPU time 35.55 seconds
Started Jul 14 05:34:00 PM PDT 24
Finished Jul 14 05:34:36 PM PDT 24
Peak memory 223608 kb
Host smart-063e059c-3720-466b-be42-9eab8a852d33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=364915313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.364915313 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.2771130932
Short name T690
Test name
Test status
Simulation time 5205297358 ps
CPU time 17.64 seconds
Started Jul 14 05:34:00 PM PDT 24
Finished Jul 14 05:34:19 PM PDT 24
Peak memory 215568 kb
Host smart-133677c0-4ea7-4e85-8963-cb056bd62598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771130932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2771130932 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.138721292
Short name T262
Test name
Test status
Simulation time 6428073969 ps
CPU time 215.81 seconds
Started Jul 14 05:33:59 PM PDT 24
Finished Jul 14 05:37:36 PM PDT 24
Peak memory 242400 kb
Host smart-49c6be60-56d0-4448-98d4-9c09af9c153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138721292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.138721292 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.3719735584
Short name T762
Test name
Test status
Simulation time 27419521047 ps
CPU time 110.87 seconds
Started Jul 14 05:34:02 PM PDT 24
Finished Jul 14 05:35:54 PM PDT 24
Peak memory 239116 kb
Host smart-781800e0-7b43-48cc-99b1-ca71bac218f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719735584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3719735584 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3391556795
Short name T63
Test name
Test status
Simulation time 2438381486 ps
CPU time 4.08 seconds
Started Jul 14 05:34:03 PM PDT 24
Finished Jul 14 05:34:07 PM PDT 24
Peak memory 215588 kb
Host smart-936114e0-04fe-4ca7-9c19-7bf32bbd8ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391556795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3391556795 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.502745236
Short name T449
Test name
Test status
Simulation time 44629199 ps
CPU time 1.24 seconds
Started Jul 14 05:34:02 PM PDT 24
Finished Jul 14 05:34:04 PM PDT 24
Peak memory 215484 kb
Host smart-d77c6215-7403-4244-9c54-ab397296fbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502745236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.502745236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.4213420101
Short name T526
Test name
Test status
Simulation time 47867032317 ps
CPU time 676.66 seconds
Started Jul 14 05:34:00 PM PDT 24
Finished Jul 14 05:45:17 PM PDT 24
Peak memory 284080 kb
Host smart-ed153670-f08a-4cb9-9db2-e92012684c4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213420101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.4213420101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.1721310570
Short name T84
Test name
Test status
Simulation time 14434740653 ps
CPU time 94.07 seconds
Started Jul 14 05:34:04 PM PDT 24
Finished Jul 14 05:35:40 PM PDT 24
Peak memory 230656 kb
Host smart-98f2430a-aae9-4095-a0a1-395f927f33e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721310570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1721310570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.3742282554
Short name T70
Test name
Test status
Simulation time 3113117546 ps
CPU time 40.02 seconds
Started Jul 14 05:34:01 PM PDT 24
Finished Jul 14 05:34:41 PM PDT 24
Peak memory 253536 kb
Host smart-ba98aa13-2795-463c-9100-17a699be4d1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742282554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3742282554 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.860934877
Short name T113
Test name
Test status
Simulation time 16886321965 ps
CPU time 322.1 seconds
Started Jul 14 05:34:02 PM PDT 24
Finished Jul 14 05:39:25 PM PDT 24
Peak memory 248912 kb
Host smart-c542ea38-5aa2-49f9-bbd6-a7cf89be4ec8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860934877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.860934877 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.289832709
Short name T194
Test name
Test status
Simulation time 2870329250 ps
CPU time 61.7 seconds
Started Jul 14 05:34:04 PM PDT 24
Finished Jul 14 05:35:06 PM PDT 24
Peak memory 216572 kb
Host smart-5852fc6e-36a3-4de3-b542-24defcbf89d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289832709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.289832709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.524163874
Short name T580
Test name
Test status
Simulation time 28271491270 ps
CPU time 591.98 seconds
Started Jul 14 05:34:02 PM PDT 24
Finished Jul 14 05:43:55 PM PDT 24
Peak memory 299420 kb
Host smart-7b0eceba-8f46-4113-a3bc-d353c02016e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=524163874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.524163874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.2573659680
Short name T269
Test name
Test status
Simulation time 66715483 ps
CPU time 4.06 seconds
Started Jul 14 05:34:04 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 215556 kb
Host smart-1f885de0-ddfa-41ea-a28f-b23fd591772a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573659680 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.2573659680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2547392555
Short name T933
Test name
Test status
Simulation time 67037116 ps
CPU time 4.49 seconds
Started Jul 14 05:34:01 PM PDT 24
Finished Jul 14 05:34:06 PM PDT 24
Peak memory 215592 kb
Host smart-f97b0764-e8f7-4cce-8d91-e8a9c8753042
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547392555 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2547392555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.3800733793
Short name T389
Test name
Test status
Simulation time 67512146090 ps
CPU time 1792.65 seconds
Started Jul 14 05:34:01 PM PDT 24
Finished Jul 14 06:03:55 PM PDT 24
Peak memory 391080 kb
Host smart-71ee6e89-c120-4827-b3f5-e38cb28101a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3800733793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3800733793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.1769387973
Short name T772
Test name
Test status
Simulation time 417531705189 ps
CPU time 1905.2 seconds
Started Jul 14 05:34:05 PM PDT 24
Finished Jul 14 06:05:51 PM PDT 24
Peak memory 375420 kb
Host smart-bd30bd5a-3be7-4353-a3d7-a95e73f18557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1769387973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1769387973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.3691811787
Short name T615
Test name
Test status
Simulation time 196343817065 ps
CPU time 1311.98 seconds
Started Jul 14 05:34:04 PM PDT 24
Finished Jul 14 05:55:57 PM PDT 24
Peak memory 335216 kb
Host smart-4af2263a-938c-40a2-9516-06303aac59db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3691811787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3691811787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.1879486991
Short name T1011
Test name
Test status
Simulation time 233466502180 ps
CPU time 869.7 seconds
Started Jul 14 05:34:00 PM PDT 24
Finished Jul 14 05:48:31 PM PDT 24
Peak memory 295428 kb
Host smart-d429ac38-b31f-43ee-b8e9-2fd15c9b28db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1879486991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1879486991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.3023224802
Short name T508
Test name
Test status
Simulation time 202957857681 ps
CPU time 3955.06 seconds
Started Jul 14 05:34:03 PM PDT 24
Finished Jul 14 06:40:00 PM PDT 24
Peak memory 647676 kb
Host smart-5b2e5c93-7464-45f9-a268-77a145ddec93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3023224802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3023224802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_alert_test.2120388771
Short name T342
Test name
Test status
Simulation time 20301416 ps
CPU time 0.79 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 205192 kb
Host smart-37434806-cfb3-40d9-b147-41ef68f7fbc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120388771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2120388771 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.694513688
Short name T986
Test name
Test status
Simulation time 484497293 ps
CPU time 13.33 seconds
Started Jul 14 05:34:12 PM PDT 24
Finished Jul 14 05:34:26 PM PDT 24
Peak memory 219140 kb
Host smart-a5753774-2366-402c-bbc8-7ab5c45e9ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694513688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.694513688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.362268909
Short name T241
Test name
Test status
Simulation time 25966340948 ps
CPU time 204.3 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:37:32 PM PDT 24
Peak memory 240108 kb
Host smart-b783a984-97a8-4be5-8725-c1e99a4c153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362268909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.362268909 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.2884257103
Short name T139
Test name
Test status
Simulation time 8742124858 ps
CPU time 378.9 seconds
Started Jul 14 05:34:04 PM PDT 24
Finished Jul 14 05:40:24 PM PDT 24
Peak memory 229256 kb
Host smart-83584c99-f6af-444f-96d5-93933b85446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884257103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2884257103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3409355387
Short name T822
Test name
Test status
Simulation time 5683948598 ps
CPU time 37.51 seconds
Started Jul 14 05:34:08 PM PDT 24
Finished Jul 14 05:34:47 PM PDT 24
Peak memory 223804 kb
Host smart-6cc2619c-4520-4590-a0c1-ae9a32fe7940
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3409355387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3409355387 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1964335179
Short name T348
Test name
Test status
Simulation time 461228857 ps
CPU time 12.7 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:34:20 PM PDT 24
Peak memory 221208 kb
Host smart-9472aabc-d028-4331-afe5-8688c83e6a85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1964335179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1964335179 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.2255276440
Short name T1030
Test name
Test status
Simulation time 17770052376 ps
CPU time 75.06 seconds
Started Jul 14 05:34:09 PM PDT 24
Finished Jul 14 05:35:25 PM PDT 24
Peak memory 215684 kb
Host smart-bd466705-4a39-43a0-bab1-eaedba6bbd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255276440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2255276440 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.1844745637
Short name T959
Test name
Test status
Simulation time 3612991273 ps
CPU time 34.61 seconds
Started Jul 14 05:34:04 PM PDT 24
Finished Jul 14 05:34:40 PM PDT 24
Peak memory 223788 kb
Host smart-8f347b5d-baaa-42ae-a5d0-7db296716bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844745637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1844745637 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.1879972594
Short name T30
Test name
Test status
Simulation time 48047192386 ps
CPU time 322.47 seconds
Started Jul 14 05:34:06 PM PDT 24
Finished Jul 14 05:39:29 PM PDT 24
Peak memory 256576 kb
Host smart-8e78ded7-923a-4cdb-a044-43e4bd3bc8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879972594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1879972594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.1040330305
Short name T64
Test name
Test status
Simulation time 1674188524 ps
CPU time 8.8 seconds
Started Jul 14 05:34:06 PM PDT 24
Finished Jul 14 05:34:16 PM PDT 24
Peak memory 215580 kb
Host smart-44171f70-b610-449e-b14c-1ba5fe9b5a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040330305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1040330305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.1584586076
Short name T308
Test name
Test status
Simulation time 80903197 ps
CPU time 1.34 seconds
Started Jul 14 05:34:08 PM PDT 24
Finished Jul 14 05:34:10 PM PDT 24
Peak memory 215540 kb
Host smart-7fe14a7f-f1c1-42d8-abad-4e7f5b0dc3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584586076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1584586076 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1529240708
Short name T616
Test name
Test status
Simulation time 71122172938 ps
CPU time 1528.88 seconds
Started Jul 14 05:34:04 PM PDT 24
Finished Jul 14 05:59:34 PM PDT 24
Peak memory 352832 kb
Host smart-24d6f232-b493-4011-81a8-afceffbd3186
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529240708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1529240708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.3201735261
Short name T472
Test name
Test status
Simulation time 7832437306 ps
CPU time 182.43 seconds
Started Jul 14 05:34:05 PM PDT 24
Finished Jul 14 05:37:08 PM PDT 24
Peak memory 239616 kb
Host smart-a1150f8d-ca7b-4f94-8151-26616bbb0e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201735261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3201735261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.1133968073
Short name T12
Test name
Test status
Simulation time 10353395604 ps
CPU time 50.58 seconds
Started Jul 14 05:34:09 PM PDT 24
Finished Jul 14 05:35:00 PM PDT 24
Peak memory 259308 kb
Host smart-c2865ce4-14e7-4e67-8538-83eb1ebdb451
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133968073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1133968073 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.464204921
Short name T502
Test name
Test status
Simulation time 20025284563 ps
CPU time 369.56 seconds
Started Jul 14 05:34:03 PM PDT 24
Finished Jul 14 05:40:14 PM PDT 24
Peak memory 249512 kb
Host smart-f9dddb46-d41f-428e-94b1-a2304bf0712f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464204921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.464204921 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2734352406
Short name T184
Test name
Test status
Simulation time 679755722 ps
CPU time 32.72 seconds
Started Jul 14 05:34:00 PM PDT 24
Finished Jul 14 05:34:33 PM PDT 24
Peak memory 218052 kb
Host smart-ed8bf94a-b8a9-4ff1-801e-423eaf096054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734352406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2734352406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.640961652
Short name T627
Test name
Test status
Simulation time 172757305424 ps
CPU time 866.22 seconds
Started Jul 14 05:34:06 PM PDT 24
Finished Jul 14 05:48:33 PM PDT 24
Peak memory 316848 kb
Host smart-ff600908-2348-48d5-9f7a-6d9a2325497b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=640961652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.640961652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.1868323067
Short name T211
Test name
Test status
Simulation time 144573207 ps
CPU time 3.95 seconds
Started Jul 14 05:34:09 PM PDT 24
Finished Jul 14 05:34:14 PM PDT 24
Peak memory 215608 kb
Host smart-7dd356e3-e799-42b2-9996-af4d481663e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868323067 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.1868323067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2575180899
Short name T1046
Test name
Test status
Simulation time 730590210 ps
CPU time 4.63 seconds
Started Jul 14 05:34:03 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 215592 kb
Host smart-3822e9e6-5a48-45db-9aa0-f624ae8ee1aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575180899 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2575180899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.4275587304
Short name T366
Test name
Test status
Simulation time 68051365828 ps
CPU time 1761.33 seconds
Started Jul 14 05:34:05 PM PDT 24
Finished Jul 14 06:03:28 PM PDT 24
Peak memory 394768 kb
Host smart-9d4b0445-f803-4db4-b56c-b8a093c61c7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4275587304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.4275587304 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.3636883625
Short name T430
Test name
Test status
Simulation time 63557936936 ps
CPU time 1709.66 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 06:02:38 PM PDT 24
Peak memory 373536 kb
Host smart-a71c6c04-56a8-4d00-8e52-95311b9cd044
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3636883625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3636883625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.2817958635
Short name T789
Test name
Test status
Simulation time 14078333819 ps
CPU time 1109.07 seconds
Started Jul 14 05:34:08 PM PDT 24
Finished Jul 14 05:52:38 PM PDT 24
Peak memory 338048 kb
Host smart-83926d3e-4b71-4adb-ba36-472aa7e54a97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2817958635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2817958635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.1628309770
Short name T323
Test name
Test status
Simulation time 96898449291 ps
CPU time 995.15 seconds
Started Jul 14 05:34:11 PM PDT 24
Finished Jul 14 05:50:47 PM PDT 24
Peak memory 293244 kb
Host smart-49493951-b715-401d-a285-dbe839a466f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1628309770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1628309770 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.3348983762
Short name T352
Test name
Test status
Simulation time 518219467624 ps
CPU time 5265.7 seconds
Started Jul 14 05:34:03 PM PDT 24
Finished Jul 14 07:01:51 PM PDT 24
Peak memory 639192 kb
Host smart-1886d587-56fb-46b4-9d29-f04ed027f499
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3348983762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3348983762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.29362260
Short name T795
Test name
Test status
Simulation time 44540974792 ps
CPU time 3477.51 seconds
Started Jul 14 05:34:04 PM PDT 24
Finished Jul 14 06:32:03 PM PDT 24
Peak memory 559056 kb
Host smart-80fac415-c3e1-4eea-9894-cf3c15020c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=29362260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.29362260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2687647137
Short name T741
Test name
Test status
Simulation time 14271582 ps
CPU time 0.77 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 05:34:39 PM PDT 24
Peak memory 205260 kb
Host smart-4306da1d-0f82-40c7-ac79-ce6aebce6528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687647137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2687647137 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.1601505105
Short name T801
Test name
Test status
Simulation time 1205108781 ps
CPU time 7.06 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:34:45 PM PDT 24
Peak memory 223784 kb
Host smart-56caeea7-ec1c-4206-8cef-b263be3aaf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601505105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1601505105 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.1269761740
Short name T558
Test name
Test status
Simulation time 1372510699 ps
CPU time 23.12 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:59 PM PDT 24
Peak memory 221676 kb
Host smart-c89cae77-4a4f-4539-8f35-0b3005bc2c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269761740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1269761740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.237147727
Short name T647
Test name
Test status
Simulation time 5288629331 ps
CPU time 27.98 seconds
Started Jul 14 05:34:39 PM PDT 24
Finished Jul 14 05:35:07 PM PDT 24
Peak memory 223756 kb
Host smart-f40ffe10-e506-44d9-a44d-efc703bf2507
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=237147727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.237147727 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.409879262
Short name T920
Test name
Test status
Simulation time 381958547 ps
CPU time 13.36 seconds
Started Jul 14 05:34:41 PM PDT 24
Finished Jul 14 05:34:55 PM PDT 24
Peak memory 215572 kb
Host smart-fa741304-c463-40aa-8947-8dabd76a358a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409879262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.409879262 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.2694324388
Short name T1034
Test name
Test status
Simulation time 16509151504 ps
CPU time 256.13 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:38:54 PM PDT 24
Peak memory 242144 kb
Host smart-eb5002ae-69e9-4ab4-b303-199f918c0f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694324388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2694324388 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.253467092
Short name T569
Test name
Test status
Simulation time 68822869158 ps
CPU time 459.17 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 05:42:20 PM PDT 24
Peak memory 265872 kb
Host smart-3735fb83-2259-4295-8bef-571c1e0fdbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253467092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.253467092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.3290864724
Short name T68
Test name
Test status
Simulation time 5539488669 ps
CPU time 6.62 seconds
Started Jul 14 05:34:41 PM PDT 24
Finished Jul 14 05:34:48 PM PDT 24
Peak memory 207368 kb
Host smart-1f23a119-4fee-4aa8-bf63-f89855ce652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290864724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3290864724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.500105050
Short name T242
Test name
Test status
Simulation time 41190195 ps
CPU time 1.2 seconds
Started Jul 14 05:34:41 PM PDT 24
Finished Jul 14 05:34:43 PM PDT 24
Peak memory 215500 kb
Host smart-2637b65e-915e-4b6b-8a91-14b5d05a8528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500105050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.500105050 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.1714189611
Short name T942
Test name
Test status
Simulation time 108772475616 ps
CPU time 842.85 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 05:48:36 PM PDT 24
Peak memory 294488 kb
Host smart-5888103f-d9a8-4e57-b327-c576f834a8b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714189611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.1714189611 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.1551946724
Short name T752
Test name
Test status
Simulation time 2955552774 ps
CPU time 111.09 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:36:29 PM PDT 24
Peak memory 229280 kb
Host smart-4ac9f4d8-fc01-44de-8952-6844fa929d0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551946724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1551946724 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.876542759
Short name T357
Test name
Test status
Simulation time 9830295668 ps
CPU time 30.05 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:35:06 PM PDT 24
Peak memory 223796 kb
Host smart-2822c1a5-686e-4dcf-9a7d-acd45badbe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876542759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.876542759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.1933940247
Short name T53
Test name
Test status
Simulation time 242619216733 ps
CPU time 1340.56 seconds
Started Jul 14 05:34:38 PM PDT 24
Finished Jul 14 05:57:00 PM PDT 24
Peak memory 393152 kb
Host smart-c1fc565e-6e5f-437e-be9a-e6c4c40224f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1933940247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1933940247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.64060107
Short name T397
Test name
Test status
Simulation time 1067212329 ps
CPU time 5.24 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:34:43 PM PDT 24
Peak memory 215644 kb
Host smart-a00ea47c-5f98-4e18-b27b-0ff5d07c46fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64060107 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.kmac_test_vectors_kmac.64060107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.1614560603
Short name T333
Test name
Test status
Simulation time 973662130 ps
CPU time 5.01 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:42 PM PDT 24
Peak memory 215616 kb
Host smart-267891ff-12c2-4228-9d59-869c97c612c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614560603 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.1614560603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.3447609521
Short name T1019
Test name
Test status
Simulation time 19390979220 ps
CPU time 1695.01 seconds
Started Jul 14 05:34:34 PM PDT 24
Finished Jul 14 06:02:50 PM PDT 24
Peak memory 399444 kb
Host smart-33c78c3b-4a04-4bb0-92ae-c52de73686ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3447609521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3447609521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.52376103
Short name T948
Test name
Test status
Simulation time 128111224011 ps
CPU time 1778.86 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 06:04:17 PM PDT 24
Peak memory 376480 kb
Host smart-3f63c8f1-b8c0-4c98-9f87-461096aa6987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=52376103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.52376103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.3937652065
Short name T549
Test name
Test status
Simulation time 27110971042 ps
CPU time 1134.14 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 05:53:33 PM PDT 24
Peak memory 333344 kb
Host smart-4b50ac13-508d-45d2-97c9-811b3110da58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3937652065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.3937652065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.246306333
Short name T402
Test name
Test status
Simulation time 9654680295 ps
CPU time 824.52 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:48:22 PM PDT 24
Peak memory 292368 kb
Host smart-d7369d13-e404-4cda-b4d5-272236331aa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=246306333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.246306333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.936509469
Short name T563
Test name
Test status
Simulation time 636696979441 ps
CPU time 3933.22 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 06:40:12 PM PDT 24
Peak memory 651552 kb
Host smart-ab4b1df5-7f6f-476b-9a6c-e478c861b6f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=936509469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.936509469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.4055670595
Short name T445
Test name
Test status
Simulation time 228778092237 ps
CPU time 3445.98 seconds
Started Jul 14 05:34:32 PM PDT 24
Finished Jul 14 06:32:00 PM PDT 24
Peak memory 565176 kb
Host smart-05241404-2fe4-41dc-834c-b36cd1be42dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4055670595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.4055670595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.3761141138
Short name T917
Test name
Test status
Simulation time 60067485 ps
CPU time 0.79 seconds
Started Jul 14 05:34:44 PM PDT 24
Finished Jul 14 05:34:45 PM PDT 24
Peak memory 205256 kb
Host smart-9117c669-bcab-4ab7-9a56-4ffdfb616bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761141138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3761141138 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.2893112730
Short name T643
Test name
Test status
Simulation time 6573255481 ps
CPU time 79.7 seconds
Started Jul 14 05:34:43 PM PDT 24
Finished Jul 14 05:36:03 PM PDT 24
Peak memory 227964 kb
Host smart-8d981230-8ca7-4306-bf9e-c45a11f830e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893112730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2893112730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.3067521105
Short name T1062
Test name
Test status
Simulation time 6728272940 ps
CPU time 203.07 seconds
Started Jul 14 05:34:49 PM PDT 24
Finished Jul 14 05:38:12 PM PDT 24
Peak memory 224488 kb
Host smart-6e61a198-ac28-4ceb-bd10-726c8ec92d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067521105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3067521105 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.1955207097
Short name T370
Test name
Test status
Simulation time 929736458 ps
CPU time 9.38 seconds
Started Jul 14 05:34:49 PM PDT 24
Finished Jul 14 05:34:59 PM PDT 24
Peak memory 223304 kb
Host smart-b3d4270b-401b-4b93-94d4-851c17b17784
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1955207097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1955207097 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2923910386
Short name T842
Test name
Test status
Simulation time 1087085668 ps
CPU time 28.79 seconds
Started Jul 14 05:34:47 PM PDT 24
Finished Jul 14 05:35:17 PM PDT 24
Peak memory 219508 kb
Host smart-d221362e-0d2e-4ed7-897f-5e906e5e8b2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2923910386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2923910386 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.3857706104
Short name T39
Test name
Test status
Simulation time 23465667139 ps
CPU time 237.6 seconds
Started Jul 14 05:34:50 PM PDT 24
Finished Jul 14 05:38:48 PM PDT 24
Peak memory 244600 kb
Host smart-0e6d6eaf-d5dc-4822-adc7-21acebadc7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857706104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3857706104 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.3554462745
Short name T830
Test name
Test status
Simulation time 7924046625 ps
CPU time 224.15 seconds
Started Jul 14 05:34:44 PM PDT 24
Finished Jul 14 05:38:28 PM PDT 24
Peak memory 249116 kb
Host smart-a0a27d88-e89e-4fcd-9b92-eac1eea80bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554462745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3554462745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.3232705652
Short name T712
Test name
Test status
Simulation time 4890420194 ps
CPU time 7.99 seconds
Started Jul 14 05:34:48 PM PDT 24
Finished Jul 14 05:34:56 PM PDT 24
Peak memory 215572 kb
Host smart-12954785-aa18-4dd6-9494-7cf66b3d5f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232705652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3232705652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1442474248
Short name T980
Test name
Test status
Simulation time 183636831305 ps
CPU time 998.71 seconds
Started Jul 14 05:34:41 PM PDT 24
Finished Jul 14 05:51:20 PM PDT 24
Peak memory 309448 kb
Host smart-ba860619-5150-4bf7-b5df-258381ca3762
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442474248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1442474248 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1783334849
Short name T740
Test name
Test status
Simulation time 5971350365 ps
CPU time 124.63 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 05:36:45 PM PDT 24
Peak memory 228968 kb
Host smart-203d03c0-e871-463b-b4b1-bb177a9523ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783334849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1783334849 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.3031588505
Short name T596
Test name
Test status
Simulation time 17347468747 ps
CPU time 47.01 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 05:35:27 PM PDT 24
Peak memory 218920 kb
Host smart-96dad8ad-df0e-4424-b618-cc1d0cd0084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031588505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3031588505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.245699032
Short name T55
Test name
Test status
Simulation time 75930853658 ps
CPU time 1593.37 seconds
Started Jul 14 05:34:44 PM PDT 24
Finished Jul 14 06:01:18 PM PDT 24
Peak memory 372392 kb
Host smart-afc87454-d3ed-4835-96a7-58957e9ab7d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=245699032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.245699032 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.2928408470
Short name T754
Test name
Test status
Simulation time 255391383 ps
CPU time 4.74 seconds
Started Jul 14 05:34:46 PM PDT 24
Finished Jul 14 05:34:51 PM PDT 24
Peak memory 215572 kb
Host smart-a8e6f002-8daa-4ea0-b1fa-8af7fd5994cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928408470 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.2928408470 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.1381502902
Short name T209
Test name
Test status
Simulation time 114532619 ps
CPU time 4.04 seconds
Started Jul 14 05:34:46 PM PDT 24
Finished Jul 14 05:34:50 PM PDT 24
Peak memory 215496 kb
Host smart-5ea9e7f5-70af-40f0-993c-3880b720ef46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381502902 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.1381502902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.3152398806
Short name T367
Test name
Test status
Simulation time 412170127846 ps
CPU time 2130.72 seconds
Started Jul 14 05:34:47 PM PDT 24
Finished Jul 14 06:10:19 PM PDT 24
Peak memory 398944 kb
Host smart-980e1305-ee0b-436a-9709-89d0643744e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3152398806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.3152398806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.3107330795
Short name T299
Test name
Test status
Simulation time 18400013405 ps
CPU time 1585.71 seconds
Started Jul 14 05:34:43 PM PDT 24
Finished Jul 14 06:01:09 PM PDT 24
Peak memory 387080 kb
Host smart-72828592-2700-42cd-9617-87a7acfade28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3107330795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3107330795 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.1524742001
Short name T602
Test name
Test status
Simulation time 28284708590 ps
CPU time 1116.13 seconds
Started Jul 14 05:34:49 PM PDT 24
Finished Jul 14 05:53:25 PM PDT 24
Peak memory 333928 kb
Host smart-ab21e51f-742b-439d-938d-56453e34d8f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1524742001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.1524742001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.2009079198
Short name T284
Test name
Test status
Simulation time 19250543089 ps
CPU time 828.22 seconds
Started Jul 14 05:34:46 PM PDT 24
Finished Jul 14 05:48:35 PM PDT 24
Peak memory 297792 kb
Host smart-615a52de-b9d2-4257-be89-adfedbcea91b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2009079198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.2009079198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.743038376
Short name T1072
Test name
Test status
Simulation time 254182283664 ps
CPU time 4903.52 seconds
Started Jul 14 05:34:49 PM PDT 24
Finished Jul 14 06:56:33 PM PDT 24
Peak memory 639876 kb
Host smart-1920cb3b-ab59-4134-a8a8-b5bed561ae09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=743038376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.743038376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.1609844236
Short name T212
Test name
Test status
Simulation time 223434355561 ps
CPU time 4108.66 seconds
Started Jul 14 05:34:45 PM PDT 24
Finished Jul 14 06:43:15 PM PDT 24
Peak memory 569992 kb
Host smart-56e32661-be5f-4e8d-b73b-7b13d56069cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1609844236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1609844236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.2800611308
Short name T606
Test name
Test status
Simulation time 33000189 ps
CPU time 0.84 seconds
Started Jul 14 05:35:04 PM PDT 24
Finished Jul 14 05:35:05 PM PDT 24
Peak memory 205304 kb
Host smart-50182108-0e02-41a5-a27c-34f5789054f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800611308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2800611308 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.2282973853
Short name T365
Test name
Test status
Simulation time 1127935789 ps
CPU time 60.52 seconds
Started Jul 14 05:34:59 PM PDT 24
Finished Jul 14 05:36:00 PM PDT 24
Peak memory 224628 kb
Host smart-c780e414-5ff3-4129-b139-eaf1e2dd499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282973853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2282973853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.3045865698
Short name T379
Test name
Test status
Simulation time 17148647682 ps
CPU time 522.95 seconds
Started Jul 14 05:34:51 PM PDT 24
Finished Jul 14 05:43:34 PM PDT 24
Peak memory 229988 kb
Host smart-4537bd0d-4309-487f-af43-b1086f66b848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045865698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3045865698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.4035755495
Short name T522
Test name
Test status
Simulation time 5261288225 ps
CPU time 27.31 seconds
Started Jul 14 05:34:59 PM PDT 24
Finished Jul 14 05:35:27 PM PDT 24
Peak memory 223988 kb
Host smart-9ed3f435-ee2f-4c89-b48c-9d2979677203
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4035755495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.4035755495 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.3357303837
Short name T823
Test name
Test status
Simulation time 1431608742 ps
CPU time 19.1 seconds
Started Jul 14 05:35:01 PM PDT 24
Finished Jul 14 05:35:21 PM PDT 24
Peak memory 218628 kb
Host smart-69670afa-dfd2-4959-8b47-240222ace098
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3357303837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3357303837 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.3060339988
Short name T2
Test name
Test status
Simulation time 25876555994 ps
CPU time 140.33 seconds
Started Jul 14 05:35:00 PM PDT 24
Finished Jul 14 05:37:21 PM PDT 24
Peak memory 232880 kb
Host smart-4eb7695d-18bb-44de-9535-51d94c47342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060339988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3060339988 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.2340442673
Short name T790
Test name
Test status
Simulation time 12580957248 ps
CPU time 206.21 seconds
Started Jul 14 05:34:59 PM PDT 24
Finished Jul 14 05:38:26 PM PDT 24
Peak memory 248428 kb
Host smart-996a856d-3557-45ff-abab-830f3fc3e128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340442673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2340442673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.704149104
Short name T20
Test name
Test status
Simulation time 2111981519 ps
CPU time 10.55 seconds
Started Jul 14 05:34:55 PM PDT 24
Finished Jul 14 05:35:06 PM PDT 24
Peak memory 207332 kb
Host smart-1bd7d57d-448f-4c6f-905b-555076a0d74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704149104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.704149104 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.898369871
Short name T235
Test name
Test status
Simulation time 36458494 ps
CPU time 1.38 seconds
Started Jul 14 05:35:03 PM PDT 24
Finished Jul 14 05:35:05 PM PDT 24
Peak memory 216568 kb
Host smart-e33750bc-1cf0-4340-95a6-ce331a48e74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898369871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.898369871 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.2454031507
Short name T88
Test name
Test status
Simulation time 391615433985 ps
CPU time 2257.95 seconds
Started Jul 14 05:34:53 PM PDT 24
Finished Jul 14 06:12:31 PM PDT 24
Peak memory 409572 kb
Host smart-97c07af9-905b-4690-a03b-b69ad2e5494f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454031507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.2454031507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1835959282
Short name T347
Test name
Test status
Simulation time 52755910188 ps
CPU time 338.4 seconds
Started Jul 14 05:34:50 PM PDT 24
Finished Jul 14 05:40:29 PM PDT 24
Peak memory 246332 kb
Host smart-045d6a6c-42af-4050-9bc1-5cfe786b19ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835959282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1835959282 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.3932470636
Short name T254
Test name
Test status
Simulation time 4105401915 ps
CPU time 48.46 seconds
Started Jul 14 05:34:50 PM PDT 24
Finished Jul 14 05:35:39 PM PDT 24
Peak memory 220340 kb
Host smart-0b4d1236-016c-4978-b90f-e3add62358cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932470636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3932470636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.243747732
Short name T443
Test name
Test status
Simulation time 120236425059 ps
CPU time 1317.32 seconds
Started Jul 14 05:35:03 PM PDT 24
Finished Jul 14 05:57:01 PM PDT 24
Peak memory 331640 kb
Host smart-a8422272-82c7-4106-aa04-c15ff9d2267b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=243747732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.243747732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.3974088666
Short name T509
Test name
Test status
Simulation time 581861778 ps
CPU time 5.06 seconds
Started Jul 14 05:34:52 PM PDT 24
Finished Jul 14 05:34:57 PM PDT 24
Peak memory 215592 kb
Host smart-3d210c8a-0dc2-4f88-8b89-9e68fdf9e0e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974088666 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.3974088666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.2684800054
Short name T415
Test name
Test status
Simulation time 599060238 ps
CPU time 3.85 seconds
Started Jul 14 05:34:52 PM PDT 24
Finished Jul 14 05:34:57 PM PDT 24
Peak memory 215628 kb
Host smart-0ad72f63-6062-4d9e-9895-9636e96eaeb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684800054 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.2684800054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.1525602498
Short name T222
Test name
Test status
Simulation time 121223338636 ps
CPU time 1817.49 seconds
Started Jul 14 05:34:49 PM PDT 24
Finished Jul 14 06:05:07 PM PDT 24
Peak memory 386864 kb
Host smart-de3aa2e9-43d6-419f-86aa-7a5c2fc4182c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1525602498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1525602498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.1830932458
Short name T519
Test name
Test status
Simulation time 101354201293 ps
CPU time 1895.54 seconds
Started Jul 14 05:34:49 PM PDT 24
Finished Jul 14 06:06:26 PM PDT 24
Peak memory 376204 kb
Host smart-a9db5149-6efa-4eab-bead-a42af1249849
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1830932458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.1830932458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.105358721
Short name T496
Test name
Test status
Simulation time 53111948429 ps
CPU time 1111.81 seconds
Started Jul 14 05:34:53 PM PDT 24
Finished Jul 14 05:53:25 PM PDT 24
Peak memory 327844 kb
Host smart-4431406a-e7f7-4bcf-9368-db756c5d1a99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=105358721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.105358721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.3698812049
Short name T1067
Test name
Test status
Simulation time 131773536502 ps
CPU time 955.89 seconds
Started Jul 14 05:34:51 PM PDT 24
Finished Jul 14 05:50:48 PM PDT 24
Peak memory 296676 kb
Host smart-c53c0678-c0db-4513-9666-40d92745f75a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3698812049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.3698812049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.2008258818
Short name T750
Test name
Test status
Simulation time 173415976741 ps
CPU time 4586.73 seconds
Started Jul 14 05:34:54 PM PDT 24
Finished Jul 14 06:51:21 PM PDT 24
Peak memory 637784 kb
Host smart-bc151770-37cc-40c3-8fe2-adca529726c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2008258818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.2008258818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_alert_test.3681646101
Short name T444
Test name
Test status
Simulation time 41982464 ps
CPU time 0.78 seconds
Started Jul 14 05:35:08 PM PDT 24
Finished Jul 14 05:35:09 PM PDT 24
Peak memory 205180 kb
Host smart-4a7644ed-02d8-42f2-9dfa-e0880cdaca44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681646101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3681646101 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.2813235223
Short name T662
Test name
Test status
Simulation time 14346016149 ps
CPU time 144.07 seconds
Started Jul 14 05:35:08 PM PDT 24
Finished Jul 14 05:37:32 PM PDT 24
Peak memory 236204 kb
Host smart-800fa691-edf8-4bab-8df1-826528811a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813235223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2813235223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2163517620
Short name T793
Test name
Test status
Simulation time 3388582513 ps
CPU time 34.72 seconds
Started Jul 14 05:35:09 PM PDT 24
Finished Jul 14 05:35:44 PM PDT 24
Peak memory 220816 kb
Host smart-409adab0-375c-46ee-8e45-07274f951521
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2163517620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2163517620 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.3889399863
Short name T865
Test name
Test status
Simulation time 235357455 ps
CPU time 17.18 seconds
Started Jul 14 05:35:09 PM PDT 24
Finished Jul 14 05:35:26 PM PDT 24
Peak memory 218880 kb
Host smart-3b6012f7-5745-4094-b740-b0107a3e0939
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3889399863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3889399863 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.803468578
Short name T641
Test name
Test status
Simulation time 32216096473 ps
CPU time 110.9 seconds
Started Jul 14 05:35:09 PM PDT 24
Finished Jul 14 05:37:01 PM PDT 24
Peak memory 228824 kb
Host smart-010fab8e-2a31-4e32-aa61-2c6665a35824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803468578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.803468578 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2330244938
Short name T590
Test name
Test status
Simulation time 30690763070 ps
CPU time 208.95 seconds
Started Jul 14 05:35:09 PM PDT 24
Finished Jul 14 05:38:39 PM PDT 24
Peak memory 252928 kb
Host smart-5779c1ec-367d-43d1-b8d9-09f1793f9988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330244938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2330244938 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.1473491760
Short name T679
Test name
Test status
Simulation time 7225590892 ps
CPU time 10.5 seconds
Started Jul 14 05:35:10 PM PDT 24
Finished Jul 14 05:35:21 PM PDT 24
Peak memory 207500 kb
Host smart-f3016c22-0664-4c61-a56b-7b7c8834fd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473491760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1473491760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.2708330784
Short name T857
Test name
Test status
Simulation time 48286879 ps
CPU time 1.29 seconds
Started Jul 14 05:35:06 PM PDT 24
Finished Jul 14 05:35:08 PM PDT 24
Peak memory 215480 kb
Host smart-76996ed5-b480-488e-a796-9e0aff238b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708330784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2708330784 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.2128076832
Short name T689
Test name
Test status
Simulation time 24482574278 ps
CPU time 2176.39 seconds
Started Jul 14 05:35:02 PM PDT 24
Finished Jul 14 06:11:19 PM PDT 24
Peak memory 447288 kb
Host smart-658d793a-85ce-4b99-b689-f5feb49191f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128076832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.2128076832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.638932842
Short name T180
Test name
Test status
Simulation time 16857731111 ps
CPU time 338.04 seconds
Started Jul 14 05:35:01 PM PDT 24
Finished Jul 14 05:40:39 PM PDT 24
Peak memory 243684 kb
Host smart-823ccf9a-bdf9-420e-add9-ca3665b175d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638932842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.638932842 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.4031987902
Short name T538
Test name
Test status
Simulation time 12543192027 ps
CPU time 63.92 seconds
Started Jul 14 05:35:02 PM PDT 24
Finished Jul 14 05:36:06 PM PDT 24
Peak memory 219156 kb
Host smart-d03c56cc-9f24-4ac7-94f8-0dbfcc0d68c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031987902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.4031987902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.2718947598
Short name T882
Test name
Test status
Simulation time 511998408401 ps
CPU time 1327.84 seconds
Started Jul 14 05:35:08 PM PDT 24
Finished Jul 14 05:57:17 PM PDT 24
Peak memory 366756 kb
Host smart-6c22d1aa-4434-4f7f-bbb3-6e166ab5b59e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2718947598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2718947598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.2571547833
Short name T200
Test name
Test status
Simulation time 731765387 ps
CPU time 4.44 seconds
Started Jul 14 05:35:05 PM PDT 24
Finished Jul 14 05:35:10 PM PDT 24
Peak memory 215504 kb
Host smart-25a6f297-5a50-47e8-ad39-6771fbe5f02c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571547833 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.2571547833 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.3343568828
Short name T1049
Test name
Test status
Simulation time 68346426 ps
CPU time 3.93 seconds
Started Jul 14 05:35:06 PM PDT 24
Finished Jul 14 05:35:11 PM PDT 24
Peak memory 208676 kb
Host smart-c89d1236-00ad-433c-bdf9-0b92fdb5255e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343568828 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.3343568828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.1988776027
Short name T302
Test name
Test status
Simulation time 67969975384 ps
CPU time 1929.16 seconds
Started Jul 14 05:35:06 PM PDT 24
Finished Jul 14 06:07:15 PM PDT 24
Peak memory 394076 kb
Host smart-8468ddaf-e0a3-4ba1-b5ef-01363bf1622d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1988776027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1988776027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.2817600051
Short name T289
Test name
Test status
Simulation time 70421921069 ps
CPU time 1483.32 seconds
Started Jul 14 05:35:03 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 370856 kb
Host smart-d2034ba3-db94-442b-ad8c-ee28c5ef4581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2817600051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2817600051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.2784048869
Short name T664
Test name
Test status
Simulation time 47944439224 ps
CPU time 1294.92 seconds
Started Jul 14 05:35:04 PM PDT 24
Finished Jul 14 05:56:40 PM PDT 24
Peak memory 329472 kb
Host smart-708ac35a-b88d-4bd3-91e7-d3c9ae132952
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2784048869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2784048869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.2089135183
Short name T541
Test name
Test status
Simulation time 97034193452 ps
CPU time 1026.11 seconds
Started Jul 14 05:35:03 PM PDT 24
Finished Jul 14 05:52:10 PM PDT 24
Peak memory 293580 kb
Host smart-1297e33b-3398-42af-b655-5c1e6c0ef525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2089135183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.2089135183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.3435433603
Short name T698
Test name
Test status
Simulation time 707422087800 ps
CPU time 4673.88 seconds
Started Jul 14 05:35:01 PM PDT 24
Finished Jul 14 06:52:56 PM PDT 24
Peak memory 636972 kb
Host smart-92a47d47-46c3-4791-a012-3c4797b4d1de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3435433603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.3435433603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.1027822279
Short name T663
Test name
Test status
Simulation time 916216074294 ps
CPU time 4710.66 seconds
Started Jul 14 05:35:01 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 574468 kb
Host smart-ec9d6682-8c9d-4bbe-8138-e7b270dbc59b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1027822279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.1027822279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.2165698754
Short name T1048
Test name
Test status
Simulation time 49949820 ps
CPU time 0.76 seconds
Started Jul 14 05:35:17 PM PDT 24
Finished Jul 14 05:35:18 PM PDT 24
Peak memory 205288 kb
Host smart-2caf1497-46df-4528-9ee9-748b347fe852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165698754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2165698754 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.869727835
Short name T253
Test name
Test status
Simulation time 2749892786 ps
CPU time 115.81 seconds
Started Jul 14 05:35:14 PM PDT 24
Finished Jul 14 05:37:10 PM PDT 24
Peak memory 232260 kb
Host smart-422a136d-1f14-486f-93b3-7f91cc8609c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869727835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.869727835 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.4250073137
Short name T976
Test name
Test status
Simulation time 8424426847 ps
CPU time 757.06 seconds
Started Jul 14 05:35:17 PM PDT 24
Finished Jul 14 05:47:55 PM PDT 24
Peak memory 232076 kb
Host smart-00f1f778-662b-4c64-9ac2-df4b0ee092ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250073137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.4250073137 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.1231091159
Short name T877
Test name
Test status
Simulation time 310932428 ps
CPU time 9.74 seconds
Started Jul 14 05:35:14 PM PDT 24
Finished Jul 14 05:35:25 PM PDT 24
Peak memory 217688 kb
Host smart-90ae78fb-6dd4-4f9b-8b78-afa6496ed198
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231091159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1231091159 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2771154832
Short name T16
Test name
Test status
Simulation time 4120291437 ps
CPU time 40.23 seconds
Started Jul 14 05:35:16 PM PDT 24
Finished Jul 14 05:35:57 PM PDT 24
Peak memory 223636 kb
Host smart-e26dd945-3934-4e4e-906c-977027cb6bcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2771154832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2771154832 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.1378062654
Short name T340
Test name
Test status
Simulation time 726900006 ps
CPU time 26.47 seconds
Started Jul 14 05:35:15 PM PDT 24
Finished Jul 14 05:35:42 PM PDT 24
Peak memory 223752 kb
Host smart-deaa5d85-d333-45c6-bcbe-ff92d4adae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378062654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1378062654 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.3283794549
Short name T671
Test name
Test status
Simulation time 1659464942 ps
CPU time 42.83 seconds
Started Jul 14 05:35:13 PM PDT 24
Finished Jul 14 05:35:56 PM PDT 24
Peak memory 238232 kb
Host smart-c93eb5dd-32c8-4371-9592-0b326db9e5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283794549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3283794549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.2551387782
Short name T911
Test name
Test status
Simulation time 237832022 ps
CPU time 1.75 seconds
Started Jul 14 05:35:15 PM PDT 24
Finished Jul 14 05:35:17 PM PDT 24
Peak memory 215460 kb
Host smart-5a55913c-50cc-4acc-981e-58679d2561df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551387782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2551387782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.789841881
Short name T551
Test name
Test status
Simulation time 17852617685 ps
CPU time 1493.1 seconds
Started Jul 14 05:35:08 PM PDT 24
Finished Jul 14 06:00:02 PM PDT 24
Peak memory 392684 kb
Host smart-d8de67de-2b05-4d70-a399-9bc1eb264774
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789841881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_an
d_output.789841881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.3695148855
Short name T458
Test name
Test status
Simulation time 39186964881 ps
CPU time 295.67 seconds
Started Jul 14 05:35:14 PM PDT 24
Finished Jul 14 05:40:11 PM PDT 24
Peak memory 241912 kb
Host smart-45886013-3768-45a7-87d5-b1ceef609df1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695148855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3695148855 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.3347488880
Short name T960
Test name
Test status
Simulation time 714768388 ps
CPU time 17.08 seconds
Started Jul 14 05:35:07 PM PDT 24
Finished Jul 14 05:35:25 PM PDT 24
Peak memory 219228 kb
Host smart-d98dc831-1520-45f3-a051-cbdf66c9566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347488880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3347488880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.3074608047
Short name T745
Test name
Test status
Simulation time 123030248337 ps
CPU time 503.19 seconds
Started Jul 14 05:35:19 PM PDT 24
Finished Jul 14 05:43:42 PM PDT 24
Peak memory 297740 kb
Host smart-874ca785-c112-4746-b5d2-50e375cb434c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3074608047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3074608047 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.1692375936
Short name T646
Test name
Test status
Simulation time 176660645 ps
CPU time 4.89 seconds
Started Jul 14 05:35:18 PM PDT 24
Finished Jul 14 05:35:24 PM PDT 24
Peak memory 215516 kb
Host smart-79b16801-f7ce-4039-89c4-c33d4f0ab8be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692375936 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.1692375936 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.3221081915
Short name T225
Test name
Test status
Simulation time 68700945 ps
CPU time 3.69 seconds
Started Jul 14 05:35:17 PM PDT 24
Finished Jul 14 05:35:22 PM PDT 24
Peak memory 215684 kb
Host smart-7f9ef982-d22f-4b6d-aad6-7ca5ea91a4a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221081915 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.3221081915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.4167017151
Short name T814
Test name
Test status
Simulation time 19366573408 ps
CPU time 1611.33 seconds
Started Jul 14 05:35:20 PM PDT 24
Finished Jul 14 06:02:13 PM PDT 24
Peak memory 390456 kb
Host smart-53fa23a9-1e83-4c73-82e6-31a63f80e9c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4167017151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.4167017151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.32786178
Short name T593
Test name
Test status
Simulation time 328337847889 ps
CPU time 1896.21 seconds
Started Jul 14 05:35:14 PM PDT 24
Finished Jul 14 06:06:51 PM PDT 24
Peak memory 388568 kb
Host smart-9f03a270-f132-403c-ad53-a9e9e377e06d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=32786178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.32786178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.1300184436
Short name T880
Test name
Test status
Simulation time 139916125939 ps
CPU time 1387.41 seconds
Started Jul 14 05:35:16 PM PDT 24
Finished Jul 14 05:58:24 PM PDT 24
Peak memory 328616 kb
Host smart-ec937fc6-eead-48c5-a5a6-a2d17876e553
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1300184436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.1300184436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.4275628283
Short name T456
Test name
Test status
Simulation time 13425571396 ps
CPU time 827.73 seconds
Started Jul 14 05:35:15 PM PDT 24
Finished Jul 14 05:49:04 PM PDT 24
Peak memory 292860 kb
Host smart-90656d8d-0255-4318-b9c0-be92e05c3a56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4275628283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.4275628283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.910213628
Short name T192
Test name
Test status
Simulation time 50551927755 ps
CPU time 4065.26 seconds
Started Jul 14 05:35:13 PM PDT 24
Finished Jul 14 06:43:00 PM PDT 24
Peak memory 644408 kb
Host smart-ce1618f1-7884-4f6b-a702-9b62bd429966
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=910213628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.910213628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.160331602
Short name T827
Test name
Test status
Simulation time 592084711465 ps
CPU time 4323.19 seconds
Started Jul 14 05:35:14 PM PDT 24
Finished Jul 14 06:47:18 PM PDT 24
Peak memory 576344 kb
Host smart-fc4f27f7-c146-43c9-b9b8-5942085b5f1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=160331602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.160331602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.2719537989
Short name T228
Test name
Test status
Simulation time 15828628 ps
CPU time 0.75 seconds
Started Jul 14 05:35:21 PM PDT 24
Finished Jul 14 05:35:24 PM PDT 24
Peak memory 205244 kb
Host smart-3604e013-2bbf-4100-b122-73ce50e23b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719537989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2719537989 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.2990372094
Short name T315
Test name
Test status
Simulation time 12880225692 ps
CPU time 177.76 seconds
Started Jul 14 05:35:22 PM PDT 24
Finished Jul 14 05:38:21 PM PDT 24
Peak memory 238080 kb
Host smart-d81d6852-d9c1-4f92-a01e-02babb39b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990372094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2990372094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.1409012224
Short name T605
Test name
Test status
Simulation time 23421494811 ps
CPU time 296.67 seconds
Started Jul 14 05:35:24 PM PDT 24
Finished Jul 14 05:40:21 PM PDT 24
Peak memory 226816 kb
Host smart-9d82c486-354e-486c-97d4-7897604c71bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409012224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1409012224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.2182878636
Short name T776
Test name
Test status
Simulation time 6256933777 ps
CPU time 28.99 seconds
Started Jul 14 05:35:21 PM PDT 24
Finished Jul 14 05:35:51 PM PDT 24
Peak memory 220112 kb
Host smart-2a24c1ed-bbe0-4c16-9694-a074abe8c083
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2182878636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2182878636 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.1354879049
Short name T691
Test name
Test status
Simulation time 343361765 ps
CPU time 13 seconds
Started Jul 14 05:35:21 PM PDT 24
Finished Jul 14 05:35:35 PM PDT 24
Peak memory 215568 kb
Host smart-326660b8-5ad7-4a2c-acb0-3d766ce1a6c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1354879049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1354879049 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.640084412
Short name T575
Test name
Test status
Simulation time 5863599172 ps
CPU time 209.61 seconds
Started Jul 14 05:35:22 PM PDT 24
Finished Jul 14 05:38:53 PM PDT 24
Peak memory 242660 kb
Host smart-4dec5ebb-9da0-4e6e-bfea-900b47f41413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640084412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.640084412 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.841594656
Short name T44
Test name
Test status
Simulation time 73961093125 ps
CPU time 390.31 seconds
Started Jul 14 05:35:23 PM PDT 24
Finished Jul 14 05:41:54 PM PDT 24
Peak memory 256628 kb
Host smart-abc2b815-2092-4c0e-a5f2-ed5bdd7ecf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841594656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.841594656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.32935399
Short name T788
Test name
Test status
Simulation time 5808618324 ps
CPU time 6.13 seconds
Started Jul 14 05:35:20 PM PDT 24
Finished Jul 14 05:35:28 PM PDT 24
Peak memory 207460 kb
Host smart-3206abbc-b0c6-44d9-8efd-00a0eeb12231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32935399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.32935399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1233864288
Short name T988
Test name
Test status
Simulation time 12343680688 ps
CPU time 1058.09 seconds
Started Jul 14 05:35:14 PM PDT 24
Finished Jul 14 05:52:53 PM PDT 24
Peak memory 338040 kb
Host smart-e19ad0be-d9f5-40c7-85fe-0a84bdd645ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233864288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1233864288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.320703034
Short name T187
Test name
Test status
Simulation time 11967025432 ps
CPU time 180.46 seconds
Started Jul 14 05:35:22 PM PDT 24
Finished Jul 14 05:38:24 PM PDT 24
Peak memory 234180 kb
Host smart-999d7147-f736-47e4-9c94-1fac78ac34f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320703034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.320703034 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1958630428
Short name T287
Test name
Test status
Simulation time 369857868 ps
CPU time 5.01 seconds
Started Jul 14 05:35:15 PM PDT 24
Finished Jul 14 05:35:21 PM PDT 24
Peak memory 221768 kb
Host smart-b8c675db-5bd6-4bb1-bc1a-cb8cab9fe47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958630428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1958630428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.1050363000
Short name T958
Test name
Test status
Simulation time 50445674077 ps
CPU time 744.64 seconds
Started Jul 14 05:35:20 PM PDT 24
Finished Jul 14 05:47:45 PM PDT 24
Peak memory 303432 kb
Host smart-c4790d8b-d912-4004-a611-dea1113b6434
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1050363000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1050363000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.913036318
Short name T537
Test name
Test status
Simulation time 514410278 ps
CPU time 5.68 seconds
Started Jul 14 05:35:21 PM PDT 24
Finished Jul 14 05:35:28 PM PDT 24
Peak memory 215544 kb
Host smart-4e5bac1f-bf44-43db-b2dc-dc2553ab47ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913036318 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.kmac_test_vectors_kmac.913036318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.2661560892
Short name T210
Test name
Test status
Simulation time 171950898 ps
CPU time 4.58 seconds
Started Jul 14 05:35:21 PM PDT 24
Finished Jul 14 05:35:27 PM PDT 24
Peak memory 215580 kb
Host smart-3c85e675-ac47-493c-a481-58b0fdb424f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661560892 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.2661560892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.1901243533
Short name T1000
Test name
Test status
Simulation time 39402366488 ps
CPU time 1648.99 seconds
Started Jul 14 05:35:19 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 393628 kb
Host smart-11e7f9e8-850b-47ef-931f-2ef6c64aeae1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1901243533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1901243533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.3367034755
Short name T571
Test name
Test status
Simulation time 128904087429 ps
CPU time 1784.13 seconds
Started Jul 14 05:35:20 PM PDT 24
Finished Jul 14 06:05:07 PM PDT 24
Peak memory 378516 kb
Host smart-acda2b16-04bc-49e3-a65c-1cdee1aa0d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3367034755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.3367034755 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.821963913
Short name T217
Test name
Test status
Simulation time 75993057909 ps
CPU time 1372.48 seconds
Started Jul 14 05:35:18 PM PDT 24
Finished Jul 14 05:58:11 PM PDT 24
Peak memory 327976 kb
Host smart-45f42d76-085b-4f84-9cca-c60442a206db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=821963913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.821963913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.916176262
Short name T1053
Test name
Test status
Simulation time 117073925711 ps
CPU time 824.5 seconds
Started Jul 14 05:35:25 PM PDT 24
Finished Jul 14 05:49:10 PM PDT 24
Peak memory 291488 kb
Host smart-f98fae39-06bc-42bf-927b-473f6c89d5d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=916176262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.916176262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.513735050
Short name T386
Test name
Test status
Simulation time 366668278153 ps
CPU time 4574.08 seconds
Started Jul 14 05:35:19 PM PDT 24
Finished Jul 14 06:51:34 PM PDT 24
Peak memory 630600 kb
Host smart-df12499e-ba68-4c50-92fc-754cee02171e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=513735050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.513735050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.2673919166
Short name T970
Test name
Test status
Simulation time 361855429830 ps
CPU time 4241.71 seconds
Started Jul 14 05:35:22 PM PDT 24
Finished Jul 14 06:46:06 PM PDT 24
Peak memory 562032 kb
Host smart-987c981a-c361-4b7f-9d34-f2a335681fb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2673919166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2673919166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.785565677
Short name T979
Test name
Test status
Simulation time 17455684 ps
CPU time 0.84 seconds
Started Jul 14 05:35:33 PM PDT 24
Finished Jul 14 05:35:34 PM PDT 24
Peak memory 205248 kb
Host smart-0981f196-d7c2-45d9-8adf-0421d2e772e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785565677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.785565677 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.1242257211
Short name T1025
Test name
Test status
Simulation time 34944435663 ps
CPU time 156.61 seconds
Started Jul 14 05:35:28 PM PDT 24
Finished Jul 14 05:38:05 PM PDT 24
Peak memory 232744 kb
Host smart-cf6c994d-16c9-403d-95cf-70ecd971f608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242257211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1242257211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.690413825
Short name T491
Test name
Test status
Simulation time 10525122311 ps
CPU time 338.7 seconds
Started Jul 14 05:35:26 PM PDT 24
Finished Jul 14 05:41:05 PM PDT 24
Peak memory 227152 kb
Host smart-8b33679a-4fcc-4f76-9130-3605f1a105e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690413825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.690413825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.3937376923
Short name T640
Test name
Test status
Simulation time 48615031 ps
CPU time 1.65 seconds
Started Jul 14 05:35:28 PM PDT 24
Finished Jul 14 05:35:30 PM PDT 24
Peak memory 215420 kb
Host smart-3845f4fa-e44e-4f42-912a-bcea24ee0a45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3937376923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3937376923 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.2615197852
Short name T527
Test name
Test status
Simulation time 2979072802 ps
CPU time 13.27 seconds
Started Jul 14 05:35:33 PM PDT 24
Finished Jul 14 05:35:47 PM PDT 24
Peak memory 219496 kb
Host smart-33caf589-1234-4750-9487-9101e6916e3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2615197852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2615197852 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.3278047545
Short name T1033
Test name
Test status
Simulation time 52638942004 ps
CPU time 87.86 seconds
Started Jul 14 05:35:28 PM PDT 24
Finished Jul 14 05:36:57 PM PDT 24
Peak memory 227840 kb
Host smart-addbf43b-7717-4771-8c87-b5dc2bfe80a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278047545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3278047545 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.423052140
Short name T505
Test name
Test status
Simulation time 3132225376 ps
CPU time 42.76 seconds
Started Jul 14 05:35:28 PM PDT 24
Finished Jul 14 05:36:11 PM PDT 24
Peak memory 231968 kb
Host smart-95c08520-76f4-4d89-858f-036551de00e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423052140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.423052140 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.1815373569
Short name T1066
Test name
Test status
Simulation time 691375738 ps
CPU time 3.93 seconds
Started Jul 14 05:35:31 PM PDT 24
Finished Jul 14 05:35:35 PM PDT 24
Peak memory 207364 kb
Host smart-065b4a03-f9aa-4b56-9d86-32ae49b257fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815373569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1815373569 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.714178728
Short name T614
Test name
Test status
Simulation time 51596884 ps
CPU time 1.35 seconds
Started Jul 14 05:35:34 PM PDT 24
Finished Jul 14 05:35:36 PM PDT 24
Peak memory 215496 kb
Host smart-8ce32d46-e9b3-45d8-964f-95f39c529417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714178728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.714178728 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1129871632
Short name T274
Test name
Test status
Simulation time 184166737843 ps
CPU time 1151.24 seconds
Started Jul 14 05:35:22 PM PDT 24
Finished Jul 14 05:54:35 PM PDT 24
Peak memory 331276 kb
Host smart-53511f87-a52a-431c-8b56-6398c8a5f90d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129871632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1129871632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.518025616
Short name T604
Test name
Test status
Simulation time 16306657505 ps
CPU time 305.45 seconds
Started Jul 14 05:35:31 PM PDT 24
Finished Jul 14 05:40:37 PM PDT 24
Peak memory 246544 kb
Host smart-07cd8ee9-3f80-4978-b8f1-c6bf7dd4d3fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518025616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.518025616 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.1839317747
Short name T133
Test name
Test status
Simulation time 371411848 ps
CPU time 19.3 seconds
Started Jul 14 05:35:20 PM PDT 24
Finished Jul 14 05:35:39 PM PDT 24
Peak memory 219172 kb
Host smart-ff3b41bd-fa4c-4b77-a349-6d64f3fd2b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839317747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1839317747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.659392818
Short name T785
Test name
Test status
Simulation time 33689662538 ps
CPU time 306.06 seconds
Started Jul 14 05:35:34 PM PDT 24
Finished Jul 14 05:40:40 PM PDT 24
Peak memory 281400 kb
Host smart-1766ae50-ff55-4cbf-b043-48ba011a727e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=659392818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.659392818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.4259003065
Short name T276
Test name
Test status
Simulation time 167438290 ps
CPU time 4.35 seconds
Started Jul 14 05:35:26 PM PDT 24
Finished Jul 14 05:35:31 PM PDT 24
Peak memory 215636 kb
Host smart-5f4562ad-5c5f-47b5-9b11-a8567f6d7e93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259003065 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.4259003065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2298888172
Short name T568
Test name
Test status
Simulation time 1037964980 ps
CPU time 4.99 seconds
Started Jul 14 05:35:27 PM PDT 24
Finished Jul 14 05:35:33 PM PDT 24
Peak memory 215652 kb
Host smart-51152cee-091c-47c2-9a96-69300dc9843e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298888172 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2298888172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.3459555294
Short name T844
Test name
Test status
Simulation time 39147944900 ps
CPU time 1516.41 seconds
Started Jul 14 05:35:29 PM PDT 24
Finished Jul 14 06:00:46 PM PDT 24
Peak memory 376556 kb
Host smart-898a97c8-1667-4935-b35f-f00a3e8f3d03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3459555294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3459555294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.23840577
Short name T851
Test name
Test status
Simulation time 384102919548 ps
CPU time 1700.58 seconds
Started Jul 14 05:35:31 PM PDT 24
Finished Jul 14 06:03:52 PM PDT 24
Peak memory 375392 kb
Host smart-c583173e-5eb2-4ea8-b89d-adb02d558624
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=23840577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.23840577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.2130694099
Short name T657
Test name
Test status
Simulation time 192189373448 ps
CPU time 1255.36 seconds
Started Jul 14 05:35:26 PM PDT 24
Finished Jul 14 05:56:23 PM PDT 24
Peak memory 330252 kb
Host smart-1a716aba-282b-4729-b66f-b212e06d9ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2130694099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.2130694099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.367447832
Short name T513
Test name
Test status
Simulation time 89086799013 ps
CPU time 937.25 seconds
Started Jul 14 05:35:26 PM PDT 24
Finished Jul 14 05:51:04 PM PDT 24
Peak memory 296684 kb
Host smart-3ed6f4a4-9f11-4b85-bfe9-190ee3e124d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=367447832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.367447832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.665996146
Short name T407
Test name
Test status
Simulation time 177395587428 ps
CPU time 4610.7 seconds
Started Jul 14 05:35:26 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 640032 kb
Host smart-1e119b46-9b08-41b3-a22b-863681b4236d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=665996146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.665996146 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.2408214039
Short name T369
Test name
Test status
Simulation time 173354222868 ps
CPU time 3352.43 seconds
Started Jul 14 05:35:27 PM PDT 24
Finished Jul 14 06:31:20 PM PDT 24
Peak memory 562628 kb
Host smart-359f8aff-1d98-4435-80d5-e318ea7e6445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2408214039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.2408214039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.2685736704
Short name T874
Test name
Test status
Simulation time 42141351 ps
CPU time 0.76 seconds
Started Jul 14 05:35:46 PM PDT 24
Finished Jul 14 05:35:47 PM PDT 24
Peak memory 205184 kb
Host smart-59e08e5e-9550-4e09-801c-ab73555b9a2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685736704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2685736704 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.936418457
Short name T494
Test name
Test status
Simulation time 32428593743 ps
CPU time 41.94 seconds
Started Jul 14 05:35:41 PM PDT 24
Finished Jul 14 05:36:23 PM PDT 24
Peak memory 223860 kb
Host smart-fe8803fa-7498-47aa-ba86-7267b93f779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936418457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.936418457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.381453401
Short name T597
Test name
Test status
Simulation time 14590497860 ps
CPU time 111.99 seconds
Started Jul 14 05:35:32 PM PDT 24
Finished Jul 14 05:37:25 PM PDT 24
Peak memory 221820 kb
Host smart-a8c0fe45-fcf1-4fa0-99e3-415377892fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381453401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.381453401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.2727332073
Short name T850
Test name
Test status
Simulation time 2603576715 ps
CPU time 36.53 seconds
Started Jul 14 05:35:36 PM PDT 24
Finished Jul 14 05:36:13 PM PDT 24
Peak memory 220388 kb
Host smart-d0dfa774-f99a-43fc-884c-c8a1aeca71cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2727332073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2727332073 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.746298210
Short name T735
Test name
Test status
Simulation time 79672593 ps
CPU time 5.43 seconds
Started Jul 14 05:35:42 PM PDT 24
Finished Jul 14 05:35:47 PM PDT 24
Peak memory 219680 kb
Host smart-c1054fd1-6f4a-4aff-bd96-6cd09ae691c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=746298210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.746298210 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2104269525
Short name T812
Test name
Test status
Simulation time 3299351934 ps
CPU time 136.96 seconds
Started Jul 14 05:35:40 PM PDT 24
Finished Jul 14 05:37:58 PM PDT 24
Peak memory 235624 kb
Host smart-b4a5ff4e-abcc-42d7-a394-739fe2beb2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104269525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2104269525 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.2805524340
Short name T321
Test name
Test status
Simulation time 24211662372 ps
CPU time 245.39 seconds
Started Jul 14 05:35:38 PM PDT 24
Finished Jul 14 05:39:44 PM PDT 24
Peak memory 249092 kb
Host smart-a45f476d-e4b8-4b96-bfa9-8232e78014e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805524340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2805524340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.3151688852
Short name T710
Test name
Test status
Simulation time 4401316860 ps
CPU time 6.33 seconds
Started Jul 14 05:35:39 PM PDT 24
Finished Jul 14 05:35:46 PM PDT 24
Peak memory 207456 kb
Host smart-2335aa68-4dfa-47d2-9789-52d7427c553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151688852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3151688852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.1407269849
Short name T815
Test name
Test status
Simulation time 51504179 ps
CPU time 1.14 seconds
Started Jul 14 05:35:48 PM PDT 24
Finished Jul 14 05:35:50 PM PDT 24
Peak memory 215536 kb
Host smart-12cdb043-4251-4d7f-b477-ee07fbffb78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407269849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1407269849 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.2944610816
Short name T182
Test name
Test status
Simulation time 28292808435 ps
CPU time 883.78 seconds
Started Jul 14 05:35:34 PM PDT 24
Finished Jul 14 05:50:18 PM PDT 24
Peak memory 299636 kb
Host smart-ef123e06-be7c-40fd-8435-5364a5f44475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944610816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.2944610816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.1108254765
Short name T328
Test name
Test status
Simulation time 8295473396 ps
CPU time 51.37 seconds
Started Jul 14 05:35:32 PM PDT 24
Finished Jul 14 05:36:24 PM PDT 24
Peak memory 223780 kb
Host smart-0ebe5e7f-297f-4f7b-9292-c21a3313c47d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108254765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1108254765 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.2788496816
Short name T360
Test name
Test status
Simulation time 424173059 ps
CPU time 9.23 seconds
Started Jul 14 05:35:33 PM PDT 24
Finished Jul 14 05:35:43 PM PDT 24
Peak memory 216896 kb
Host smart-6f9cea01-5f53-4211-a01b-dfcd33f56d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788496816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2788496816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.3511161964
Short name T886
Test name
Test status
Simulation time 12730184739 ps
CPU time 333.78 seconds
Started Jul 14 05:35:46 PM PDT 24
Finished Jul 14 05:41:20 PM PDT 24
Peak memory 285520 kb
Host smart-21bc6b77-cfb1-4d44-87fd-4a9291bf5bc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3511161964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3511161964 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.3474544340
Short name T918
Test name
Test status
Simulation time 394096026 ps
CPU time 4.01 seconds
Started Jul 14 05:35:39 PM PDT 24
Finished Jul 14 05:35:44 PM PDT 24
Peak memory 215724 kb
Host smart-afbbb92e-ae29-4ac9-96ca-9628cb148959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474544340 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.3474544340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.23640214
Short name T531
Test name
Test status
Simulation time 65147158 ps
CPU time 3.85 seconds
Started Jul 14 05:35:39 PM PDT 24
Finished Jul 14 05:35:43 PM PDT 24
Peak memory 215596 kb
Host smart-4d348e6f-2ae9-4010-b24a-5e6abdb36520
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23640214 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.kmac_test_vectors_kmac_xof.23640214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.2530360150
Short name T427
Test name
Test status
Simulation time 76868414466 ps
CPU time 1661.85 seconds
Started Jul 14 05:35:33 PM PDT 24
Finished Jul 14 06:03:15 PM PDT 24
Peak memory 399972 kb
Host smart-99927c1c-763e-417a-afc8-a26a16d78c4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2530360150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.2530360150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.2912187700
Short name T291
Test name
Test status
Simulation time 19285197027 ps
CPU time 1453 seconds
Started Jul 14 05:35:32 PM PDT 24
Finished Jul 14 05:59:45 PM PDT 24
Peak memory 373688 kb
Host smart-1a272782-3ba1-4e78-84ea-484bae604b16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2912187700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.2912187700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.407471735
Short name T417
Test name
Test status
Simulation time 296218381210 ps
CPU time 1526.53 seconds
Started Jul 14 05:35:33 PM PDT 24
Finished Jul 14 06:01:01 PM PDT 24
Peak memory 338200 kb
Host smart-90ab9690-439e-47f4-83bd-c97e51746ba9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=407471735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.407471735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.2903584683
Short name T408
Test name
Test status
Simulation time 103987078838 ps
CPU time 1016.35 seconds
Started Jul 14 05:35:33 PM PDT 24
Finished Jul 14 05:52:30 PM PDT 24
Peak memory 298772 kb
Host smart-ae06de31-7512-4789-8a78-57ec4a3fe9ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2903584683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.2903584683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.2871476969
Short name T841
Test name
Test status
Simulation time 219341756977 ps
CPU time 3953.54 seconds
Started Jul 14 05:35:33 PM PDT 24
Finished Jul 14 06:41:27 PM PDT 24
Peak memory 640656 kb
Host smart-ec71102b-0f22-4c07-8ff8-29955e40eea3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2871476969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.2871476969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.1929124056
Short name T998
Test name
Test status
Simulation time 892379302520 ps
CPU time 4473.4 seconds
Started Jul 14 05:35:40 PM PDT 24
Finished Jul 14 06:50:15 PM PDT 24
Peak memory 551400 kb
Host smart-99e11345-ffce-44e8-b409-44533d84c809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1929124056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.1929124056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.3624423968
Short name T391
Test name
Test status
Simulation time 49821980 ps
CPU time 0.81 seconds
Started Jul 14 05:35:52 PM PDT 24
Finished Jul 14 05:35:53 PM PDT 24
Peak memory 205196 kb
Host smart-ba0aeac3-b870-4b9e-8f77-d7156e88b09f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624423968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3624423968 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.4110809056
Short name T327
Test name
Test status
Simulation time 23630063768 ps
CPU time 134.91 seconds
Started Jul 14 05:35:45 PM PDT 24
Finished Jul 14 05:38:01 PM PDT 24
Peak memory 232056 kb
Host smart-3dd767da-18ac-4c80-a14d-0b57627197a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110809056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.4110809056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.2085913479
Short name T728
Test name
Test status
Simulation time 14887756978 ps
CPU time 335.41 seconds
Started Jul 14 05:35:44 PM PDT 24
Finished Jul 14 05:41:19 PM PDT 24
Peak memory 235772 kb
Host smart-f60bfc60-2196-44ae-a0ca-0a863f0c867e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085913479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2085913479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.698022789
Short name T843
Test name
Test status
Simulation time 1674730924 ps
CPU time 30.15 seconds
Started Jul 14 05:35:51 PM PDT 24
Finished Jul 14 05:36:21 PM PDT 24
Peak memory 223868 kb
Host smart-f5787bb3-3f09-46ab-88a9-0dd21d25a032
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=698022789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.698022789 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.3885561200
Short name T230
Test name
Test status
Simulation time 1446405222 ps
CPU time 26.29 seconds
Started Jul 14 05:35:51 PM PDT 24
Finished Jul 14 05:36:18 PM PDT 24
Peak memory 219880 kb
Host smart-160973b3-1f79-4941-8d2a-f0eb721a6fba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3885561200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3885561200 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.865927822
Short name T154
Test name
Test status
Simulation time 14241423779 ps
CPU time 260.81 seconds
Started Jul 14 05:35:45 PM PDT 24
Finished Jul 14 05:40:06 PM PDT 24
Peak memory 242296 kb
Host smart-89029835-227b-494d-a774-4391e4cbe3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865927822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.865927822 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.2349703475
Short name T803
Test name
Test status
Simulation time 8463196921 ps
CPU time 243.96 seconds
Started Jul 14 05:35:43 PM PDT 24
Finished Jul 14 05:39:47 PM PDT 24
Peak memory 251284 kb
Host smart-0cd73d27-8608-4c3d-aa67-34bad4f2ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349703475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2349703475 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.340217532
Short name T32
Test name
Test status
Simulation time 30448876 ps
CPU time 1.16 seconds
Started Jul 14 05:35:50 PM PDT 24
Finished Jul 14 05:35:52 PM PDT 24
Peak memory 215536 kb
Host smart-b02a0d31-508c-4811-8681-8f2e1261e93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340217532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.340217532 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.799735330
Short name T219
Test name
Test status
Simulation time 238044536275 ps
CPU time 2411.56 seconds
Started Jul 14 05:35:49 PM PDT 24
Finished Jul 14 06:16:01 PM PDT 24
Peak memory 448508 kb
Host smart-1f44e1f1-912d-4626-886c-3d42998f74e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799735330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_an
d_output.799735330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.2462760505
Short name T484
Test name
Test status
Simulation time 51640154692 ps
CPU time 305.42 seconds
Started Jul 14 05:35:46 PM PDT 24
Finished Jul 14 05:40:52 PM PDT 24
Peak memory 244432 kb
Host smart-04aeb14c-5227-4d71-b498-b56b75e18663
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462760505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2462760505 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.1042109390
Short name T966
Test name
Test status
Simulation time 51100331489 ps
CPU time 82.57 seconds
Started Jul 14 05:35:44 PM PDT 24
Finished Jul 14 05:37:07 PM PDT 24
Peak memory 220956 kb
Host smart-0d69a267-5288-4899-9040-31d88eeee52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042109390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1042109390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.2638234688
Short name T255
Test name
Test status
Simulation time 57661317882 ps
CPU time 1045.16 seconds
Started Jul 14 05:35:53 PM PDT 24
Finished Jul 14 05:53:19 PM PDT 24
Peak memory 360112 kb
Host smart-9f4e99d0-44d5-4d63-815f-e22db2c9a445
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2638234688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2638234688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.3643765082
Short name T275
Test name
Test status
Simulation time 120936735 ps
CPU time 3.84 seconds
Started Jul 14 05:35:48 PM PDT 24
Finished Jul 14 05:35:53 PM PDT 24
Peak memory 215620 kb
Host smart-8377c505-bb6f-4548-b421-557cfcb52da4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643765082 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.3643765082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3746469152
Short name T581
Test name
Test status
Simulation time 66855440 ps
CPU time 3.84 seconds
Started Jul 14 05:35:44 PM PDT 24
Finished Jul 14 05:35:48 PM PDT 24
Peak memory 208752 kb
Host smart-78ed828d-de10-439d-a1f0-6b17774c2ca3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746469152 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3746469152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.2558287121
Short name T649
Test name
Test status
Simulation time 539172668341 ps
CPU time 1851.79 seconds
Started Jul 14 05:35:45 PM PDT 24
Finished Jul 14 06:06:37 PM PDT 24
Peak memory 390600 kb
Host smart-78a3212c-ba21-447b-8dd6-466a5f049bdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2558287121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.2558287121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.1980540962
Short name T336
Test name
Test status
Simulation time 95102586020 ps
CPU time 1764.81 seconds
Started Jul 14 05:35:46 PM PDT 24
Finished Jul 14 06:05:11 PM PDT 24
Peak memory 373116 kb
Host smart-65215519-89ba-48fa-a21c-4a59da495979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1980540962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.1980540962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.735196312
Short name T1076
Test name
Test status
Simulation time 104217065487 ps
CPU time 1091.73 seconds
Started Jul 14 05:35:45 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 333764 kb
Host smart-a2664d76-aff7-45c4-97f4-977b13fd4dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=735196312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.735196312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.2785806730
Short name T521
Test name
Test status
Simulation time 271112877629 ps
CPU time 992.33 seconds
Started Jul 14 05:35:44 PM PDT 24
Finished Jul 14 05:52:17 PM PDT 24
Peak memory 294060 kb
Host smart-66f80e0b-eecb-476a-836b-06055ca4ba7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2785806730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.2785806730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.2910361743
Short name T215
Test name
Test status
Simulation time 769131641617 ps
CPU time 4576.99 seconds
Started Jul 14 05:35:45 PM PDT 24
Finished Jul 14 06:52:03 PM PDT 24
Peak memory 634700 kb
Host smart-ac4eed12-1404-42c0-9ebb-1da3a49647d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2910361743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.2910361743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.19356254
Short name T594
Test name
Test status
Simulation time 180156630275 ps
CPU time 3488.66 seconds
Started Jul 14 05:35:44 PM PDT 24
Finished Jul 14 06:33:54 PM PDT 24
Peak memory 559920 kb
Host smart-3fafc6dc-64da-4d19-acaa-584fcf473491
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=19356254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.19356254 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.180524950
Short name T903
Test name
Test status
Simulation time 87526867 ps
CPU time 0.86 seconds
Started Jul 14 05:36:27 PM PDT 24
Finished Jul 14 05:36:28 PM PDT 24
Peak memory 205236 kb
Host smart-adb28827-7d09-487a-90bb-603fa2d5dfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180524950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.180524950 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3083263181
Short name T528
Test name
Test status
Simulation time 10633983959 ps
CPU time 259.04 seconds
Started Jul 14 05:35:55 PM PDT 24
Finished Jul 14 05:40:15 PM PDT 24
Peak memory 244516 kb
Host smart-fdc90935-0c68-4eb3-a1d5-51ea5d8700f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083263181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3083263181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.501510529
Short name T934
Test name
Test status
Simulation time 8891622352 ps
CPU time 727.68 seconds
Started Jul 14 05:35:55 PM PDT 24
Finished Jul 14 05:48:03 PM PDT 24
Peak memory 231660 kb
Host smart-0c410e8f-c2e0-4581-95c6-ae0bb6a6b6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501510529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.501510529 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.2613251414
Short name T589
Test name
Test status
Simulation time 1012679159 ps
CPU time 25.05 seconds
Started Jul 14 05:36:26 PM PDT 24
Finished Jul 14 05:36:52 PM PDT 24
Peak memory 223696 kb
Host smart-0fb3c7a5-d8fc-4044-a5b0-8355d43e301d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2613251414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2613251414 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.453455097
Short name T453
Test name
Test status
Simulation time 499645554 ps
CPU time 11.83 seconds
Started Jul 14 05:36:28 PM PDT 24
Finished Jul 14 05:36:40 PM PDT 24
Peak memory 217052 kb
Host smart-dae7199a-726a-424f-8c36-8fb7d7a10de6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=453455097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.453455097 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.3495739553
Short name T574
Test name
Test status
Simulation time 21769597720 ps
CPU time 97.84 seconds
Started Jul 14 05:36:26 PM PDT 24
Finished Jul 14 05:38:04 PM PDT 24
Peak memory 227616 kb
Host smart-8642c693-b9a2-4611-b216-c4de00bf5aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495739553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3495739553 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.2696888784
Short name T945
Test name
Test status
Simulation time 11391484901 ps
CPU time 213.52 seconds
Started Jul 14 05:36:30 PM PDT 24
Finished Jul 14 05:40:04 PM PDT 24
Peak memory 249532 kb
Host smart-e25b41a5-d91d-4558-988e-2f6830ba7c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696888784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2696888784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.2287832848
Short name T545
Test name
Test status
Simulation time 839393126 ps
CPU time 2.38 seconds
Started Jul 14 05:36:27 PM PDT 24
Finished Jul 14 05:36:30 PM PDT 24
Peak memory 207300 kb
Host smart-25ff355d-08a4-4715-a41a-ef2f8e505041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287832848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2287832848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.1621663895
Short name T5
Test name
Test status
Simulation time 52021481 ps
CPU time 1.2 seconds
Started Jul 14 05:36:27 PM PDT 24
Finished Jul 14 05:36:29 PM PDT 24
Peak memory 215520 kb
Host smart-7d7196cb-7c9e-4490-8bbb-f887d6fc8bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621663895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1621663895 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.1205731951
Short name T421
Test name
Test status
Simulation time 29987477056 ps
CPU time 2130.71 seconds
Started Jul 14 05:35:54 PM PDT 24
Finished Jul 14 06:11:25 PM PDT 24
Peak memory 458008 kb
Host smart-e383badc-c2a4-4f9d-9b8d-8b4429ac022b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205731951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.1205731951 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.3268625079
Short name T355
Test name
Test status
Simulation time 12824268581 ps
CPU time 239.41 seconds
Started Jul 14 05:35:55 PM PDT 24
Finished Jul 14 05:39:55 PM PDT 24
Peak memory 243256 kb
Host smart-91ffff11-80fc-41a7-899e-55ddf7c56c24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268625079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3268625079 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.3515588838
Short name T524
Test name
Test status
Simulation time 828354834 ps
CPU time 13.98 seconds
Started Jul 14 05:35:51 PM PDT 24
Finished Jul 14 05:36:06 PM PDT 24
Peak memory 218644 kb
Host smart-20bb1cd3-e664-4d68-a885-e845613844c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515588838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3515588838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.2656591644
Short name T297
Test name
Test status
Simulation time 676712212250 ps
CPU time 1289.42 seconds
Started Jul 14 05:36:27 PM PDT 24
Finished Jul 14 05:57:57 PM PDT 24
Peak memory 347032 kb
Host smart-e7c6591f-f041-4fa8-90c8-8a8e6e9cf3d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2656591644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2656591644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.1186804423
Short name T286
Test name
Test status
Simulation time 225389024 ps
CPU time 5.03 seconds
Started Jul 14 05:35:56 PM PDT 24
Finished Jul 14 05:36:02 PM PDT 24
Peak memory 215576 kb
Host smart-dbe59f4c-3def-48c1-b6b4-713a5a1b24bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186804423 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.1186804423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3978954694
Short name T992
Test name
Test status
Simulation time 2008806021 ps
CPU time 5.4 seconds
Started Jul 14 05:35:57 PM PDT 24
Finished Jul 14 05:36:02 PM PDT 24
Peak memory 215596 kb
Host smart-4393595c-fbc7-4fbb-80e6-042f2979f41a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978954694 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3978954694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.1176456843
Short name T680
Test name
Test status
Simulation time 580136173308 ps
CPU time 1954.49 seconds
Started Jul 14 05:35:56 PM PDT 24
Finished Jul 14 06:08:31 PM PDT 24
Peak memory 378968 kb
Host smart-ed287634-464c-43c6-a5ae-2d6a9897040f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1176456843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.1176456843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.4116128757
Short name T375
Test name
Test status
Simulation time 36335498145 ps
CPU time 1528.86 seconds
Started Jul 14 05:35:58 PM PDT 24
Finished Jul 14 06:01:27 PM PDT 24
Peak memory 375044 kb
Host smart-27ef23da-b6e0-4e64-a83a-2ff1cd330914
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4116128757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.4116128757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.1612890358
Short name T35
Test name
Test status
Simulation time 71060520372 ps
CPU time 1376.8 seconds
Started Jul 14 05:35:55 PM PDT 24
Finished Jul 14 05:58:52 PM PDT 24
Peak memory 338564 kb
Host smart-f2e9a9fe-b070-4d2b-940c-c23bb24228dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1612890358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.1612890358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.2341654637
Short name T337
Test name
Test status
Simulation time 37752281535 ps
CPU time 754.2 seconds
Started Jul 14 05:35:55 PM PDT 24
Finished Jul 14 05:48:30 PM PDT 24
Peak memory 293580 kb
Host smart-41d20380-2066-4049-a432-6601501e1075
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2341654637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.2341654637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.1686241738
Short name T1050
Test name
Test status
Simulation time 213149308956 ps
CPU time 4099.07 seconds
Started Jul 14 05:35:58 PM PDT 24
Finished Jul 14 06:44:18 PM PDT 24
Peak memory 657060 kb
Host smart-d8da0c5d-ccf7-4ceb-83e0-df10f451bab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1686241738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.1686241738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.73015382
Short name T806
Test name
Test status
Simulation time 252085237624 ps
CPU time 4004.13 seconds
Started Jul 14 05:35:58 PM PDT 24
Finished Jul 14 06:42:43 PM PDT 24
Peak memory 551468 kb
Host smart-d19cd87e-fb49-4576-98de-1f8016800290
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=73015382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.73015382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.1167057098
Short name T881
Test name
Test status
Simulation time 18493406 ps
CPU time 0.78 seconds
Started Jul 14 05:34:11 PM PDT 24
Finished Jul 14 05:34:13 PM PDT 24
Peak memory 205292 kb
Host smart-b12900e3-c056-438e-9abb-005e96608a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167057098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1167057098 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.2686699626
Short name T991
Test name
Test status
Simulation time 10514492113 ps
CPU time 215.87 seconds
Started Jul 14 05:34:11 PM PDT 24
Finished Jul 14 05:37:48 PM PDT 24
Peak memory 241708 kb
Host smart-6034506d-d854-4ec4-8a39-f363e58af846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686699626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2686699626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.341571202
Short name T1032
Test name
Test status
Simulation time 28877917963 ps
CPU time 270.7 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 05:38:42 PM PDT 24
Peak memory 243836 kb
Host smart-ca1c80d8-21a1-4d45-94b4-e180d2bcd533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341571202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.341571202 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.533233437
Short name T261
Test name
Test status
Simulation time 638639147 ps
CPU time 25.73 seconds
Started Jul 14 05:34:12 PM PDT 24
Finished Jul 14 05:34:39 PM PDT 24
Peak memory 217568 kb
Host smart-7b42b07c-3066-4135-aa1e-861f1d35636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533233437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.533233437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.3775929542
Short name T658
Test name
Test status
Simulation time 421996597 ps
CPU time 23.92 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 05:34:35 PM PDT 24
Peak memory 231876 kb
Host smart-5705f65d-4d1c-447d-844f-6c75f46ca6d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3775929542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3775929542 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.499338851
Short name T1017
Test name
Test status
Simulation time 1731935238 ps
CPU time 15.89 seconds
Started Jul 14 05:34:08 PM PDT 24
Finished Jul 14 05:34:25 PM PDT 24
Peak memory 223556 kb
Host smart-a6f798b1-7516-4c57-aa25-f536238cff52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=499338851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.499338851 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3128108452
Short name T783
Test name
Test status
Simulation time 19063182653 ps
CPU time 113.71 seconds
Started Jul 14 05:34:14 PM PDT 24
Finished Jul 14 05:36:08 PM PDT 24
Peak memory 232104 kb
Host smart-b19ff785-c186-4aad-8840-00bb8b288386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128108452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3128108452 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.2041711196
Short name T1036
Test name
Test status
Simulation time 43940521972 ps
CPU time 253.82 seconds
Started Jul 14 05:34:09 PM PDT 24
Finished Jul 14 05:38:24 PM PDT 24
Peak memory 252004 kb
Host smart-376b7661-ffaf-4f1e-bca4-f866271ccc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041711196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2041711196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.2369198123
Short name T556
Test name
Test status
Simulation time 1869176466 ps
CPU time 4.99 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 05:34:17 PM PDT 24
Peak memory 215496 kb
Host smart-89825826-e510-4fce-90ce-12336fb8ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369198123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2369198123 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.3510520222
Short name T940
Test name
Test status
Simulation time 57671259 ps
CPU time 1.25 seconds
Started Jul 14 05:34:12 PM PDT 24
Finished Jul 14 05:34:14 PM PDT 24
Peak memory 220076 kb
Host smart-e75b53a6-2841-410e-a5b9-658e6303654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510520222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3510520222 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.3282528902
Short name T648
Test name
Test status
Simulation time 1215122303450 ps
CPU time 2574.7 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 06:17:06 PM PDT 24
Peak memory 462924 kb
Host smart-99a9cdf2-5939-49c3-a5fa-d5d1427fa7c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282528902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.3282528902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.1582114357
Short name T390
Test name
Test status
Simulation time 33483062130 ps
CPU time 158.63 seconds
Started Jul 14 05:34:12 PM PDT 24
Finished Jul 14 05:36:52 PM PDT 24
Peak memory 234652 kb
Host smart-e33960a4-d9fb-4e84-9855-c1f9703e1511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582114357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1582114357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.4120807628
Short name T69
Test name
Test status
Simulation time 23668058594 ps
CPU time 30.17 seconds
Started Jul 14 05:34:11 PM PDT 24
Finished Jul 14 05:34:42 PM PDT 24
Peak memory 241212 kb
Host smart-2d4d6f66-25c0-4ceb-8a9c-4f5a45f1e1dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120807628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4120807628 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.1016384314
Short name T309
Test name
Test status
Simulation time 15956013506 ps
CPU time 104.53 seconds
Started Jul 14 05:34:06 PM PDT 24
Finished Jul 14 05:35:51 PM PDT 24
Peak memory 227992 kb
Host smart-336310ce-1d77-4208-b5f7-0cd4985ecf93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016384314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1016384314 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.1241618417
Short name T351
Test name
Test status
Simulation time 3348471070 ps
CPU time 17.66 seconds
Started Jul 14 05:34:09 PM PDT 24
Finished Jul 14 05:34:28 PM PDT 24
Peak memory 219260 kb
Host smart-7f97e9f3-e7f2-42d5-8f8b-a5279b336b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241618417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.1241618417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2883509158
Short name T924
Test name
Test status
Simulation time 195325710846 ps
CPU time 593.51 seconds
Started Jul 14 05:34:14 PM PDT 24
Finished Jul 14 05:44:08 PM PDT 24
Peak memory 302732 kb
Host smart-f15e7025-7842-462f-b9b2-c79dbb79b250
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2883509158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2883509158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.3769657719
Short name T715
Test name
Test status
Simulation time 257514944 ps
CPU time 4.31 seconds
Started Jul 14 05:34:08 PM PDT 24
Finished Jul 14 05:34:14 PM PDT 24
Peak memory 215620 kb
Host smart-3fb6673f-4f14-4a23-aa43-454cad7b401f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769657719 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.3769657719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.790151647
Short name T807
Test name
Test status
Simulation time 97039869 ps
CPU time 4.37 seconds
Started Jul 14 05:34:05 PM PDT 24
Finished Jul 14 05:34:10 PM PDT 24
Peak memory 215692 kb
Host smart-2dffc726-fc83-4c48-8ae8-425a843f0359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790151647 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.790151647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.4115950835
Short name T364
Test name
Test status
Simulation time 38402501913 ps
CPU time 1530.8 seconds
Started Jul 14 05:34:11 PM PDT 24
Finished Jul 14 05:59:43 PM PDT 24
Peak memory 376752 kb
Host smart-db305482-26fa-45df-996c-ac92b4192acb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4115950835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.4115950835 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.2228438811
Short name T848
Test name
Test status
Simulation time 317595381040 ps
CPU time 1918.28 seconds
Started Jul 14 05:34:11 PM PDT 24
Finished Jul 14 06:06:10 PM PDT 24
Peak memory 376256 kb
Host smart-8128486d-2f1d-4266-965a-938f64952c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2228438811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2228438811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.3188014728
Short name T232
Test name
Test status
Simulation time 75751079433 ps
CPU time 1163.96 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:53:32 PM PDT 24
Peak memory 335048 kb
Host smart-60db6af8-09ce-4985-b190-86b5851d6d25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3188014728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3188014728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.2609572651
Short name T373
Test name
Test status
Simulation time 9693019104 ps
CPU time 803.72 seconds
Started Jul 14 05:34:09 PM PDT 24
Finished Jul 14 05:47:34 PM PDT 24
Peak memory 298832 kb
Host smart-9e13d0e9-d208-4bc0-992a-8e9f068c24b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2609572651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2609572651 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.3534476958
Short name T495
Test name
Test status
Simulation time 531765187144 ps
CPU time 5128.96 seconds
Started Jul 14 05:34:11 PM PDT 24
Finished Jul 14 06:59:42 PM PDT 24
Peak memory 644548 kb
Host smart-7d3a04e2-dfad-4e77-a4e3-78cffd2dfb9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3534476958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3534476958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.2665906709
Short name T819
Test name
Test status
Simulation time 89466499448 ps
CPU time 3379.89 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 06:30:29 PM PDT 24
Peak memory 554800 kb
Host smart-7ee26783-a1d3-4863-a6b0-430a901effd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2665906709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2665906709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.903426678
Short name T929
Test name
Test status
Simulation time 17216866 ps
CPU time 0.81 seconds
Started Jul 14 05:36:32 PM PDT 24
Finished Jul 14 05:36:33 PM PDT 24
Peak memory 205196 kb
Host smart-01f3fda5-d02d-41de-a40a-8d49f38fbdde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903426678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.903426678 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.1232106557
Short name T1016
Test name
Test status
Simulation time 19476724337 ps
CPU time 91.09 seconds
Started Jul 14 05:36:29 PM PDT 24
Finished Jul 14 05:38:00 PM PDT 24
Peak memory 229704 kb
Host smart-f3121e25-a5a3-4230-9b22-9f7bb8d3c970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232106557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1232106557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2335727009
Short name T652
Test name
Test status
Simulation time 5208129471 ps
CPU time 409.78 seconds
Started Jul 14 05:36:28 PM PDT 24
Finished Jul 14 05:43:18 PM PDT 24
Peak memory 229168 kb
Host smart-c6f58acc-8829-47c1-9eab-b6c135046156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335727009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2335727009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.115417848
Short name T607
Test name
Test status
Simulation time 11100192037 ps
CPU time 111.43 seconds
Started Jul 14 05:36:30 PM PDT 24
Finished Jul 14 05:38:22 PM PDT 24
Peak memory 232312 kb
Host smart-b5b7b02e-569e-47a7-9c7f-2c2ecfaac820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115417848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.115417848 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.4021002789
Short name T489
Test name
Test status
Simulation time 34377146153 ps
CPU time 190.34 seconds
Started Jul 14 05:36:29 PM PDT 24
Finished Jul 14 05:39:40 PM PDT 24
Peak memory 256488 kb
Host smart-e34a723f-2c2d-45ba-881b-ad2ad2fb2eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021002789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.4021002789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.2589069903
Short name T3
Test name
Test status
Simulation time 2162262682 ps
CPU time 5.49 seconds
Started Jul 14 05:36:30 PM PDT 24
Finished Jul 14 05:36:36 PM PDT 24
Peak memory 207348 kb
Host smart-3baa1d2a-4607-48c1-b1f7-954d578653c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589069903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2589069903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.3053471691
Short name T60
Test name
Test status
Simulation time 212547236 ps
CPU time 1.41 seconds
Started Jul 14 05:36:31 PM PDT 24
Finished Jul 14 05:36:33 PM PDT 24
Peak memory 215780 kb
Host smart-dfa175c4-e86c-43b4-88b7-d0e8af92f8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053471691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3053471691 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1817314641
Short name T1061
Test name
Test status
Simulation time 29820783519 ps
CPU time 889.82 seconds
Started Jul 14 05:36:26 PM PDT 24
Finished Jul 14 05:51:16 PM PDT 24
Peak memory 300188 kb
Host smart-e62c32ab-2a83-4538-a15a-c82d317d9693
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817314641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1817314641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_smoke.2495033135
Short name T883
Test name
Test status
Simulation time 2157293274 ps
CPU time 49.06 seconds
Started Jul 14 05:36:29 PM PDT 24
Finished Jul 14 05:37:18 PM PDT 24
Peak memory 215712 kb
Host smart-7eda2cbf-7eb4-449e-9029-1fb1a3217de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495033135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2495033135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.3038489111
Short name T651
Test name
Test status
Simulation time 343397768 ps
CPU time 3.75 seconds
Started Jul 14 05:36:32 PM PDT 24
Finished Jul 14 05:36:37 PM PDT 24
Peak memory 215588 kb
Host smart-b6596598-ffb2-47e4-a024-897b5162659c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3038489111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3038489111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.3838586153
Short name T353
Test name
Test status
Simulation time 71402789 ps
CPU time 4.37 seconds
Started Jul 14 05:36:32 PM PDT 24
Finished Jul 14 05:36:37 PM PDT 24
Peak memory 208668 kb
Host smart-07bb2e46-e287-42b2-be33-1af9129257c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838586153 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.3838586153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.1063574893
Short name T249
Test name
Test status
Simulation time 217028754 ps
CPU time 4.27 seconds
Started Jul 14 05:36:28 PM PDT 24
Finished Jul 14 05:36:33 PM PDT 24
Peak memory 215616 kb
Host smart-7bf067ec-ed8f-472a-8da1-5f94c0024901
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063574893 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.1063574893 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.486438297
Short name T246
Test name
Test status
Simulation time 69689952662 ps
CPU time 1571.63 seconds
Started Jul 14 05:36:26 PM PDT 24
Finished Jul 14 06:02:38 PM PDT 24
Peak memory 391436 kb
Host smart-9457421c-5ea3-4e0a-9b2d-600248b09015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=486438297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.486438297 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.2671605743
Short name T982
Test name
Test status
Simulation time 92883335507 ps
CPU time 1797.8 seconds
Started Jul 14 05:36:27 PM PDT 24
Finished Jul 14 06:06:26 PM PDT 24
Peak memory 376016 kb
Host smart-4177520f-809e-4b4b-8ea5-ef68d46559bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2671605743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2671605743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.419196975
Short name T247
Test name
Test status
Simulation time 49653758628 ps
CPU time 1151.65 seconds
Started Jul 14 05:36:30 PM PDT 24
Finished Jul 14 05:55:42 PM PDT 24
Peak memory 330432 kb
Host smart-1b871d78-1ca5-4e31-a088-d53f360325e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=419196975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.419196975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.442034996
Short name T699
Test name
Test status
Simulation time 130581947265 ps
CPU time 946.88 seconds
Started Jul 14 05:36:27 PM PDT 24
Finished Jul 14 05:52:15 PM PDT 24
Peak memory 294388 kb
Host smart-1201dbc7-4ea2-4a7f-9126-23bb97ca2145
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=442034996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.442034996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.1795892197
Short name T863
Test name
Test status
Simulation time 2871886928575 ps
CPU time 4936.75 seconds
Started Jul 14 05:36:28 PM PDT 24
Finished Jul 14 06:58:46 PM PDT 24
Peak memory 651408 kb
Host smart-70dc4753-a933-4762-bd7c-0403ca09fcc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1795892197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.1795892197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.3290608651
Short name T239
Test name
Test status
Simulation time 392086259412 ps
CPU time 3582.85 seconds
Started Jul 14 05:36:27 PM PDT 24
Finished Jul 14 06:36:10 PM PDT 24
Peak memory 559464 kb
Host smart-3d93a43e-bbb2-46e1-9fa3-205f771b0ace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3290608651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3290608651 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1689546555
Short name T420
Test name
Test status
Simulation time 14849658 ps
CPU time 0.78 seconds
Started Jul 14 05:36:38 PM PDT 24
Finished Jul 14 05:36:40 PM PDT 24
Peak memory 205188 kb
Host smart-06ba3490-02da-4df3-a18d-bdc0f3d04a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689546555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1689546555 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.3341753713
Short name T410
Test name
Test status
Simulation time 12998592921 ps
CPU time 152.24 seconds
Started Jul 14 05:36:33 PM PDT 24
Finished Jul 14 05:39:06 PM PDT 24
Peak memory 234588 kb
Host smart-b55b34e4-f731-4abd-ba4b-1452d735f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341753713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3341753713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.718454479
Short name T140
Test name
Test status
Simulation time 4100969522 ps
CPU time 347.01 seconds
Started Jul 14 05:36:33 PM PDT 24
Finished Jul 14 05:42:21 PM PDT 24
Peak memory 228232 kb
Host smart-ab7ff3dd-fb31-4f49-be7b-8eb10015c30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718454479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.718454479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.1706615844
Short name T384
Test name
Test status
Simulation time 21150766613 ps
CPU time 245.34 seconds
Started Jul 14 05:36:35 PM PDT 24
Finished Jul 14 05:40:41 PM PDT 24
Peak memory 242756 kb
Host smart-b942ac79-cc58-4bcd-b8f7-cb6aff58c892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706615844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1706615844 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.2180320194
Short name T667
Test name
Test status
Simulation time 4992623020 ps
CPU time 88.9 seconds
Started Jul 14 05:36:35 PM PDT 24
Finished Jul 14 05:38:04 PM PDT 24
Peak memory 239504 kb
Host smart-ff21adf9-1231-4bba-8550-222d269a80e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180320194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2180320194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.1454159470
Short name T478
Test name
Test status
Simulation time 1308159733 ps
CPU time 3.66 seconds
Started Jul 14 05:36:33 PM PDT 24
Finished Jul 14 05:36:37 PM PDT 24
Peak memory 207296 kb
Host smart-a814d927-b5c6-47dd-89e4-58a3facd04f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454159470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1454159470 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.4291944483
Short name T9
Test name
Test status
Simulation time 146759601 ps
CPU time 1.29 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 05:36:39 PM PDT 24
Peak memory 220160 kb
Host smart-79b5aaf8-b73c-444a-966c-ad3da7dc9dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291944483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.4291944483 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.987202653
Short name T567
Test name
Test status
Simulation time 17290359419 ps
CPU time 741.88 seconds
Started Jul 14 05:36:34 PM PDT 24
Finished Jul 14 05:48:57 PM PDT 24
Peak memory 298540 kb
Host smart-34ecd21a-1b0d-47df-b508-f61f8e84d5eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987202653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_an
d_output.987202653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.3052659618
Short name T15
Test name
Test status
Simulation time 14839463803 ps
CPU time 423.59 seconds
Started Jul 14 05:36:33 PM PDT 24
Finished Jul 14 05:43:37 PM PDT 24
Peak memory 251864 kb
Host smart-b599bf9a-9470-40db-a947-f52ae6227342
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052659618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3052659618 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.1113044277
Short name T775
Test name
Test status
Simulation time 635693481 ps
CPU time 13.7 seconds
Started Jul 14 05:36:34 PM PDT 24
Finished Jul 14 05:36:48 PM PDT 24
Peak memory 218272 kb
Host smart-eff7742e-d7e4-4729-aa12-9ba385a14118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113044277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1113044277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.65427112
Short name T622
Test name
Test status
Simulation time 14358691634 ps
CPU time 301.89 seconds
Started Jul 14 05:36:34 PM PDT 24
Finished Jul 14 05:41:36 PM PDT 24
Peak memory 265052 kb
Host smart-3477a1f6-6615-493f-bfe7-bca627181bc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=65427112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.65427112 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3744770683
Short name T400
Test name
Test status
Simulation time 68726819 ps
CPU time 4.05 seconds
Started Jul 14 05:36:34 PM PDT 24
Finished Jul 14 05:36:38 PM PDT 24
Peak memory 215596 kb
Host smart-48cd3b56-a673-462b-9ffc-756f031357bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744770683 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3744770683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.3293126698
Short name T471
Test name
Test status
Simulation time 509902210 ps
CPU time 5.1 seconds
Started Jul 14 05:36:34 PM PDT 24
Finished Jul 14 05:36:40 PM PDT 24
Peak memory 215628 kb
Host smart-e87d0ed4-946d-4299-920f-100cbaed3f2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293126698 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.3293126698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.27242565
Short name T252
Test name
Test status
Simulation time 943708953956 ps
CPU time 2101.84 seconds
Started Jul 14 05:36:32 PM PDT 24
Finished Jul 14 06:11:34 PM PDT 24
Peak memory 394488 kb
Host smart-863feb03-e8ad-4c1c-a863-e8924ea68c44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=27242565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.27242565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3364205102
Short name T226
Test name
Test status
Simulation time 95907140421 ps
CPU time 1919.58 seconds
Started Jul 14 05:36:31 PM PDT 24
Finished Jul 14 06:08:31 PM PDT 24
Peak memory 375820 kb
Host smart-5233a7f5-ebdf-4bfb-8b5c-db09de1023b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3364205102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3364205102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.2100262940
Short name T160
Test name
Test status
Simulation time 68552420592 ps
CPU time 1392.49 seconds
Started Jul 14 05:36:30 PM PDT 24
Finished Jul 14 05:59:43 PM PDT 24
Peak memory 328040 kb
Host smart-1c21ed51-b3b9-440f-b63c-409776a2df4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2100262940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2100262940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.2603756134
Short name T350
Test name
Test status
Simulation time 191603307843 ps
CPU time 912.54 seconds
Started Jul 14 05:36:31 PM PDT 24
Finished Jul 14 05:51:45 PM PDT 24
Peak memory 293832 kb
Host smart-bf6feddf-ab2f-4561-8534-f6ba6ce72a22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2603756134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2603756134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.2198465483
Short name T258
Test name
Test status
Simulation time 50257661210 ps
CPU time 3922.62 seconds
Started Jul 14 05:36:33 PM PDT 24
Finished Jul 14 06:41:56 PM PDT 24
Peak memory 639240 kb
Host smart-75ffa603-53f0-477f-a963-853e6537db41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2198465483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.2198465483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.2107695503
Short name T932
Test name
Test status
Simulation time 147872851415 ps
CPU time 3942.28 seconds
Started Jul 14 05:36:34 PM PDT 24
Finished Jul 14 06:42:17 PM PDT 24
Peak memory 541244 kb
Host smart-78a5cdd1-6a7b-4d16-8715-9b0753e33d5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2107695503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.2107695503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.1822952411
Short name T760
Test name
Test status
Simulation time 17882028 ps
CPU time 0.77 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 05:36:39 PM PDT 24
Peak memory 205304 kb
Host smart-75ca402b-ad02-4eb5-b816-36c8b3d41119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822952411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1822952411 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.2505016715
Short name T278
Test name
Test status
Simulation time 14894507901 ps
CPU time 93.52 seconds
Started Jul 14 05:36:36 PM PDT 24
Finished Jul 14 05:38:10 PM PDT 24
Peak memory 228588 kb
Host smart-a78e6cb1-5b80-4271-9125-3ac038447338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505016715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2505016715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.1981751537
Short name T892
Test name
Test status
Simulation time 2996923449 ps
CPU time 60.5 seconds
Started Jul 14 05:36:36 PM PDT 24
Finished Jul 14 05:37:38 PM PDT 24
Peak memory 219680 kb
Host smart-7aa5a618-221e-457d-bd35-1d46b775cb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981751537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1981751537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.1982540061
Short name T566
Test name
Test status
Simulation time 5097029661 ps
CPU time 87.8 seconds
Started Jul 14 05:36:39 PM PDT 24
Finished Jul 14 05:38:07 PM PDT 24
Peak memory 229208 kb
Host smart-b146fd50-417b-44e3-90aa-0a73e634a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982540061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1982540061 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_key_error.1054363048
Short name T66
Test name
Test status
Simulation time 1052608439 ps
CPU time 4.94 seconds
Started Jul 14 05:36:39 PM PDT 24
Finished Jul 14 05:36:45 PM PDT 24
Peak memory 207164 kb
Host smart-418c5dde-6151-415d-bd51-a9f6cfa34d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054363048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1054363048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.2114320164
Short name T33
Test name
Test status
Simulation time 159842010 ps
CPU time 1.25 seconds
Started Jul 14 05:36:38 PM PDT 24
Finished Jul 14 05:36:40 PM PDT 24
Peak memory 215520 kb
Host smart-ecdd0763-1a8a-4cc3-b7f1-341c1a0eb7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114320164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2114320164 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.984131633
Short name T497
Test name
Test status
Simulation time 119025105117 ps
CPU time 2573 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 06:19:31 PM PDT 24
Peak memory 448388 kb
Host smart-201d6be2-8634-4fe6-82ae-5e153e26efdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984131633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_an
d_output.984131633 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2119984394
Short name T645
Test name
Test status
Simulation time 3351043917 ps
CPU time 141.31 seconds
Started Jul 14 05:36:39 PM PDT 24
Finished Jul 14 05:39:01 PM PDT 24
Peak memory 231876 kb
Host smart-cd3667c2-6e39-43e2-bc4b-3cb58d844971
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119984394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2119984394 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.2536144384
Short name T477
Test name
Test status
Simulation time 247003715 ps
CPU time 1.84 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 05:36:40 PM PDT 24
Peak memory 218524 kb
Host smart-a5d61b1f-5fe8-4cde-8fce-5ef4a4af079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536144384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2536144384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.1572888031
Short name T304
Test name
Test status
Simulation time 159858986811 ps
CPU time 1139.41 seconds
Started Jul 14 05:36:40 PM PDT 24
Finished Jul 14 05:55:40 PM PDT 24
Peak memory 341824 kb
Host smart-a774d0cf-c7ed-440b-b432-00e81a3e73de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1572888031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1572888031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1411682314
Short name T868
Test name
Test status
Simulation time 495626728 ps
CPU time 5.04 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 05:36:43 PM PDT 24
Peak memory 215696 kb
Host smart-c7b82398-e50b-4d2e-a75a-046d28885e4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411682314 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1411682314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3385731478
Short name T811
Test name
Test status
Simulation time 349825383 ps
CPU time 4.73 seconds
Started Jul 14 05:36:40 PM PDT 24
Finished Jul 14 05:36:45 PM PDT 24
Peak memory 215520 kb
Host smart-9b5aaca0-6790-480f-860d-52178253732d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385731478 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3385731478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.3820379971
Short name T265
Test name
Test status
Simulation time 271683230804 ps
CPU time 1639.6 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 06:03:58 PM PDT 24
Peak memory 396084 kb
Host smart-89afdcfd-a2b2-4ede-8b54-891946cce97f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3820379971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.3820379971 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.3187941890
Short name T1051
Test name
Test status
Simulation time 74507104177 ps
CPU time 1571.54 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 377244 kb
Host smart-79bd3268-0d06-45af-803c-2f6c03a79767
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3187941890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.3187941890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.2488770658
Short name T371
Test name
Test status
Simulation time 27919461662 ps
CPU time 1160.26 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 05:55:58 PM PDT 24
Peak memory 341016 kb
Host smart-25ceec1a-8c89-4be9-9695-cfc00aed2467
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2488770658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.2488770658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.2472069500
Short name T245
Test name
Test status
Simulation time 135221214738 ps
CPU time 857.39 seconds
Started Jul 14 05:36:37 PM PDT 24
Finished Jul 14 05:50:55 PM PDT 24
Peak memory 293544 kb
Host smart-d13c235b-a07d-4fd3-b446-07f8f6fc3bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2472069500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.2472069500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1607841198
Short name T244
Test name
Test status
Simulation time 1016115951687 ps
CPU time 4546.89 seconds
Started Jul 14 05:36:36 PM PDT 24
Finished Jul 14 06:52:24 PM PDT 24
Peak memory 654516 kb
Host smart-ee1e13b6-d5c2-41ee-b6ce-86854d3d00f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1607841198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1607841198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.1969854737
Short name T77
Test name
Test status
Simulation time 225302892023 ps
CPU time 4102.3 seconds
Started Jul 14 05:36:40 PM PDT 24
Finished Jul 14 06:45:03 PM PDT 24
Peak memory 551060 kb
Host smart-bc5a7ecc-4956-4ea6-8d70-e72be882e9d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1969854737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1969854737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.2326867996
Short name T875
Test name
Test status
Simulation time 15766923 ps
CPU time 0.81 seconds
Started Jul 14 05:37:00 PM PDT 24
Finished Jul 14 05:37:01 PM PDT 24
Peak memory 205228 kb
Host smart-f43a1b36-15cc-45bb-adf3-35919727d3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326867996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2326867996 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_burst_write.74329569
Short name T1024
Test name
Test status
Simulation time 40401461055 ps
CPU time 722.44 seconds
Started Jul 14 05:36:43 PM PDT 24
Finished Jul 14 05:48:45 PM PDT 24
Peak memory 231396 kb
Host smart-f55aa318-d08b-40a1-9a7d-f5b7f6da61b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74329569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.74329569 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.1579066347
Short name T34
Test name
Test status
Simulation time 618185169 ps
CPU time 30.18 seconds
Started Jul 14 05:36:56 PM PDT 24
Finished Jul 14 05:37:27 PM PDT 24
Peak memory 223816 kb
Host smart-3db77808-44cd-449e-be3a-88b501996e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579066347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1579066347 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.2982657741
Short name T157
Test name
Test status
Simulation time 3985831068 ps
CPU time 309.99 seconds
Started Jul 14 05:37:00 PM PDT 24
Finished Jul 14 05:42:11 PM PDT 24
Peak memory 264832 kb
Host smart-33c190a1-592a-4397-925a-c6df6f11317d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982657741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2982657741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.2144206701
Short name T864
Test name
Test status
Simulation time 816056419 ps
CPU time 4.36 seconds
Started Jul 14 05:36:59 PM PDT 24
Finished Jul 14 05:37:04 PM PDT 24
Peak memory 207236 kb
Host smart-b9b4fc69-9f4e-400f-ab56-8d3e96e7dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144206701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2144206701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.1443221420
Short name T777
Test name
Test status
Simulation time 21912405 ps
CPU time 1.12 seconds
Started Jul 14 05:36:59 PM PDT 24
Finished Jul 14 05:37:00 PM PDT 24
Peak memory 215540 kb
Host smart-e2be65bc-8bd4-40c8-a393-93ef7434d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443221420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1443221420 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.2973113026
Short name T859
Test name
Test status
Simulation time 63210618646 ps
CPU time 2058.98 seconds
Started Jul 14 05:36:44 PM PDT 24
Finished Jul 14 06:11:03 PM PDT 24
Peak memory 446168 kb
Host smart-9cb1bb42-ed55-4841-a9bd-4220d057d5c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973113026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.2973113026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.1494231450
Short name T377
Test name
Test status
Simulation time 6298958752 ps
CPU time 87.22 seconds
Started Jul 14 05:36:43 PM PDT 24
Finished Jul 14 05:38:11 PM PDT 24
Peak memory 225388 kb
Host smart-68da9a74-5c43-4bc4-808e-d2f689cc9d17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494231450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.1494231450 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.4018895606
Short name T674
Test name
Test status
Simulation time 545759269 ps
CPU time 28.2 seconds
Started Jul 14 05:36:39 PM PDT 24
Finished Jul 14 05:37:09 PM PDT 24
Peak memory 223800 kb
Host smart-00180895-b27a-48e5-9314-c965e4ec716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018895606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.4018895606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.3130613989
Short name T1029
Test name
Test status
Simulation time 336578829 ps
CPU time 4.36 seconds
Started Jul 14 05:36:51 PM PDT 24
Finished Jul 14 05:36:55 PM PDT 24
Peak memory 215644 kb
Host smart-7e43bb18-9e47-4ad1-8e2e-52710bbda5c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130613989 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.3130613989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3008040495
Short name T78
Test name
Test status
Simulation time 1625118123 ps
CPU time 5.01 seconds
Started Jul 14 05:36:56 PM PDT 24
Finished Jul 14 05:37:01 PM PDT 24
Peak memory 215524 kb
Host smart-d80e6d3e-41d4-4bda-ae1f-790d7b0be085
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008040495 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3008040495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.117367316
Short name T189
Test name
Test status
Simulation time 342977386940 ps
CPU time 1829.71 seconds
Started Jul 14 05:36:48 PM PDT 24
Finished Jul 14 06:07:19 PM PDT 24
Peak memory 375892 kb
Host smart-0ffb03ff-95a5-4df1-a48c-c80077f0fe6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=117367316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.117367316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.1683063323
Short name T14
Test name
Test status
Simulation time 29923663777 ps
CPU time 1437.2 seconds
Started Jul 14 05:36:48 PM PDT 24
Finished Jul 14 06:00:46 PM PDT 24
Peak memory 371784 kb
Host smart-c0f1e61b-918f-47d4-95d1-d410022bdf75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1683063323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.1683063323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.2322424929
Short name T75
Test name
Test status
Simulation time 168737461730 ps
CPU time 1261.26 seconds
Started Jul 14 05:36:48 PM PDT 24
Finished Jul 14 05:57:50 PM PDT 24
Peak memory 326544 kb
Host smart-1aabec1c-b867-42b6-b6a8-ccaf97d3acf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2322424929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2322424929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.491980715
Short name T473
Test name
Test status
Simulation time 9775635926 ps
CPU time 781.69 seconds
Started Jul 14 05:36:50 PM PDT 24
Finished Jul 14 05:49:52 PM PDT 24
Peak memory 296672 kb
Host smart-1a71c608-a8cc-4ec7-9048-820f6025b7f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=491980715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.491980715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.3390205363
Short name T112
Test name
Test status
Simulation time 212121850942 ps
CPU time 3998.24 seconds
Started Jul 14 05:36:50 PM PDT 24
Finished Jul 14 06:43:29 PM PDT 24
Peak memory 651752 kb
Host smart-8afccbe2-5ac6-478f-9537-e227458bdc65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3390205363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3390205363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.979970293
Short name T307
Test name
Test status
Simulation time 45239127102 ps
CPU time 3229.24 seconds
Started Jul 14 05:36:49 PM PDT 24
Finished Jul 14 06:30:39 PM PDT 24
Peak memory 563988 kb
Host smart-337d97c0-ebd0-4f96-8613-1f39e2fbd0c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=979970293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.979970293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.2423369098
Short name T821
Test name
Test status
Simulation time 43343011 ps
CPU time 0.78 seconds
Started Jul 14 05:37:16 PM PDT 24
Finished Jul 14 05:37:17 PM PDT 24
Peak memory 205292 kb
Host smart-44b882fb-fbe2-4724-a37b-46eb1136201c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423369098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2423369098 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.4211583252
Short name T729
Test name
Test status
Simulation time 4478201354 ps
CPU time 48.12 seconds
Started Jul 14 05:37:11 PM PDT 24
Finished Jul 14 05:38:00 PM PDT 24
Peak memory 224684 kb
Host smart-f991187f-2f30-44d9-92e1-ec8e0aea8d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211583252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.4211583252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.4015891766
Short name T536
Test name
Test status
Simulation time 12327675647 ps
CPU time 183.64 seconds
Started Jul 14 05:37:04 PM PDT 24
Finished Jul 14 05:40:08 PM PDT 24
Peak memory 223908 kb
Host smart-594b763f-207e-42e3-908f-86263e82350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015891766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.4015891766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.135713858
Short name T482
Test name
Test status
Simulation time 77183688055 ps
CPU time 269.44 seconds
Started Jul 14 05:37:16 PM PDT 24
Finished Jul 14 05:41:46 PM PDT 24
Peak memory 243216 kb
Host smart-db2681ef-1968-4867-8168-ae2085b72e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135713858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.135713858 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.1758651480
Short name T599
Test name
Test status
Simulation time 2124691762 ps
CPU time 88.1 seconds
Started Jul 14 05:37:16 PM PDT 24
Finished Jul 14 05:38:45 PM PDT 24
Peak memory 236972 kb
Host smart-80cc6f44-8a6a-4855-86e8-1c2cf35fe629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758651480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1758651480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.1086112999
Short name T464
Test name
Test status
Simulation time 1112303897 ps
CPU time 6.53 seconds
Started Jul 14 05:37:19 PM PDT 24
Finished Jul 14 05:37:26 PM PDT 24
Peak memory 215540 kb
Host smart-10df1cdc-78ed-4b2f-a799-55dab795930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086112999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1086112999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.358279102
Short name T794
Test name
Test status
Simulation time 122600857 ps
CPU time 1.26 seconds
Started Jul 14 05:37:16 PM PDT 24
Finished Jul 14 05:37:19 PM PDT 24
Peak memory 215512 kb
Host smart-74028267-cf19-4847-8ec6-659f4c966d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358279102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.358279102 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.1277404792
Short name T273
Test name
Test status
Simulation time 53208427829 ps
CPU time 747.42 seconds
Started Jul 14 05:37:00 PM PDT 24
Finished Jul 14 05:49:28 PM PDT 24
Peak memory 291168 kb
Host smart-66b61a92-2c47-4869-b3f7-2021a9a33c85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277404792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.1277404792 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.2172672828
Short name T866
Test name
Test status
Simulation time 16676550177 ps
CPU time 360.37 seconds
Started Jul 14 05:37:07 PM PDT 24
Finished Jul 14 05:43:08 PM PDT 24
Peak memory 249624 kb
Host smart-d703e571-c6a4-4d9f-8239-b6ff12e88787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172672828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2172672828 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.1803774635
Short name T633
Test name
Test status
Simulation time 1326063323 ps
CPU time 5.73 seconds
Started Jul 14 05:36:59 PM PDT 24
Finished Jul 14 05:37:05 PM PDT 24
Peak memory 219248 kb
Host smart-d271b8c5-1d68-4714-96df-a7f4c56467db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803774635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1803774635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.1626442734
Short name T683
Test name
Test status
Simulation time 109276550799 ps
CPU time 595.4 seconds
Started Jul 14 05:37:16 PM PDT 24
Finished Jul 14 05:47:13 PM PDT 24
Peak memory 298916 kb
Host smart-869ebeee-f00e-4a71-b697-fbbe724f136d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1626442734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1626442734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.2371840337
Short name T89
Test name
Test status
Simulation time 77791730 ps
CPU time 3.8 seconds
Started Jul 14 05:37:12 PM PDT 24
Finished Jul 14 05:37:16 PM PDT 24
Peak memory 215540 kb
Host smart-6d4d1647-f745-475a-afb0-91dcc8d42993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371840337 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.2371840337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.3296589328
Short name T951
Test name
Test status
Simulation time 251187976 ps
CPU time 4.87 seconds
Started Jul 14 05:37:10 PM PDT 24
Finished Jul 14 05:37:15 PM PDT 24
Peak memory 215588 kb
Host smart-198437dd-e6e4-4aca-b413-722f9a09e22d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296589328 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.3296589328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.4175212665
Short name T938
Test name
Test status
Simulation time 75074762230 ps
CPU time 1937.39 seconds
Started Jul 14 05:37:05 PM PDT 24
Finished Jul 14 06:09:23 PM PDT 24
Peak memory 403556 kb
Host smart-b607e53b-c3ef-4f33-b26b-0e4b5c4e2d31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4175212665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.4175212665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.3258194165
Short name T234
Test name
Test status
Simulation time 76308395691 ps
CPU time 1443.99 seconds
Started Jul 14 05:37:05 PM PDT 24
Finished Jul 14 06:01:09 PM PDT 24
Peak memory 370476 kb
Host smart-79bc989c-2e49-472e-a9ad-7dc486f34041
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3258194165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.3258194165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.2271484355
Short name T561
Test name
Test status
Simulation time 94936293317 ps
CPU time 1359.88 seconds
Started Jul 14 05:37:12 PM PDT 24
Finished Jul 14 05:59:53 PM PDT 24
Peak memory 332808 kb
Host smart-a3ecae05-5c76-417b-ae47-53bcc91c5c18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2271484355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.2271484355 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.657197286
Short name T550
Test name
Test status
Simulation time 50679044659 ps
CPU time 979.93 seconds
Started Jul 14 05:37:12 PM PDT 24
Finished Jul 14 05:53:32 PM PDT 24
Peak memory 294164 kb
Host smart-528b44bd-3c91-4660-a583-3a886fe7b1e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=657197286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.657197286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3847620437
Short name T1023
Test name
Test status
Simulation time 312887377473 ps
CPU time 5251.14 seconds
Started Jul 14 05:37:10 PM PDT 24
Finished Jul 14 07:04:42 PM PDT 24
Peak memory 662828 kb
Host smart-141fc6fe-bfc8-4a46-8561-0a693bf82b1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3847620437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3847620437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1753774802
Short name T994
Test name
Test status
Simulation time 58461176366 ps
CPU time 3355.53 seconds
Started Jul 14 05:37:11 PM PDT 24
Finished Jul 14 06:33:07 PM PDT 24
Peak memory 561996 kb
Host smart-66ddd40d-5582-42f1-80bd-d74a03f46c27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1753774802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1753774802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.3891744128
Short name T707
Test name
Test status
Simulation time 20251451 ps
CPU time 0.81 seconds
Started Jul 14 05:37:30 PM PDT 24
Finished Jul 14 05:37:32 PM PDT 24
Peak memory 205244 kb
Host smart-0c3a1e34-a5c3-45fb-b494-650761b4880b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891744128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3891744128 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.2026748095
Short name T413
Test name
Test status
Simulation time 4305113599 ps
CPU time 60.61 seconds
Started Jul 14 05:37:24 PM PDT 24
Finished Jul 14 05:38:25 PM PDT 24
Peak memory 224360 kb
Host smart-25dc999d-6a6b-4c45-9456-8fa91ab8d3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026748095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2026748095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.3583457942
Short name T995
Test name
Test status
Simulation time 34264945457 ps
CPU time 552.55 seconds
Started Jul 14 05:37:18 PM PDT 24
Finished Jul 14 05:46:31 PM PDT 24
Peak memory 238824 kb
Host smart-2cd8f7ab-e81a-4f6c-b73f-6593cf4ddbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583457942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.3583457942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.3538210898
Short name T218
Test name
Test status
Simulation time 14107114824 ps
CPU time 137.13 seconds
Started Jul 14 05:37:30 PM PDT 24
Finished Jul 14 05:39:47 PM PDT 24
Peak memory 235172 kb
Host smart-1a81f28e-8b86-418b-b5c7-39f158dad272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538210898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3538210898 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.1046910184
Short name T238
Test name
Test status
Simulation time 438642505 ps
CPU time 32.61 seconds
Started Jul 14 05:37:28 PM PDT 24
Finished Jul 14 05:38:01 PM PDT 24
Peak memory 232044 kb
Host smart-57f93994-5048-46ff-8127-a0de5c024fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046910184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1046910184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.3304470696
Short name T617
Test name
Test status
Simulation time 1590148212 ps
CPU time 7.08 seconds
Started Jul 14 05:37:30 PM PDT 24
Finished Jul 14 05:37:38 PM PDT 24
Peak memory 207416 kb
Host smart-6fe1a70a-b747-4a28-8dfc-859b85273439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304470696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3304470696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.1629846939
Short name T542
Test name
Test status
Simulation time 36231893 ps
CPU time 1.21 seconds
Started Jul 14 05:37:31 PM PDT 24
Finished Jul 14 05:37:33 PM PDT 24
Peak memory 215532 kb
Host smart-75e62938-e255-4cfa-8211-33185d556e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629846939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1629846939 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.534822697
Short name T178
Test name
Test status
Simulation time 534903057714 ps
CPU time 2678.49 seconds
Started Jul 14 05:37:15 PM PDT 24
Finished Jul 14 06:21:54 PM PDT 24
Peak memory 479304 kb
Host smart-6067dbe9-97cc-4ac6-8763-151f0910fdd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534822697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an
d_output.534822697 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.3742276249
Short name T250
Test name
Test status
Simulation time 9818274477 ps
CPU time 169.63 seconds
Started Jul 14 05:37:17 PM PDT 24
Finished Jul 14 05:40:08 PM PDT 24
Peak memory 240128 kb
Host smart-5ca283db-901e-4a01-8cd3-17d580ec644b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742276249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3742276249 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.4133184342
Short name T809
Test name
Test status
Simulation time 8207171677 ps
CPU time 11.03 seconds
Started Jul 14 05:37:17 PM PDT 24
Finished Jul 14 05:37:29 PM PDT 24
Peak memory 219840 kb
Host smart-49601f98-2e81-4142-b9eb-d4d8fa0ad2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133184342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.4133184342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.1673899131
Short name T757
Test name
Test status
Simulation time 11768799616 ps
CPU time 421.13 seconds
Started Jul 14 05:37:31 PM PDT 24
Finished Jul 14 05:44:33 PM PDT 24
Peak memory 291168 kb
Host smart-22c7e0ec-f610-4a67-80d6-14aac022eac1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1673899131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.1673899131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.220851156
Short name T485
Test name
Test status
Simulation time 253677582 ps
CPU time 4 seconds
Started Jul 14 05:37:23 PM PDT 24
Finished Jul 14 05:37:27 PM PDT 24
Peak memory 208620 kb
Host smart-a7dfaf9e-af63-48cf-9f9c-8cb042bb0f8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220851156 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.kmac_test_vectors_kmac.220851156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.838698222
Short name T266
Test name
Test status
Simulation time 821212568 ps
CPU time 4.87 seconds
Started Jul 14 05:37:26 PM PDT 24
Finished Jul 14 05:37:32 PM PDT 24
Peak memory 215616 kb
Host smart-4b8d3d5b-27ab-4209-a941-d3ccec8dec41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838698222 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.838698222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.3802533691
Short name T547
Test name
Test status
Simulation time 63874593982 ps
CPU time 1558.66 seconds
Started Jul 14 05:37:17 PM PDT 24
Finished Jul 14 06:03:17 PM PDT 24
Peak memory 378896 kb
Host smart-919614b6-e8c2-466d-926d-c1256bbf2af5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3802533691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3802533691 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.331516476
Short name T488
Test name
Test status
Simulation time 1576645023385 ps
CPU time 2258.66 seconds
Started Jul 14 05:37:18 PM PDT 24
Finished Jul 14 06:14:57 PM PDT 24
Peak memory 371996 kb
Host smart-db0e81a9-3d58-4172-ac71-bf29fbe54ca1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=331516476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.331516476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.2083723
Short name T267
Test name
Test status
Simulation time 275168984913 ps
CPU time 1393.64 seconds
Started Jul 14 05:37:23 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 329536 kb
Host smart-7a8106c0-195f-4f4d-b894-d124cf3022b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2083723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.2083723 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.2751375616
Short name T359
Test name
Test status
Simulation time 199588562611 ps
CPU time 1047.32 seconds
Started Jul 14 05:37:27 PM PDT 24
Finished Jul 14 05:54:55 PM PDT 24
Peak memory 298336 kb
Host smart-bb4499ea-572d-4a5d-bf3a-3d43c4c3c3a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2751375616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.2751375616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.295750269
Short name T346
Test name
Test status
Simulation time 50381215974 ps
CPU time 4100.15 seconds
Started Jul 14 05:37:25 PM PDT 24
Finished Jul 14 06:45:46 PM PDT 24
Peak memory 629808 kb
Host smart-96ca3950-3625-4447-a22a-0b50486b7fd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=295750269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.295750269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.296068600
Short name T257
Test name
Test status
Simulation time 540391936483 ps
CPU time 4163.41 seconds
Started Jul 14 05:37:27 PM PDT 24
Finished Jul 14 06:46:52 PM PDT 24
Peak memory 563756 kb
Host smart-b4995625-0b7c-486f-b292-e4ecdd94e7e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=296068600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.296068600 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.2321113773
Short name T48
Test name
Test status
Simulation time 64694563 ps
CPU time 0.86 seconds
Started Jul 14 05:37:52 PM PDT 24
Finished Jul 14 05:37:53 PM PDT 24
Peak memory 205284 kb
Host smart-f4048707-bdd7-419d-a73a-214ae0c929e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321113773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2321113773 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.2829366535
Short name T906
Test name
Test status
Simulation time 18977288963 ps
CPU time 346.53 seconds
Started Jul 14 05:37:42 PM PDT 24
Finished Jul 14 05:43:29 PM PDT 24
Peak memory 247804 kb
Host smart-bac9328f-5dd4-4976-b500-0bdaa320d32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829366535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2829366535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.2230941013
Short name T989
Test name
Test status
Simulation time 24200065422 ps
CPU time 834.84 seconds
Started Jul 14 05:37:36 PM PDT 24
Finished Jul 14 05:51:31 PM PDT 24
Peak memory 232220 kb
Host smart-d2dd72de-e43c-4999-8f63-c67e94f432fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230941013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2230941013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.3976343357
Short name T1054
Test name
Test status
Simulation time 11313464426 ps
CPU time 179.72 seconds
Started Jul 14 05:37:41 PM PDT 24
Finished Jul 14 05:40:41 PM PDT 24
Peak memory 238448 kb
Host smart-7293378c-f3e7-433b-8f33-cc205d300094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976343357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3976343357 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.2247441103
Short name T787
Test name
Test status
Simulation time 8249850469 ps
CPU time 68.89 seconds
Started Jul 14 05:37:43 PM PDT 24
Finished Jul 14 05:38:52 PM PDT 24
Peak memory 240224 kb
Host smart-9274c0e6-3a67-42a6-958f-63d7ccabf2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247441103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2247441103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.742609308
Short name T62
Test name
Test status
Simulation time 427872120 ps
CPU time 2.84 seconds
Started Jul 14 05:37:50 PM PDT 24
Finished Jul 14 05:37:53 PM PDT 24
Peak memory 207144 kb
Host smart-70727d56-1981-45b9-951b-ec39034c38b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742609308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.742609308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.2515809083
Short name T59
Test name
Test status
Simulation time 53907839 ps
CPU time 1.15 seconds
Started Jul 14 05:37:49 PM PDT 24
Finished Jul 14 05:37:50 PM PDT 24
Peak memory 215500 kb
Host smart-10f39b92-001b-4acf-a05e-76401d191c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515809083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2515809083 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.1431333693
Short name T324
Test name
Test status
Simulation time 100377422459 ps
CPU time 2223.63 seconds
Started Jul 14 05:37:31 PM PDT 24
Finished Jul 14 06:14:36 PM PDT 24
Peak memory 455312 kb
Host smart-a32fe7b7-8948-464a-af82-0592f62df514
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431333693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.1431333693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.3323842302
Short name T1041
Test name
Test status
Simulation time 9135665033 ps
CPU time 188.24 seconds
Started Jul 14 05:37:31 PM PDT 24
Finished Jul 14 05:40:40 PM PDT 24
Peak memory 237308 kb
Host smart-c87c46fd-7285-494c-833d-774697fcb268
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323842302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3323842302 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3281410580
Short name T1045
Test name
Test status
Simulation time 157684676 ps
CPU time 3.97 seconds
Started Jul 14 05:37:32 PM PDT 24
Finished Jul 14 05:37:36 PM PDT 24
Peak memory 219788 kb
Host smart-264e689d-f75d-48a4-964f-e5ca8b8bbb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281410580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3281410580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.3347540509
Short name T54
Test name
Test status
Simulation time 31254568556 ps
CPU time 648.64 seconds
Started Jul 14 05:37:51 PM PDT 24
Finished Jul 14 05:48:41 PM PDT 24
Peak memory 304364 kb
Host smart-4606c4ed-1b3e-47a9-8ba9-c63651506760
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3347540509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3347540509 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.1646335830
Short name T628
Test name
Test status
Simulation time 64435930 ps
CPU time 4.1 seconds
Started Jul 14 05:37:41 PM PDT 24
Finished Jul 14 05:37:47 PM PDT 24
Peak memory 215724 kb
Host smart-34823fb3-d696-448b-84b7-3fca8eeb101c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646335830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.1646335830 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1670863065
Short name T237
Test name
Test status
Simulation time 240840777 ps
CPU time 5.29 seconds
Started Jul 14 05:37:42 PM PDT 24
Finished Jul 14 05:37:48 PM PDT 24
Peak memory 215576 kb
Host smart-0c8e0a86-4d05-41c6-9b02-e7e7858051e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670863065 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1670863065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.684876916
Short name T243
Test name
Test status
Simulation time 19880192332 ps
CPU time 1613.28 seconds
Started Jul 14 05:37:37 PM PDT 24
Finished Jul 14 06:04:31 PM PDT 24
Peak memory 396936 kb
Host smart-c6ecddd8-23b1-4f0b-881d-3f33b14152d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=684876916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.684876916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.4198387866
Short name T533
Test name
Test status
Simulation time 369516622597 ps
CPU time 1706.67 seconds
Started Jul 14 05:37:38 PM PDT 24
Finished Jul 14 06:06:05 PM PDT 24
Peak memory 377288 kb
Host smart-072cbede-3a7b-4241-b8f3-1a5764d13a21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4198387866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.4198387866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.777560885
Short name T1006
Test name
Test status
Simulation time 48295314256 ps
CPU time 1195.41 seconds
Started Jul 14 05:37:37 PM PDT 24
Finished Jul 14 05:57:33 PM PDT 24
Peak memory 331088 kb
Host smart-53086f87-3d59-4f38-9a68-c90880c5c383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=777560885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.777560885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.598755706
Short name T675
Test name
Test status
Simulation time 226305077672 ps
CPU time 889.98 seconds
Started Jul 14 05:37:40 PM PDT 24
Finished Jul 14 05:52:31 PM PDT 24
Peak memory 289912 kb
Host smart-95c84d3d-2d34-443a-b251-9625de4f2737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=598755706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.598755706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.277455586
Short name T987
Test name
Test status
Simulation time 685103409368 ps
CPU time 4503.85 seconds
Started Jul 14 05:37:42 PM PDT 24
Finished Jul 14 06:52:47 PM PDT 24
Peak memory 645984 kb
Host smart-facda455-3b9f-46c0-a61c-34b485afaa5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=277455586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.277455586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.2173947857
Short name T962
Test name
Test status
Simulation time 386428100180 ps
CPU time 3947.79 seconds
Started Jul 14 05:37:42 PM PDT 24
Finished Jul 14 06:43:31 PM PDT 24
Peak memory 550792 kb
Host smart-0c2077d0-0952-48bf-a66e-a1e692b133d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2173947857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.2173947857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.1790711096
Short name T771
Test name
Test status
Simulation time 20098213 ps
CPU time 0.84 seconds
Started Jul 14 05:38:10 PM PDT 24
Finished Jul 14 05:38:12 PM PDT 24
Peak memory 205268 kb
Host smart-66a53b81-a35e-4908-aeaf-87f334bb5c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790711096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1790711096 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.4028736265
Short name T279
Test name
Test status
Simulation time 26008216744 ps
CPU time 141.57 seconds
Started Jul 14 05:38:09 PM PDT 24
Finished Jul 14 05:40:31 PM PDT 24
Peak memory 233196 kb
Host smart-374b364e-91ca-4fc6-9f9a-1e4ca4e773df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028736265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.4028736265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.3237178634
Short name T392
Test name
Test status
Simulation time 96105843424 ps
CPU time 602.48 seconds
Started Jul 14 05:37:59 PM PDT 24
Finished Jul 14 05:48:02 PM PDT 24
Peak memory 230128 kb
Host smart-9e73d73c-0e66-4dfc-8f25-bb2aa6fa3a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237178634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3237178634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.2140573202
Short name T206
Test name
Test status
Simulation time 13815546168 ps
CPU time 130.03 seconds
Started Jul 14 05:38:09 PM PDT 24
Finished Jul 14 05:40:19 PM PDT 24
Peak memory 231676 kb
Host smart-b48b824f-d716-4d6a-9f46-9f4d9883485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140573202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2140573202 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3200796414
Short name T27
Test name
Test status
Simulation time 20395726419 ps
CPU time 108.94 seconds
Started Jul 14 05:38:10 PM PDT 24
Finished Jul 14 05:40:00 PM PDT 24
Peak memory 240260 kb
Host smart-30f70896-2757-47af-ae82-417fa12a5486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200796414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3200796414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.935826617
Short name T416
Test name
Test status
Simulation time 2191137270 ps
CPU time 3.51 seconds
Started Jul 14 05:38:11 PM PDT 24
Finished Jul 14 05:38:15 PM PDT 24
Peak memory 207292 kb
Host smart-ea2d423a-1fbf-476f-b891-3e636172dfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935826617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.935826617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1112359613
Short name T722
Test name
Test status
Simulation time 41910401 ps
CPU time 1.36 seconds
Started Jul 14 05:38:11 PM PDT 24
Finished Jul 14 05:38:12 PM PDT 24
Peak memory 215636 kb
Host smart-f73c9144-3248-4f5c-ab91-bd11d2625731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112359613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1112359613 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.497853700
Short name T429
Test name
Test status
Simulation time 30035783759 ps
CPU time 874.51 seconds
Started Jul 14 05:37:56 PM PDT 24
Finished Jul 14 05:52:31 PM PDT 24
Peak memory 303640 kb
Host smart-cad0a733-7392-4e30-9407-489f7c2b9331
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497853700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an
d_output.497853700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1155007232
Short name T316
Test name
Test status
Simulation time 151687379 ps
CPU time 4.6 seconds
Started Jul 14 05:37:59 PM PDT 24
Finished Jul 14 05:38:04 PM PDT 24
Peak memory 218788 kb
Host smart-f6b349c5-70e9-4cef-a444-24ab34df38c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155007232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1155007232 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3988597145
Short name T405
Test name
Test status
Simulation time 11835785330 ps
CPU time 53.33 seconds
Started Jul 14 05:37:53 PM PDT 24
Finished Jul 14 05:38:46 PM PDT 24
Peak memory 219472 kb
Host smart-8d2b375f-421d-41ae-a658-1ffd0b75db15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988597145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3988597145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.3746387920
Short name T943
Test name
Test status
Simulation time 82055290441 ps
CPU time 973.61 seconds
Started Jul 14 05:38:09 PM PDT 24
Finished Jul 14 05:54:23 PM PDT 24
Peak memory 322164 kb
Host smart-4905e710-487b-4070-824c-b18c70aba989
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3746387920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3746387920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.235533829
Short name T483
Test name
Test status
Simulation time 255359163 ps
CPU time 5.21 seconds
Started Jul 14 05:38:07 PM PDT 24
Finished Jul 14 05:38:13 PM PDT 24
Peak memory 215512 kb
Host smart-c87bb03b-0fec-4ae0-964b-b04defa666d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235533829 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.kmac_test_vectors_kmac.235533829 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.1019000840
Short name T401
Test name
Test status
Simulation time 907474209 ps
CPU time 4.5 seconds
Started Jul 14 05:38:06 PM PDT 24
Finished Jul 14 05:38:11 PM PDT 24
Peak memory 215580 kb
Host smart-b481033e-e639-477a-8f0b-33c57d23dd63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019000840 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.1019000840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.613819048
Short name T908
Test name
Test status
Simulation time 74570285749 ps
CPU time 1584.26 seconds
Started Jul 14 05:37:58 PM PDT 24
Finished Jul 14 06:04:23 PM PDT 24
Peak memory 388332 kb
Host smart-513aa325-f2e4-485f-a6aa-e142a39bbed3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=613819048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.613819048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.3726666256
Short name T1038
Test name
Test status
Simulation time 197188275426 ps
CPU time 1511.4 seconds
Started Jul 14 05:37:59 PM PDT 24
Finished Jul 14 06:03:11 PM PDT 24
Peak memory 374508 kb
Host smart-80cffd34-fe10-4a61-b6f1-ab7f9c4d8648
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3726666256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3726666256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.1375294227
Short name T523
Test name
Test status
Simulation time 14282569535 ps
CPU time 1154.75 seconds
Started Jul 14 05:38:07 PM PDT 24
Finished Jul 14 05:57:22 PM PDT 24
Peak memory 336552 kb
Host smart-985d12c5-5f56-48b5-9f75-65637f53f70b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1375294227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1375294227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.3377844450
Short name T339
Test name
Test status
Simulation time 85031339271 ps
CPU time 786.13 seconds
Started Jul 14 05:38:06 PM PDT 24
Finished Jul 14 05:51:12 PM PDT 24
Peak memory 291972 kb
Host smart-5b6b49d1-d1e9-4a63-b168-545d11677bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3377844450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.3377844450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.1706468114
Short name T949
Test name
Test status
Simulation time 51953018348 ps
CPU time 3958.37 seconds
Started Jul 14 05:38:05 PM PDT 24
Finished Jul 14 06:44:05 PM PDT 24
Peak memory 650220 kb
Host smart-29f32883-aab9-4110-8dab-84fdca6d78f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1706468114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1706468114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.2423085988
Short name T813
Test name
Test status
Simulation time 53281447956 ps
CPU time 3664.99 seconds
Started Jul 14 05:38:06 PM PDT 24
Finished Jul 14 06:39:12 PM PDT 24
Peak memory 559856 kb
Host smart-1dc82cdc-d214-49ee-90fa-2fa1a4865050
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2423085988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.2423085988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.731824441
Short name T884
Test name
Test status
Simulation time 50457119 ps
CPU time 0.8 seconds
Started Jul 14 05:38:26 PM PDT 24
Finished Jul 14 05:38:27 PM PDT 24
Peak memory 205268 kb
Host smart-79036698-03b3-49e1-b640-f6edd6104a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731824441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.731824441 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.2323580179
Short name T686
Test name
Test status
Simulation time 16458391447 ps
CPU time 160.72 seconds
Started Jul 14 05:38:21 PM PDT 24
Finished Jul 14 05:41:03 PM PDT 24
Peak memory 235764 kb
Host smart-a1ec09fb-b88b-4f66-8556-17d3b24b2866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323580179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2323580179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.889468219
Short name T562
Test name
Test status
Simulation time 83776212189 ps
CPU time 322.29 seconds
Started Jul 14 05:38:20 PM PDT 24
Finished Jul 14 05:43:42 PM PDT 24
Peak memory 248832 kb
Host smart-2969f221-21f2-4f99-accb-71118ddea179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889468219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.889468219 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.345094581
Short name T43
Test name
Test status
Simulation time 11777892882 ps
CPU time 106.57 seconds
Started Jul 14 05:38:25 PM PDT 24
Finished Jul 14 05:40:12 PM PDT 24
Peak memory 240260 kb
Host smart-1ac0c7b4-6512-4501-a528-8aa24a9ffedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345094581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.345094581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2903533433
Short name T915
Test name
Test status
Simulation time 164599259 ps
CPU time 1.22 seconds
Started Jul 14 05:38:27 PM PDT 24
Finished Jul 14 05:38:28 PM PDT 24
Peak memory 215540 kb
Host smart-0c3b8406-ce6f-497e-ba77-8870d06231e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903533433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2903533433 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.2345533311
Short name T436
Test name
Test status
Simulation time 389369604 ps
CPU time 31.33 seconds
Started Jul 14 05:38:10 PM PDT 24
Finished Jul 14 05:38:42 PM PDT 24
Peak memory 222476 kb
Host smart-0ebc9cbe-56b6-4f2f-a81e-a27456ff88e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345533311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.2345533311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.3456998479
Short name T381
Test name
Test status
Simulation time 13633155559 ps
CPU time 324.04 seconds
Started Jul 14 05:38:11 PM PDT 24
Finished Jul 14 05:43:36 PM PDT 24
Peak memory 245400 kb
Host smart-e30b775d-0821-482f-90c7-888a925f8f54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456998479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3456998479 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.4238423848
Short name T897
Test name
Test status
Simulation time 1055247155 ps
CPU time 10.48 seconds
Started Jul 14 05:38:12 PM PDT 24
Finished Jul 14 05:38:22 PM PDT 24
Peak memory 218656 kb
Host smart-5ff1e3cd-1f7c-4181-bd45-815a3e890fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238423848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.4238423848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.3533251709
Short name T1035
Test name
Test status
Simulation time 10980159577 ps
CPU time 524.76 seconds
Started Jul 14 05:38:27 PM PDT 24
Finished Jul 14 05:47:12 PM PDT 24
Peak memory 314216 kb
Host smart-2a4013e6-4485-4a18-b6e7-3c807c0d8444
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3533251709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3533251709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.460427393
Short name T393
Test name
Test status
Simulation time 170142620 ps
CPU time 4.65 seconds
Started Jul 14 05:38:21 PM PDT 24
Finished Jul 14 05:38:26 PM PDT 24
Peak memory 215684 kb
Host smart-6ae73ee6-f1f4-4d4e-aba1-c231171a0625
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460427393 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.kmac_test_vectors_kmac.460427393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.1198217784
Short name T774
Test name
Test status
Simulation time 126080970 ps
CPU time 4.05 seconds
Started Jul 14 05:38:21 PM PDT 24
Finished Jul 14 05:38:25 PM PDT 24
Peak memory 215592 kb
Host smart-852aa5a7-d72d-4069-8665-8728c4d6e902
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198217784 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.1198217784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.3707376974
Short name T922
Test name
Test status
Simulation time 190871870440 ps
CPU time 1832.66 seconds
Started Jul 14 05:38:20 PM PDT 24
Finished Jul 14 06:08:53 PM PDT 24
Peak memory 391836 kb
Host smart-d5deccae-6850-483f-8049-ee7a023b0f14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3707376974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3707376974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.1813833597
Short name T847
Test name
Test status
Simulation time 63649161310 ps
CPU time 1799.94 seconds
Started Jul 14 05:38:17 PM PDT 24
Finished Jul 14 06:08:17 PM PDT 24
Peak memory 373948 kb
Host smart-414f4a3d-0eff-47a7-8d9f-190be9e6291d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1813833597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.1813833597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.616006633
Short name T343
Test name
Test status
Simulation time 139997337899 ps
CPU time 1449.05 seconds
Started Jul 14 05:38:21 PM PDT 24
Finished Jul 14 06:02:30 PM PDT 24
Peak memory 333712 kb
Host smart-5beb5957-56be-4dfa-8707-037f832a0c9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=616006633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.616006633 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.1204426173
Short name T925
Test name
Test status
Simulation time 205694917551 ps
CPU time 1077.66 seconds
Started Jul 14 05:38:15 PM PDT 24
Finished Jul 14 05:56:14 PM PDT 24
Peak memory 297016 kb
Host smart-25cd5b97-65a6-42cf-ba0f-3174ad0bfe55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1204426173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.1204426173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.3659456522
Short name T1022
Test name
Test status
Simulation time 177468748394 ps
CPU time 4517.89 seconds
Started Jul 14 05:38:21 PM PDT 24
Finished Jul 14 06:53:40 PM PDT 24
Peak memory 650792 kb
Host smart-337382cf-4428-4ed2-baf3-e21dbfd8cab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3659456522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.3659456522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.4169904554
Short name T764
Test name
Test status
Simulation time 215666430188 ps
CPU time 4346.82 seconds
Started Jul 14 05:38:22 PM PDT 24
Finished Jul 14 06:50:49 PM PDT 24
Peak memory 556788 kb
Host smart-8d9d6978-b4e7-431c-b3f3-9c256893f7db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4169904554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.4169904554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.1257783240
Short name T47
Test name
Test status
Simulation time 20822756 ps
CPU time 0.86 seconds
Started Jul 14 05:38:44 PM PDT 24
Finished Jul 14 05:38:45 PM PDT 24
Peak memory 205272 kb
Host smart-f43477d6-b8c5-440e-8da4-29f8506cc5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257783240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1257783240 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1118319699
Short name T23
Test name
Test status
Simulation time 6604284210 ps
CPU time 40.75 seconds
Started Jul 14 05:38:38 PM PDT 24
Finished Jul 14 05:39:19 PM PDT 24
Peak memory 223856 kb
Host smart-3d0d9b6d-7809-4d5c-9262-53bdb942e87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118319699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1118319699 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.716861519
Short name T1052
Test name
Test status
Simulation time 80250375927 ps
CPU time 686.12 seconds
Started Jul 14 05:38:32 PM PDT 24
Finished Jul 14 05:49:58 PM PDT 24
Peak memory 230188 kb
Host smart-130bb383-167f-4eb2-b98b-bc809e4740c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716861519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.716861519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.3484420173
Short name T653
Test name
Test status
Simulation time 8307360835 ps
CPU time 67.77 seconds
Started Jul 14 05:38:38 PM PDT 24
Finished Jul 14 05:39:46 PM PDT 24
Peak memory 223928 kb
Host smart-691cb965-c9db-49ec-8f6d-de00d29da63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484420173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3484420173 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.1980756769
Short name T759
Test name
Test status
Simulation time 3613785257 ps
CPU time 251.82 seconds
Started Jul 14 05:38:39 PM PDT 24
Finished Jul 14 05:42:51 PM PDT 24
Peak memory 256608 kb
Host smart-29c07581-c16b-4701-93b4-f18303c65ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980756769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1980756769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.3941517591
Short name T372
Test name
Test status
Simulation time 922241857 ps
CPU time 3.67 seconds
Started Jul 14 05:38:37 PM PDT 24
Finished Jul 14 05:38:41 PM PDT 24
Peak memory 207240 kb
Host smart-d5f7ed06-5040-4944-8038-38978bde9746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941517591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3941517591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.982190608
Short name T802
Test name
Test status
Simulation time 139074626 ps
CPU time 1.33 seconds
Started Jul 14 05:38:44 PM PDT 24
Finished Jul 14 05:38:46 PM PDT 24
Peak memory 215680 kb
Host smart-0f623ceb-c4ed-4064-8fff-6c493da33668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982190608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.982190608 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1307005906
Short name T901
Test name
Test status
Simulation time 23253326420 ps
CPU time 2003.37 seconds
Started Jul 14 05:38:33 PM PDT 24
Finished Jul 14 06:11:57 PM PDT 24
Peak memory 442532 kb
Host smart-9b85647b-2a7d-4898-b4c1-91fc85a229da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307005906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1307005906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.2663851877
Short name T221
Test name
Test status
Simulation time 35161406957 ps
CPU time 158.56 seconds
Started Jul 14 05:38:33 PM PDT 24
Finished Jul 14 05:41:12 PM PDT 24
Peak memory 232040 kb
Host smart-7c36eb6b-b9e1-4b32-91ed-e8efe67a3615
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663851877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2663851877 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.3176624293
Short name T185
Test name
Test status
Simulation time 642171768 ps
CPU time 30.92 seconds
Started Jul 14 05:38:27 PM PDT 24
Finished Jul 14 05:38:59 PM PDT 24
Peak memory 219092 kb
Host smart-c920136e-3fb7-4fad-becc-e49db5aef984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176624293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3176624293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.66696220
Short name T515
Test name
Test status
Simulation time 20686201258 ps
CPU time 625.6 seconds
Started Jul 14 05:38:45 PM PDT 24
Finished Jul 14 05:49:11 PM PDT 24
Peak memory 305732 kb
Host smart-17d6c7a5-c5de-4ca5-986f-85eae685365d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=66696220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.66696220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.782363668
Short name T520
Test name
Test status
Simulation time 702032325 ps
CPU time 3.92 seconds
Started Jul 14 05:38:36 PM PDT 24
Finished Jul 14 05:38:40 PM PDT 24
Peak memory 215600 kb
Host smart-3d00b10e-25b3-4f50-9a07-8fffde7813b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782363668 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.kmac_test_vectors_kmac.782363668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.3384451423
Short name T706
Test name
Test status
Simulation time 1050506992 ps
CPU time 4.93 seconds
Started Jul 14 05:38:39 PM PDT 24
Finished Jul 14 05:38:44 PM PDT 24
Peak memory 215540 kb
Host smart-c30b16a9-026e-4e18-bd54-18094f52629f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384451423 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.3384451423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.421235636
Short name T718
Test name
Test status
Simulation time 115250493539 ps
CPU time 1545.55 seconds
Started Jul 14 05:38:39 PM PDT 24
Finished Jul 14 06:04:25 PM PDT 24
Peak memory 376292 kb
Host smart-1a520cc0-e17b-4593-af5d-7984c4568a26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=421235636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.421235636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.334398857
Short name T619
Test name
Test status
Simulation time 17850714833 ps
CPU time 1531.16 seconds
Started Jul 14 05:38:39 PM PDT 24
Finished Jul 14 06:04:11 PM PDT 24
Peak memory 375984 kb
Host smart-bf232789-3c6f-4339-8d50-f04a56f1a466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=334398857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.334398857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.481674100
Short name T620
Test name
Test status
Simulation time 46748096024 ps
CPU time 1322.46 seconds
Started Jul 14 05:38:38 PM PDT 24
Finished Jul 14 06:00:41 PM PDT 24
Peak memory 333728 kb
Host smart-1f4ad89e-2b82-4a77-819e-cd5b73c5a77c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=481674100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.481674100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.1711922126
Short name T201
Test name
Test status
Simulation time 56279349997 ps
CPU time 771.26 seconds
Started Jul 14 05:38:38 PM PDT 24
Finished Jul 14 05:51:29 PM PDT 24
Peak memory 295976 kb
Host smart-c6cc4c56-e65e-429c-a063-0e8d455ff4ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1711922126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1711922126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.1450075041
Short name T767
Test name
Test status
Simulation time 505655835020 ps
CPU time 4779.55 seconds
Started Jul 14 05:38:38 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 649128 kb
Host smart-a6446187-9d82-43cd-9676-babb467bb669
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1450075041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1450075041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.4172422788
Short name T227
Test name
Test status
Simulation time 179776276025 ps
CPU time 3484.97 seconds
Started Jul 14 05:38:38 PM PDT 24
Finished Jul 14 06:36:44 PM PDT 24
Peak memory 560628 kb
Host smart-a6b37627-2a48-4186-b24e-20f8f56ffe6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4172422788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.4172422788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.3686488546
Short name T912
Test name
Test status
Simulation time 90098183 ps
CPU time 0.81 seconds
Started Jul 14 05:34:15 PM PDT 24
Finished Jul 14 05:34:16 PM PDT 24
Peak memory 205264 kb
Host smart-716756dd-ea97-49ae-952a-71f70284db46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686488546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3686488546 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.3262611319
Short name T156
Test name
Test status
Simulation time 55663802738 ps
CPU time 288.26 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 05:38:59 PM PDT 24
Peak memory 243464 kb
Host smart-52bf31c1-bf07-4283-93d1-22e9caf2973d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262611319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3262611319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.1996156023
Short name T644
Test name
Test status
Simulation time 6467787788 ps
CPU time 68.15 seconds
Started Jul 14 05:34:16 PM PDT 24
Finished Jul 14 05:35:25 PM PDT 24
Peak memory 224480 kb
Host smart-e71988fb-11be-44ae-90dd-1db8ad31913e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996156023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1996156023 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.1189162869
Short name T1080
Test name
Test status
Simulation time 10646354129 ps
CPU time 273.18 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 05:38:45 PM PDT 24
Peak memory 225492 kb
Host smart-a936225f-71c3-498c-a9af-7c9b192f8343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189162869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1189162869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3764234996
Short name T260
Test name
Test status
Simulation time 3974599597 ps
CPU time 18.38 seconds
Started Jul 14 05:34:16 PM PDT 24
Finished Jul 14 05:34:35 PM PDT 24
Peak memory 218376 kb
Host smart-df24ec72-c95c-4823-83d2-a45b4c196a16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3764234996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3764234996 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.1292638721
Short name T487
Test name
Test status
Simulation time 1044567492 ps
CPU time 17.86 seconds
Started Jul 14 05:34:19 PM PDT 24
Finished Jul 14 05:34:38 PM PDT 24
Peak memory 223056 kb
Host smart-4fbd1c0d-d552-4385-b269-f0ecb2685e3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1292638721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1292638721 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.4000147223
Short name T40
Test name
Test status
Simulation time 6675002186 ps
CPU time 44.61 seconds
Started Jul 14 05:34:14 PM PDT 24
Finished Jul 14 05:34:59 PM PDT 24
Peak memory 216948 kb
Host smart-77ab7892-35ad-4f73-bd4c-65959a790070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000147223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.4000147223 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.2442337766
Short name T155
Test name
Test status
Simulation time 18407204567 ps
CPU time 312.03 seconds
Started Jul 14 05:34:16 PM PDT 24
Finished Jul 14 05:39:29 PM PDT 24
Peak memory 244152 kb
Host smart-b4f10b63-5217-408e-b3bb-a8114cdb488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442337766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2442337766 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.3733299340
Short name T320
Test name
Test status
Simulation time 2805034677 ps
CPU time 82.03 seconds
Started Jul 14 05:34:16 PM PDT 24
Finished Jul 14 05:35:39 PM PDT 24
Peak memory 240220 kb
Host smart-1ecacddb-5943-4491-90ee-0fb780b94d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733299340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3733299340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.3245622830
Short name T838
Test name
Test status
Simulation time 122281163 ps
CPU time 1.31 seconds
Started Jul 14 05:34:17 PM PDT 24
Finished Jul 14 05:34:19 PM PDT 24
Peak memory 207440 kb
Host smart-fbbc959a-714b-400b-8734-c27f04250f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245622830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3245622830 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.3426864046
Short name T57
Test name
Test status
Simulation time 232643504 ps
CPU time 4.94 seconds
Started Jul 14 05:34:17 PM PDT 24
Finished Jul 14 05:34:23 PM PDT 24
Peak memory 220104 kb
Host smart-9723531a-e769-4b96-ae23-6a6e419a9975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426864046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3426864046 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.1170577694
Short name T1056
Test name
Test status
Simulation time 350560006536 ps
CPU time 1865.91 seconds
Started Jul 14 05:34:12 PM PDT 24
Finished Jul 14 06:05:19 PM PDT 24
Peak memory 395652 kb
Host smart-42b4a669-baa5-4719-b530-45e548662707
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170577694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.1170577694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.1288643585
Short name T85
Test name
Test status
Simulation time 1337859990 ps
CPU time 9.69 seconds
Started Jul 14 05:34:22 PM PDT 24
Finished Jul 14 05:34:32 PM PDT 24
Peak memory 224028 kb
Host smart-ec2b1bdd-85da-4a29-b55d-20b6e524f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288643585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1288643585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1616208061
Short name T11
Test name
Test status
Simulation time 16716102143 ps
CPU time 63.22 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 05:35:22 PM PDT 24
Peak memory 264340 kb
Host smart-9923e23f-01f8-43eb-a915-4224b0b160c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616208061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1616208061 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.3388546025
Short name T967
Test name
Test status
Simulation time 48553453133 ps
CPU time 369.04 seconds
Started Jul 14 05:34:14 PM PDT 24
Finished Jul 14 05:40:23 PM PDT 24
Peak memory 247860 kb
Host smart-0ec13da4-ab2c-4a6d-b16c-f16a70b5c0d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388546025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3388546025 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.3720015422
Short name T791
Test name
Test status
Simulation time 56264482 ps
CPU time 1.17 seconds
Started Jul 14 05:34:12 PM PDT 24
Finished Jul 14 05:34:14 PM PDT 24
Peak memory 221872 kb
Host smart-f774aa3f-47e5-41e8-b9f0-8a2eda965542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720015422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3720015422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.4137357498
Short name T86
Test name
Test status
Simulation time 17612098776 ps
CPU time 115.54 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 05:36:14 PM PDT 24
Peak memory 240948 kb
Host smart-833f2522-9055-40a0-8a20-6fb66c22ffe9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4137357498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.4137357498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.3648052196
Short name T695
Test name
Test status
Simulation time 217885380 ps
CPU time 4.4 seconds
Started Jul 14 05:34:12 PM PDT 24
Finished Jul 14 05:34:18 PM PDT 24
Peak memory 215676 kb
Host smart-260e0c9c-754e-4cad-98dc-09cc2024233f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648052196 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.3648052196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.1374102308
Short name T362
Test name
Test status
Simulation time 863449039 ps
CPU time 4.67 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 05:34:16 PM PDT 24
Peak memory 215236 kb
Host smart-c2707358-193b-4ddf-8366-4f406930a883
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374102308 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1374102308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.1608447876
Short name T486
Test name
Test status
Simulation time 68596151162 ps
CPU time 1749.61 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 06:03:20 PM PDT 24
Peak memory 396780 kb
Host smart-b572d74b-c0f7-4e97-968f-ae6882aa0f88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1608447876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1608447876 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.763244602
Short name T79
Test name
Test status
Simulation time 17355386533 ps
CPU time 1413.61 seconds
Started Jul 14 05:34:10 PM PDT 24
Finished Jul 14 05:57:44 PM PDT 24
Peak memory 366032 kb
Host smart-6de613a6-eea3-40a3-932b-156b81018f49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=763244602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.763244602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.2316595944
Short name T281
Test name
Test status
Simulation time 145257796327 ps
CPU time 1372.12 seconds
Started Jul 14 05:34:13 PM PDT 24
Finished Jul 14 05:57:06 PM PDT 24
Peak memory 333204 kb
Host smart-13f87428-343d-471e-8c3c-de8995eafb52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2316595944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2316595944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.3146990255
Short name T1042
Test name
Test status
Simulation time 32173862122 ps
CPU time 834.18 seconds
Started Jul 14 05:34:13 PM PDT 24
Finished Jul 14 05:48:08 PM PDT 24
Peak memory 292392 kb
Host smart-b8ad95ce-ce89-47ad-a748-c01b6cf3be1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3146990255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3146990255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.3703371945
Short name T963
Test name
Test status
Simulation time 1059982865933 ps
CPU time 4942.9 seconds
Started Jul 14 05:34:11 PM PDT 24
Finished Jul 14 06:56:35 PM PDT 24
Peak memory 642556 kb
Host smart-a504c2a3-89ed-467b-b55f-155a591f142e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3703371945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3703371945 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.1251955496
Short name T398
Test name
Test status
Simulation time 1964837859485 ps
CPU time 4420.23 seconds
Started Jul 14 05:34:12 PM PDT 24
Finished Jul 14 06:47:54 PM PDT 24
Peak memory 558404 kb
Host smart-3c6cce4c-4a83-4100-8609-5b1fdf21d88b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1251955496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1251955496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3271977254
Short name T1063
Test name
Test status
Simulation time 77815729 ps
CPU time 0.9 seconds
Started Jul 14 05:39:04 PM PDT 24
Finished Jul 14 05:39:06 PM PDT 24
Peak memory 205284 kb
Host smart-f158d3ad-b60b-4b9a-9f52-b4586558d0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271977254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3271977254 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.2658788926
Short name T530
Test name
Test status
Simulation time 525613255 ps
CPU time 8.87 seconds
Started Jul 14 05:38:56 PM PDT 24
Finished Jul 14 05:39:05 PM PDT 24
Peak memory 216416 kb
Host smart-20f67ab0-362c-4409-b158-0bd52eb525f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658788926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2658788926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.3127644859
Short name T854
Test name
Test status
Simulation time 12495499874 ps
CPU time 99.07 seconds
Started Jul 14 05:38:50 PM PDT 24
Finished Jul 14 05:40:29 PM PDT 24
Peak memory 221032 kb
Host smart-26b3ab9f-2280-42b1-a7b6-7deac30a6f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127644859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3127644859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.561679588
Short name T935
Test name
Test status
Simulation time 24739310185 ps
CPU time 73 seconds
Started Jul 14 05:38:55 PM PDT 24
Finished Jul 14 05:40:08 PM PDT 24
Peak memory 226176 kb
Host smart-64f98f06-e535-4952-a1d3-04dccca3061a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561679588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.561679588 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.2819606946
Short name T668
Test name
Test status
Simulation time 1130943352 ps
CPU time 58.16 seconds
Started Jul 14 05:39:03 PM PDT 24
Finished Jul 14 05:40:02 PM PDT 24
Peak memory 240200 kb
Host smart-ce552d67-2642-4802-b0b8-4fbe9537b81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819606946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2819606946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2806046320
Short name T956
Test name
Test status
Simulation time 490658935 ps
CPU time 3.54 seconds
Started Jul 14 05:39:04 PM PDT 24
Finished Jul 14 05:39:08 PM PDT 24
Peak memory 215468 kb
Host smart-97399279-d32d-4ff2-93c7-e67efdfe95d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806046320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2806046320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.120965675
Short name T961
Test name
Test status
Simulation time 64209652 ps
CPU time 1.27 seconds
Started Jul 14 05:39:03 PM PDT 24
Finished Jul 14 05:39:05 PM PDT 24
Peak memory 215580 kb
Host smart-633391dd-7d7b-43ff-8063-c03b78337d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120965675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.120965675 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.3883745241
Short name T383
Test name
Test status
Simulation time 75106415882 ps
CPU time 1989.21 seconds
Started Jul 14 05:38:46 PM PDT 24
Finished Jul 14 06:11:56 PM PDT 24
Peak memory 424936 kb
Host smart-a43cbc06-89a9-4c9d-a29e-c20394bfef26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883745241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.3883745241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.3058641052
Short name T411
Test name
Test status
Simulation time 28435994835 ps
CPU time 133.86 seconds
Started Jul 14 05:38:51 PM PDT 24
Finished Jul 14 05:41:05 PM PDT 24
Peak memory 229960 kb
Host smart-2e66a874-920f-4541-9028-15f7bd7c7974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058641052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3058641052 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.3337789155
Short name T780
Test name
Test status
Simulation time 1187439786 ps
CPU time 31.37 seconds
Started Jul 14 05:38:46 PM PDT 24
Finished Jul 14 05:39:18 PM PDT 24
Peak memory 219876 kb
Host smart-abd26edd-6766-4cf0-8079-b26bd8f71f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337789155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3337789155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.3911508522
Short name T681
Test name
Test status
Simulation time 363444788629 ps
CPU time 2222.05 seconds
Started Jul 14 05:39:04 PM PDT 24
Finished Jul 14 06:16:07 PM PDT 24
Peak memory 435776 kb
Host smart-158665b5-ffbc-4cb7-a9ff-b3d92b7f0bb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3911508522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3911508522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.3610745192
Short name T891
Test name
Test status
Simulation time 355143465 ps
CPU time 4.8 seconds
Started Jul 14 05:38:50 PM PDT 24
Finished Jul 14 05:38:55 PM PDT 24
Peak memory 215640 kb
Host smart-cbb1c970-61f5-4c60-bc97-ddb60e7e9e22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610745192 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.3610745192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.1559148265
Short name T188
Test name
Test status
Simulation time 126143157 ps
CPU time 4.15 seconds
Started Jul 14 05:38:56 PM PDT 24
Finished Jul 14 05:39:01 PM PDT 24
Peak memory 215704 kb
Host smart-6edf0580-6773-402a-ab8f-eeb9786d55e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559148265 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.1559148265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.1796061899
Short name T1
Test name
Test status
Simulation time 18546018314 ps
CPU time 1552.5 seconds
Started Jul 14 05:38:50 PM PDT 24
Finished Jul 14 06:04:43 PM PDT 24
Peak memory 386580 kb
Host smart-863364d7-f20d-4a6b-af23-9c34fdb79d77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1796061899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.1796061899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.2067977184
Short name T676
Test name
Test status
Simulation time 35855785356 ps
CPU time 1448.54 seconds
Started Jul 14 05:38:49 PM PDT 24
Finished Jul 14 06:02:58 PM PDT 24
Peak memory 377552 kb
Host smart-2ffccf03-6e1c-4d48-a8c7-5494050f2849
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2067977184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2067977184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.3403315023
Short name T701
Test name
Test status
Simulation time 76945218343 ps
CPU time 1395.54 seconds
Started Jul 14 05:38:51 PM PDT 24
Finished Jul 14 06:02:07 PM PDT 24
Peak memory 336684 kb
Host smart-94b220c8-d8cb-4a77-bbe6-719ee513f36a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3403315023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.3403315023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.159214424
Short name T999
Test name
Test status
Simulation time 95308562035 ps
CPU time 768.09 seconds
Started Jul 14 05:38:50 PM PDT 24
Finished Jul 14 05:51:39 PM PDT 24
Peak memory 295640 kb
Host smart-dfac8981-54fb-4662-bef9-537952bec279
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=159214424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.159214424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.4291602057
Short name T470
Test name
Test status
Simulation time 4261392633662 ps
CPU time 5685.84 seconds
Started Jul 14 05:38:51 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 646260 kb
Host smart-44e4a76d-d2bc-47f5-aa73-420afea021d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4291602057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.4291602057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.3288198372
Short name T885
Test name
Test status
Simulation time 43394853324 ps
CPU time 3401.48 seconds
Started Jul 14 05:38:50 PM PDT 24
Finished Jul 14 06:35:32 PM PDT 24
Peak memory 563520 kb
Host smart-19961cfd-f50a-4ad9-b486-d3ade7d7d7ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3288198372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3288198372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.3713833368
Short name T766
Test name
Test status
Simulation time 45696151 ps
CPU time 0.82 seconds
Started Jul 14 05:39:19 PM PDT 24
Finished Jul 14 05:39:20 PM PDT 24
Peak memory 205208 kb
Host smart-60e678e8-d94c-4cf5-9d9d-7d4f9f78f687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713833368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3713833368 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.4106717787
Short name T426
Test name
Test status
Simulation time 6100620789 ps
CPU time 105.8 seconds
Started Jul 14 05:39:14 PM PDT 24
Finished Jul 14 05:41:01 PM PDT 24
Peak memory 230276 kb
Host smart-4c3293ee-2a62-486e-bd09-8eb05c4dde9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106717787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.4106717787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.171179929
Short name T738
Test name
Test status
Simulation time 6662047195 ps
CPU time 524.4 seconds
Started Jul 14 05:39:04 PM PDT 24
Finished Jul 14 05:47:49 PM PDT 24
Peak memory 231616 kb
Host smart-b3c52ec1-a57d-46ef-bee7-50a2dca7743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171179929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.171179929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.1717664642
Short name T1026
Test name
Test status
Simulation time 2502972871 ps
CPU time 46.99 seconds
Started Jul 14 05:39:13 PM PDT 24
Finished Jul 14 05:40:01 PM PDT 24
Peak memory 223840 kb
Host smart-b9c08742-4665-4b51-a766-1ab624f22984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717664642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1717664642 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.3710687881
Short name T25
Test name
Test status
Simulation time 15172843591 ps
CPU time 109.5 seconds
Started Jul 14 05:39:16 PM PDT 24
Finished Jul 14 05:41:06 PM PDT 24
Peak memory 240144 kb
Host smart-a6a16739-8502-4b90-8203-882da841a8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710687881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3710687881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.2797914557
Short name T656
Test name
Test status
Simulation time 3976571990 ps
CPU time 6.06 seconds
Started Jul 14 05:39:15 PM PDT 24
Finished Jul 14 05:39:21 PM PDT 24
Peak memory 207256 kb
Host smart-d8d78e0b-9342-46b7-94ba-e9040f2d6333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797914557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2797914557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.170059491
Short name T56
Test name
Test status
Simulation time 3227063897 ps
CPU time 15.31 seconds
Started Jul 14 05:39:21 PM PDT 24
Finished Jul 14 05:39:37 PM PDT 24
Peak memory 223908 kb
Host smart-09f3d425-9096-4e92-ad5a-c9baf00298dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170059491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.170059491 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.1931833027
Short name T709
Test name
Test status
Simulation time 545687923288 ps
CPU time 2578.22 seconds
Started Jul 14 05:39:02 PM PDT 24
Finished Jul 14 06:22:00 PM PDT 24
Peak memory 451972 kb
Host smart-eae7eb66-e3e3-46a9-a212-877ebd8e05db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931833027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.1931833027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.3271472244
Short name T972
Test name
Test status
Simulation time 6011287769 ps
CPU time 38.29 seconds
Started Jul 14 05:39:03 PM PDT 24
Finished Jul 14 05:39:42 PM PDT 24
Peak memory 223824 kb
Host smart-3fc46e4c-eb27-480f-a1fa-7dcbda9c8fc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271472244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3271472244 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.3641708447
Short name T898
Test name
Test status
Simulation time 1285240134 ps
CPU time 36.74 seconds
Started Jul 14 05:39:04 PM PDT 24
Finished Jul 14 05:39:41 PM PDT 24
Peak memory 218956 kb
Host smart-92c4d614-c9ac-4d5b-96cf-abbcf3d65630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641708447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3641708447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.2535712063
Short name T1069
Test name
Test status
Simulation time 26041771730 ps
CPU time 665.85 seconds
Started Jul 14 05:39:18 PM PDT 24
Finished Jul 14 05:50:24 PM PDT 24
Peak memory 321288 kb
Host smart-f7e58719-2e06-4d4a-9b7e-bf73f1b2fb60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2535712063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2535712063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.1681530185
Short name T952
Test name
Test status
Simulation time 341508823 ps
CPU time 3.97 seconds
Started Jul 14 05:39:15 PM PDT 24
Finished Jul 14 05:39:19 PM PDT 24
Peak memory 215524 kb
Host smart-94cf34b9-b08d-4c37-82be-876890933cd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681530185 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.1681530185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.4224107282
Short name T583
Test name
Test status
Simulation time 268228808 ps
CPU time 4.06 seconds
Started Jul 14 05:39:16 PM PDT 24
Finished Jul 14 05:39:21 PM PDT 24
Peak memory 215504 kb
Host smart-88ba5941-4a1d-45ae-b3e8-ec8d948ef2ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224107282 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.4224107282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.590468324
Short name T744
Test name
Test status
Simulation time 129778992477 ps
CPU time 1795.65 seconds
Started Jul 14 05:39:00 PM PDT 24
Finished Jul 14 06:08:56 PM PDT 24
Peak memory 392200 kb
Host smart-6249ef5a-4bbf-4808-a5b5-d17008e6a868
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=590468324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.590468324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.1161040857
Short name T190
Test name
Test status
Simulation time 66596372864 ps
CPU time 1701.15 seconds
Started Jul 14 05:39:04 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 374936 kb
Host smart-cc8a8e80-7e27-4c42-ade1-158cf0f5d333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1161040857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.1161040857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.349580064
Short name T661
Test name
Test status
Simulation time 197346137105 ps
CPU time 1454.33 seconds
Started Jul 14 05:39:03 PM PDT 24
Finished Jul 14 06:03:18 PM PDT 24
Peak memory 337428 kb
Host smart-8b61ab73-c6ce-4981-9e83-744cad06c118
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=349580064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.349580064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1849716331
Short name T748
Test name
Test status
Simulation time 49217015043 ps
CPU time 981.37 seconds
Started Jul 14 05:39:11 PM PDT 24
Finished Jul 14 05:55:33 PM PDT 24
Peak memory 292788 kb
Host smart-d7487408-35e5-4716-880c-52f2edb29d0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1849716331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1849716331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.2081738912
Short name T650
Test name
Test status
Simulation time 103091253883 ps
CPU time 4075.86 seconds
Started Jul 14 05:39:10 PM PDT 24
Finished Jul 14 06:47:06 PM PDT 24
Peak memory 644184 kb
Host smart-9e063a9a-c67b-414c-b9ea-f21d34df560b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2081738912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.2081738912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.2011186656
Short name T941
Test name
Test status
Simulation time 1206564057130 ps
CPU time 4585.26 seconds
Started Jul 14 05:39:15 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 562500 kb
Host smart-82482859-6740-490b-9985-a68bb703d3be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2011186656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.2011186656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.2286608179
Short name T310
Test name
Test status
Simulation time 18745826 ps
CPU time 0.82 seconds
Started Jul 14 05:39:37 PM PDT 24
Finished Jul 14 05:39:38 PM PDT 24
Peak memory 205264 kb
Host smart-5763f519-6a13-4678-ba2c-d9f6d82c83b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286608179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2286608179 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.482618850
Short name T532
Test name
Test status
Simulation time 25464998917 ps
CPU time 271.22 seconds
Started Jul 14 05:39:30 PM PDT 24
Finished Jul 14 05:44:02 PM PDT 24
Peak memory 241324 kb
Host smart-ff5f7efa-0418-4030-bc3b-ea63a7d3d5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482618850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.482618850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.917082683
Short name T737
Test name
Test status
Simulation time 61596382945 ps
CPU time 391.07 seconds
Started Jul 14 05:39:23 PM PDT 24
Finished Jul 14 05:45:55 PM PDT 24
Peak memory 226512 kb
Host smart-e3845e93-ab52-4002-865d-1db80c6ece8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917082683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.917082683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.1732005888
Short name T635
Test name
Test status
Simulation time 7681396174 ps
CPU time 144.57 seconds
Started Jul 14 05:39:31 PM PDT 24
Finished Jul 14 05:41:56 PM PDT 24
Peak memory 233516 kb
Host smart-e0abf55e-e23e-40d2-8eaf-c0b70a44f8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732005888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1732005888 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.3690848796
Short name T867
Test name
Test status
Simulation time 14021119773 ps
CPU time 396.08 seconds
Started Jul 14 05:39:31 PM PDT 24
Finished Jul 14 05:46:08 PM PDT 24
Peak memory 257608 kb
Host smart-c4e0a1f7-4573-4931-a573-54a8290ebedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690848796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3690848796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2608043644
Short name T469
Test name
Test status
Simulation time 1665538544 ps
CPU time 2.53 seconds
Started Jul 14 05:39:31 PM PDT 24
Finished Jul 14 05:39:34 PM PDT 24
Peak memory 215452 kb
Host smart-f08c2868-b5f4-401b-86d1-435885be334e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608043644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2608043644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.3139230489
Short name T535
Test name
Test status
Simulation time 1375923867 ps
CPU time 26.37 seconds
Started Jul 14 05:39:31 PM PDT 24
Finished Jul 14 05:39:58 PM PDT 24
Peak memory 231904 kb
Host smart-e0f07794-cadc-4b54-afc5-cd8525086797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139230489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3139230489 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.2271537199
Short name T560
Test name
Test status
Simulation time 1499605779 ps
CPU time 132.91 seconds
Started Jul 14 05:39:21 PM PDT 24
Finished Jul 14 05:41:35 PM PDT 24
Peak memory 236976 kb
Host smart-56126ae9-81d8-458f-8c31-b9e7e549f3bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271537199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.2271537199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.1694231645
Short name T825
Test name
Test status
Simulation time 39704526288 ps
CPU time 281.88 seconds
Started Jul 14 05:39:23 PM PDT 24
Finished Jul 14 05:44:06 PM PDT 24
Peak memory 246480 kb
Host smart-02a498ec-0965-45ce-af6e-7f1cc493795d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694231645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1694231645 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.1314959833
Short name T798
Test name
Test status
Simulation time 16026225775 ps
CPU time 60.38 seconds
Started Jul 14 05:39:21 PM PDT 24
Finished Jul 14 05:40:21 PM PDT 24
Peak memory 219504 kb
Host smart-0c9a5ad8-5ab4-4b5e-a5c0-e475c075bfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314959833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1314959833 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.3110307777
Short name T475
Test name
Test status
Simulation time 49849988915 ps
CPU time 1243.52 seconds
Started Jul 14 05:39:39 PM PDT 24
Finished Jul 14 06:00:23 PM PDT 24
Peak memory 355204 kb
Host smart-70a14aba-0939-46b3-b3bc-9ea5c8f6d4c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3110307777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3110307777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.1792696071
Short name T71
Test name
Test status
Simulation time 674292510 ps
CPU time 4.51 seconds
Started Jul 14 05:39:27 PM PDT 24
Finished Jul 14 05:39:31 PM PDT 24
Peak memory 215652 kb
Host smart-5497c42e-3936-4f13-8dfa-0ea3b5f57801
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792696071 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.1792696071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.1066368238
Short name T1055
Test name
Test status
Simulation time 64231350 ps
CPU time 3.84 seconds
Started Jul 14 05:39:26 PM PDT 24
Finished Jul 14 05:39:30 PM PDT 24
Peak memory 215508 kb
Host smart-afef2c88-520d-4209-995c-154aea6ecc98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066368238 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.1066368238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3087754087
Short name T716
Test name
Test status
Simulation time 96448550688 ps
CPU time 1760.94 seconds
Started Jul 14 05:39:20 PM PDT 24
Finished Jul 14 06:08:41 PM PDT 24
Peak memory 401696 kb
Host smart-aa682259-1387-4b86-80ec-5f11b153a451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3087754087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3087754087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.845781544
Short name T727
Test name
Test status
Simulation time 18778787673 ps
CPU time 1439.17 seconds
Started Jul 14 05:39:21 PM PDT 24
Finished Jul 14 06:03:21 PM PDT 24
Peak memory 376376 kb
Host smart-764d98b5-e49d-4acc-960e-04df8a820836
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=845781544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.845781544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.1804013116
Short name T1007
Test name
Test status
Simulation time 27756494683 ps
CPU time 1172.91 seconds
Started Jul 14 05:39:21 PM PDT 24
Finished Jul 14 05:58:54 PM PDT 24
Peak memory 334168 kb
Host smart-7caf427b-cf8e-4c97-9f6e-eadb6d0eeb09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1804013116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.1804013116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.818848847
Short name T1083
Test name
Test status
Simulation time 32796463200 ps
CPU time 852.03 seconds
Started Jul 14 05:39:25 PM PDT 24
Finished Jul 14 05:53:37 PM PDT 24
Peak memory 288172 kb
Host smart-ee81e704-9781-4883-a928-0a80d84ae987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=818848847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.818848847 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.1031552971
Short name T985
Test name
Test status
Simulation time 106201526720 ps
CPU time 3829.94 seconds
Started Jul 14 05:39:26 PM PDT 24
Finished Jul 14 06:43:17 PM PDT 24
Peak memory 653764 kb
Host smart-43ce7602-fcef-42fa-86b0-5d9d797ba41c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1031552971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.1031552971 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.1162272238
Short name T804
Test name
Test status
Simulation time 331713062989 ps
CPU time 3539.51 seconds
Started Jul 14 05:39:25 PM PDT 24
Finished Jul 14 06:38:25 PM PDT 24
Peak memory 557700 kb
Host smart-f7208c84-8be2-4297-8991-7e14100626c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1162272238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1162272238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.4063416600
Short name T448
Test name
Test status
Simulation time 40875120 ps
CPU time 0.73 seconds
Started Jul 14 05:40:00 PM PDT 24
Finished Jul 14 05:40:01 PM PDT 24
Peak memory 205208 kb
Host smart-3b53501f-d3a7-4a08-81b9-88f2f5292284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063416600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.4063416600 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.496746923
Short name T702
Test name
Test status
Simulation time 20268165190 ps
CPU time 251.26 seconds
Started Jul 14 05:39:55 PM PDT 24
Finished Jul 14 05:44:06 PM PDT 24
Peak memory 241764 kb
Host smart-6d2740d3-6f50-4e94-a6eb-4b8e7d2d03ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496746923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.496746923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.342140259
Short name T578
Test name
Test status
Simulation time 36553606204 ps
CPU time 240.81 seconds
Started Jul 14 05:39:40 PM PDT 24
Finished Jul 14 05:43:41 PM PDT 24
Peak memory 225536 kb
Host smart-8474700e-d78e-48d0-bf1c-d11008359efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342140259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.342140259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.1676149959
Short name T103
Test name
Test status
Simulation time 6483813034 ps
CPU time 57.33 seconds
Started Jul 14 05:39:55 PM PDT 24
Finished Jul 14 05:40:53 PM PDT 24
Peak memory 225056 kb
Host smart-254aebce-63b6-48f9-8513-18f474f8b69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676149959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1676149959 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.1987690631
Short name T1065
Test name
Test status
Simulation time 3419139512 ps
CPU time 60.42 seconds
Started Jul 14 05:39:54 PM PDT 24
Finished Jul 14 05:40:55 PM PDT 24
Peak memory 240176 kb
Host smart-e6e41c33-5750-4ba5-b3d3-72e0a39af9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987690631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1987690631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.3510150163
Short name T65
Test name
Test status
Simulation time 5766620762 ps
CPU time 7.67 seconds
Started Jul 14 05:39:55 PM PDT 24
Finished Jul 14 05:40:03 PM PDT 24
Peak memory 215672 kb
Host smart-21656642-7352-4411-887e-177dbd22aabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510150163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3510150163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.4194061442
Short name T296
Test name
Test status
Simulation time 57221636 ps
CPU time 1.41 seconds
Started Jul 14 05:39:55 PM PDT 24
Finished Jul 14 05:39:57 PM PDT 24
Peak memory 215692 kb
Host smart-6b25b3b1-02c2-4380-aa5a-826129f8c3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194061442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.4194061442 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.2125291162
Short name T208
Test name
Test status
Simulation time 7340976889 ps
CPU time 601.38 seconds
Started Jul 14 05:39:37 PM PDT 24
Finished Jul 14 05:49:39 PM PDT 24
Peak memory 286120 kb
Host smart-a10ec2dc-7873-4320-9a45-c1149f4f5fc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125291162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.2125291162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.514252249
Short name T461
Test name
Test status
Simulation time 48579105554 ps
CPU time 239.07 seconds
Started Jul 14 05:39:41 PM PDT 24
Finished Jul 14 05:43:40 PM PDT 24
Peak memory 237716 kb
Host smart-779ac745-f48b-4ed3-afd1-d0752019cd81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514252249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.514252249 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.397599033
Short name T385
Test name
Test status
Simulation time 931968934 ps
CPU time 23.93 seconds
Started Jul 14 05:39:39 PM PDT 24
Finished Jul 14 05:40:03 PM PDT 24
Peak memory 219360 kb
Host smart-59927f50-e50b-49a6-8abc-d16ffa0d35d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397599033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.397599033 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.1996637138
Short name T833
Test name
Test status
Simulation time 22324287498 ps
CPU time 400.12 seconds
Started Jul 14 05:39:55 PM PDT 24
Finished Jul 14 05:46:36 PM PDT 24
Peak memory 282404 kb
Host smart-f4c090ed-8735-4c6f-a000-19b36f122157
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1996637138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1996637138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.2594616771
Short name T554
Test name
Test status
Simulation time 336367087 ps
CPU time 4.52 seconds
Started Jul 14 05:39:43 PM PDT 24
Finished Jul 14 05:39:48 PM PDT 24
Peak memory 215576 kb
Host smart-2475e4a1-1c40-4649-a2cf-eb6d1f68bd30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594616771 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.2594616771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3626786168
Short name T758
Test name
Test status
Simulation time 63753920 ps
CPU time 3.41 seconds
Started Jul 14 05:39:52 PM PDT 24
Finished Jul 14 05:39:56 PM PDT 24
Peak memory 215516 kb
Host smart-8130b7b8-ebd1-4fd1-8b01-e073a480c487
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626786168 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3626786168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.2086285427
Short name T818
Test name
Test status
Simulation time 18781431696 ps
CPU time 1575.52 seconds
Started Jul 14 05:39:39 PM PDT 24
Finished Jul 14 06:05:55 PM PDT 24
Peak memory 376308 kb
Host smart-57347c49-8ee6-4351-80e3-0c9061c387b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2086285427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.2086285427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.784761630
Short name T577
Test name
Test status
Simulation time 18457037386 ps
CPU time 1532.21 seconds
Started Jul 14 05:39:44 PM PDT 24
Finished Jul 14 06:05:16 PM PDT 24
Peak memory 373504 kb
Host smart-7d199759-c004-4340-a3b8-da28308de3ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=784761630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.784761630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.2274381207
Short name T659
Test name
Test status
Simulation time 53498777545 ps
CPU time 1073.62 seconds
Started Jul 14 05:39:44 PM PDT 24
Finished Jul 14 05:57:38 PM PDT 24
Peak memory 329884 kb
Host smart-429e4ca9-6d92-4dbe-8f31-faee0851d395
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2274381207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.2274381207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.3231145048
Short name T954
Test name
Test status
Simulation time 66468470190 ps
CPU time 896.38 seconds
Started Jul 14 05:39:43 PM PDT 24
Finished Jul 14 05:54:40 PM PDT 24
Peak memory 298004 kb
Host smart-f2ee175e-cff3-47db-8594-9ce5faf8d054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3231145048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3231145048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.3859815
Short name T198
Test name
Test status
Simulation time 220814150041 ps
CPU time 4708.35 seconds
Started Jul 14 05:39:43 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 639968 kb
Host smart-5422078d-6560-44fc-9574-a80fbfcac9aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3859815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3859815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.1769171642
Short name T893
Test name
Test status
Simulation time 1274573928888 ps
CPU time 4329.55 seconds
Started Jul 14 05:39:43 PM PDT 24
Finished Jul 14 06:51:54 PM PDT 24
Peak memory 562956 kb
Host smart-9d41e393-f7a1-4c5a-b48d-30cfa353412b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1769171642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.1769171642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_app.2962354070
Short name T195
Test name
Test status
Simulation time 3815850127 ps
CPU time 74.09 seconds
Started Jul 14 05:40:12 PM PDT 24
Finished Jul 14 05:41:27 PM PDT 24
Peak memory 228804 kb
Host smart-bad237f8-38b9-4e5c-a223-b92760a148ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962354070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2962354070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.3222961360
Short name T1085
Test name
Test status
Simulation time 28183753702 ps
CPU time 598.44 seconds
Started Jul 14 05:40:00 PM PDT 24
Finished Jul 14 05:49:59 PM PDT 24
Peak memory 231528 kb
Host smart-326008a3-3c73-4c4e-8163-7916cb62be52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222961360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3222961360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.2368180567
Short name T688
Test name
Test status
Simulation time 31591417673 ps
CPU time 133.72 seconds
Started Jul 14 05:40:13 PM PDT 24
Finished Jul 14 05:42:27 PM PDT 24
Peak memory 231060 kb
Host smart-e9470db8-ff98-4e03-a43a-b94b79c6e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368180567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2368180567 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.2960551830
Short name T746
Test name
Test status
Simulation time 10787616484 ps
CPU time 293.5 seconds
Started Jul 14 05:40:14 PM PDT 24
Finished Jul 14 05:45:08 PM PDT 24
Peak memory 256608 kb
Host smart-e943f1ea-66b7-41a5-94e1-8ddda640e424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960551830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2960551830 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.229471639
Short name T514
Test name
Test status
Simulation time 1101474666 ps
CPU time 2.24 seconds
Started Jul 14 05:40:13 PM PDT 24
Finished Jul 14 05:40:16 PM PDT 24
Peak memory 207348 kb
Host smart-be9e8d89-6ef8-4363-b786-4ddeec5d6da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229471639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.229471639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.1536506933
Short name T6
Test name
Test status
Simulation time 119650140 ps
CPU time 1.29 seconds
Started Jul 14 05:40:19 PM PDT 24
Finished Jul 14 05:40:21 PM PDT 24
Peak memory 215496 kb
Host smart-1f8b7840-9f06-4c95-8e8b-4b782fa70221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536506933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1536506933 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.3771154212
Short name T720
Test name
Test status
Simulation time 32551043314 ps
CPU time 943.27 seconds
Started Jul 14 05:40:01 PM PDT 24
Finished Jul 14 05:55:44 PM PDT 24
Peak memory 306760 kb
Host smart-f7f61bf8-9d1d-46f5-a22a-5b727c4cf186
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771154212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.3771154212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.237886895
Short name T236
Test name
Test status
Simulation time 150257251289 ps
CPU time 425.89 seconds
Started Jul 14 05:39:59 PM PDT 24
Finished Jul 14 05:47:05 PM PDT 24
Peak memory 248640 kb
Host smart-4f5660ba-5f0e-423d-b13b-181389552423
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237886895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.237886895 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.3283152384
Short name T380
Test name
Test status
Simulation time 3831444179 ps
CPU time 43.89 seconds
Started Jul 14 05:39:59 PM PDT 24
Finished Jul 14 05:40:43 PM PDT 24
Peak memory 221692 kb
Host smart-1b10dd96-04d0-4f00-bdfb-3c9ca288cd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283152384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3283152384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.2473605538
Short name T685
Test name
Test status
Simulation time 9679862556 ps
CPU time 37.81 seconds
Started Jul 14 05:40:19 PM PDT 24
Finished Jul 14 05:40:57 PM PDT 24
Peak memory 221736 kb
Host smart-8055a1f9-ee09-4006-b8d8-d5e932451803
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2473605538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2473605538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1268949196
Short name T557
Test name
Test status
Simulation time 243969504 ps
CPU time 3.92 seconds
Started Jul 14 05:40:13 PM PDT 24
Finished Jul 14 05:40:18 PM PDT 24
Peak memory 215696 kb
Host smart-5f4bcc16-64cf-4f04-be34-6db80c950ea3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268949196 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1268949196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.3833482998
Short name T944
Test name
Test status
Simulation time 259385102 ps
CPU time 5.38 seconds
Started Jul 14 05:40:14 PM PDT 24
Finished Jul 14 05:40:20 PM PDT 24
Peak memory 215672 kb
Host smart-127be6fd-1e3d-4435-ab35-6ef3dffb64fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833482998 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.3833482998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.3769402369
Short name T1081
Test name
Test status
Simulation time 129365624863 ps
CPU time 1711.04 seconds
Started Jul 14 05:40:10 PM PDT 24
Finished Jul 14 06:08:41 PM PDT 24
Peak memory 375868 kb
Host smart-1a0fcbe6-b213-4b6b-81ef-e15468202660
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3769402369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3769402369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.973881409
Short name T983
Test name
Test status
Simulation time 62020371944 ps
CPU time 1744.6 seconds
Started Jul 14 05:40:05 PM PDT 24
Finished Jul 14 06:09:10 PM PDT 24
Peak memory 364852 kb
Host smart-650ae75c-36a6-425f-b749-b70476e34bef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=973881409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.973881409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.577417108
Short name T926
Test name
Test status
Simulation time 48533830966 ps
CPU time 1208.87 seconds
Started Jul 14 05:40:06 PM PDT 24
Finished Jul 14 06:00:15 PM PDT 24
Peak memory 329992 kb
Host smart-d33197c2-e393-449e-896f-59f9b696e7f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=577417108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.577417108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.1545676245
Short name T205
Test name
Test status
Simulation time 406800028311 ps
CPU time 947.09 seconds
Started Jul 14 05:40:10 PM PDT 24
Finished Jul 14 05:55:57 PM PDT 24
Peak memory 294804 kb
Host smart-43aa1656-0789-4785-a29a-53d04129a652
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1545676245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.1545676245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.3894445734
Short name T452
Test name
Test status
Simulation time 177630374199 ps
CPU time 4408.96 seconds
Started Jul 14 05:40:07 PM PDT 24
Finished Jul 14 06:53:37 PM PDT 24
Peak memory 641072 kb
Host smart-83c8d9e9-fd97-4c17-adfd-b8e54b4bcea5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3894445734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.3894445734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.2016827166
Short name T481
Test name
Test status
Simulation time 1121802016161 ps
CPU time 4517.26 seconds
Started Jul 14 05:40:07 PM PDT 24
Finished Jul 14 06:55:25 PM PDT 24
Peak memory 563980 kb
Host smart-37b23118-05df-4f78-bf60-b8dedeb01b20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2016827166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.2016827166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.1424883534
Short name T739
Test name
Test status
Simulation time 58613853 ps
CPU time 0.84 seconds
Started Jul 14 05:40:42 PM PDT 24
Finished Jul 14 05:40:44 PM PDT 24
Peak memory 205160 kb
Host smart-ae2d15ca-e1b6-4a6b-a18c-95286ececd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424883534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1424883534 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.2760077548
Short name T152
Test name
Test status
Simulation time 56880621171 ps
CPU time 247.86 seconds
Started Jul 14 05:40:35 PM PDT 24
Finished Jul 14 05:44:44 PM PDT 24
Peak memory 243112 kb
Host smart-9b73148b-199d-4e8f-8d1c-ab5853c5e6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760077548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2760077548 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3913736535
Short name T829
Test name
Test status
Simulation time 4728996584 ps
CPU time 437.59 seconds
Started Jul 14 05:40:27 PM PDT 24
Finished Jul 14 05:47:45 PM PDT 24
Peak memory 228384 kb
Host smart-ae59bcf0-31bf-4f0f-8162-62f2eea1a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913736535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3913736535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.3128372688
Short name T544
Test name
Test status
Simulation time 31713766376 ps
CPU time 151.62 seconds
Started Jul 14 05:40:34 PM PDT 24
Finished Jul 14 05:43:06 PM PDT 24
Peak memory 232900 kb
Host smart-92f81134-b31f-4153-a3ea-83185454aee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128372688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3128372688 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.231456384
Short name T1003
Test name
Test status
Simulation time 34617132761 ps
CPU time 362.46 seconds
Started Jul 14 05:40:34 PM PDT 24
Finished Jul 14 05:46:37 PM PDT 24
Peak memory 256588 kb
Host smart-8dcdb444-4e8b-4852-95f0-29130f6e00ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231456384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.231456384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.1712735850
Short name T637
Test name
Test status
Simulation time 167749207 ps
CPU time 1.49 seconds
Started Jul 14 05:40:41 PM PDT 24
Finished Jul 14 05:40:43 PM PDT 24
Peak memory 207160 kb
Host smart-61c6bbe3-41d6-40e6-8925-ca006fbda424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712735850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1712735850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.4161296234
Short name T579
Test name
Test status
Simulation time 3117593292 ps
CPU time 12.51 seconds
Started Jul 14 05:40:44 PM PDT 24
Finished Jul 14 05:40:57 PM PDT 24
Peak memory 220324 kb
Host smart-ebf53368-f807-4c75-8b76-b3da90a76f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161296234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.4161296234 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.3136801637
Short name T1010
Test name
Test status
Simulation time 64231574901 ps
CPU time 1481.53 seconds
Started Jul 14 05:40:21 PM PDT 24
Finished Jul 14 06:05:03 PM PDT 24
Peak memory 370132 kb
Host smart-6b9886a0-c665-4d10-9756-704855cf0ab8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136801637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.3136801637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.2773389089
Short name T610
Test name
Test status
Simulation time 10803363888 ps
CPU time 226.64 seconds
Started Jul 14 05:40:28 PM PDT 24
Finished Jul 14 05:44:15 PM PDT 24
Peak memory 238056 kb
Host smart-034e002f-5e63-4ec0-bf49-bcca992915be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773389089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2773389089 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.1627972968
Short name T439
Test name
Test status
Simulation time 2572080039 ps
CPU time 15.48 seconds
Started Jul 14 05:40:20 PM PDT 24
Finished Jul 14 05:40:35 PM PDT 24
Peak memory 218172 kb
Host smart-e721b637-add6-473c-af25-86928771f401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627972968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1627972968 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.792960771
Short name T846
Test name
Test status
Simulation time 220231051865 ps
CPU time 692.53 seconds
Started Jul 14 05:40:43 PM PDT 24
Finished Jul 14 05:52:17 PM PDT 24
Peak memory 304088 kb
Host smart-2e9777b0-416f-4cb5-8386-2ee3f01f536c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=792960771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.792960771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.3715779905
Short name T642
Test name
Test status
Simulation time 953995796 ps
CPU time 4.4 seconds
Started Jul 14 05:40:34 PM PDT 24
Finished Jul 14 05:40:39 PM PDT 24
Peak memory 215604 kb
Host smart-bf2ace6c-e6ca-4538-b6ca-cf7c4d7b54ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715779905 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.3715779905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.249586853
Short name T223
Test name
Test status
Simulation time 359959767 ps
CPU time 5.09 seconds
Started Jul 14 05:40:36 PM PDT 24
Finished Jul 14 05:40:42 PM PDT 24
Peak memory 215592 kb
Host smart-0a10296b-ebf8-4325-98c6-4889ced14577
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249586853 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.kmac_test_vectors_kmac_xof.249586853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.278249984
Short name T301
Test name
Test status
Simulation time 18708057819 ps
CPU time 1544.57 seconds
Started Jul 14 05:40:27 PM PDT 24
Finished Jul 14 06:06:12 PM PDT 24
Peak memory 390088 kb
Host smart-8d063961-8401-4687-88f8-cd09582b5e23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=278249984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.278249984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.3913918678
Short name T621
Test name
Test status
Simulation time 191535430736 ps
CPU time 1963.84 seconds
Started Jul 14 05:40:25 PM PDT 24
Finished Jul 14 06:13:09 PM PDT 24
Peak memory 376008 kb
Host smart-255fe778-3c63-4710-86c9-d729b2a91c72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3913918678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.3913918678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3080203789
Short name T546
Test name
Test status
Simulation time 75134737294 ps
CPU time 1241.49 seconds
Started Jul 14 05:40:28 PM PDT 24
Finished Jul 14 06:01:10 PM PDT 24
Peak memory 331916 kb
Host smart-ce8f392c-13a0-4452-a469-85ab739d9733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3080203789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3080203789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.1395956345
Short name T331
Test name
Test status
Simulation time 143601149907 ps
CPU time 934.13 seconds
Started Jul 14 05:40:36 PM PDT 24
Finished Jul 14 05:56:10 PM PDT 24
Peak memory 297440 kb
Host smart-839c76b6-d819-4b1b-9d60-76bb8f7b7751
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1395956345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1395956345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.1521095584
Short name T930
Test name
Test status
Simulation time 52901952863 ps
CPU time 4266.77 seconds
Started Jul 14 05:40:34 PM PDT 24
Finished Jul 14 06:51:42 PM PDT 24
Peak memory 648572 kb
Host smart-f49f2ae9-1cb4-4fb3-9355-1951bf63a5ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1521095584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.1521095584 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.1387031006
Short name T573
Test name
Test status
Simulation time 1542732980831 ps
CPU time 4782.29 seconds
Started Jul 14 05:40:34 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 558248 kb
Host smart-0c123f6e-d2b3-4b63-9537-ea75fbcce00f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1387031006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.1387031006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.323852502
Short name T836
Test name
Test status
Simulation time 18914366 ps
CPU time 0.85 seconds
Started Jul 14 05:41:02 PM PDT 24
Finished Jul 14 05:41:03 PM PDT 24
Peak memory 205232 kb
Host smart-a260a2aa-cec9-4efa-a01b-1bb5587b9419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323852502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.323852502 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.4168886211
Short name T955
Test name
Test status
Simulation time 1317924497 ps
CPU time 6.96 seconds
Started Jul 14 05:40:52 PM PDT 24
Finished Jul 14 05:40:59 PM PDT 24
Peak memory 220500 kb
Host smart-e8008dda-43b7-46b3-bb76-4e0e8b9dcd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168886211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.4168886211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.4141060749
Short name T632
Test name
Test status
Simulation time 11133709478 ps
CPU time 245.7 seconds
Started Jul 14 05:40:43 PM PDT 24
Finished Jul 14 05:44:49 PM PDT 24
Peak memory 224796 kb
Host smart-fad72d10-3436-4a56-8be9-7f18637828a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141060749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.4141060749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.2445630083
Short name T852
Test name
Test status
Simulation time 31513347629 ps
CPU time 192.67 seconds
Started Jul 14 05:41:03 PM PDT 24
Finished Jul 14 05:44:16 PM PDT 24
Peak memory 238568 kb
Host smart-ebce8426-a88b-4eba-8646-0b40efb64986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445630083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2445630083 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.2407486555
Short name T909
Test name
Test status
Simulation time 25982866323 ps
CPU time 133.35 seconds
Started Jul 14 05:41:01 PM PDT 24
Finished Jul 14 05:43:15 PM PDT 24
Peak memory 240280 kb
Host smart-75a18c71-eb69-406f-88be-56809d75a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407486555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2407486555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.1695583309
Short name T894
Test name
Test status
Simulation time 3276699174 ps
CPU time 4.72 seconds
Started Jul 14 05:41:02 PM PDT 24
Finished Jul 14 05:41:07 PM PDT 24
Peak memory 215488 kb
Host smart-9e57c537-cfa2-484c-8312-03ca79b4a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695583309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1695583309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.3564785794
Short name T326
Test name
Test status
Simulation time 864316990748 ps
CPU time 3006.7 seconds
Started Jul 14 05:40:43 PM PDT 24
Finished Jul 14 06:30:51 PM PDT 24
Peak memory 480988 kb
Host smart-5c600ed6-25b6-4cd7-99ae-63e17c74e2b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564785794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.3564785794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.3347333901
Short name T927
Test name
Test status
Simulation time 4598595147 ps
CPU time 360.84 seconds
Started Jul 14 05:40:44 PM PDT 24
Finished Jul 14 05:46:46 PM PDT 24
Peak memory 252408 kb
Host smart-883c638a-0c7e-42fd-8806-144a4fd13b2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347333901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3347333901 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.1334086774
Short name T552
Test name
Test status
Simulation time 913241951 ps
CPU time 14.85 seconds
Started Jul 14 05:40:43 PM PDT 24
Finished Jul 14 05:40:59 PM PDT 24
Peak memory 220092 kb
Host smart-57eb7b3c-16c7-495c-b0cc-e83a0168dee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334086774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1334086774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.2810909915
Short name T153
Test name
Test status
Simulation time 68668443434 ps
CPU time 1470.46 seconds
Started Jul 14 05:40:59 PM PDT 24
Finished Jul 14 06:05:30 PM PDT 24
Peak memory 392796 kb
Host smart-560098c9-76b1-4496-a3a0-4e6c2981f653
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2810909915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2810909915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.3748813340
Short name T1040
Test name
Test status
Simulation time 257881202 ps
CPU time 4.98 seconds
Started Jul 14 05:40:49 PM PDT 24
Finished Jul 14 05:40:55 PM PDT 24
Peak memory 215716 kb
Host smart-aad1862d-ef8d-4a53-820c-1b61a9e7369a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748813340 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.3748813340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.1643318326
Short name T553
Test name
Test status
Simulation time 218558737 ps
CPU time 4.87 seconds
Started Jul 14 05:40:49 PM PDT 24
Finished Jul 14 05:40:54 PM PDT 24
Peak memory 215572 kb
Host smart-480c9bef-7650-4c76-848d-8a0b0c73a4b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643318326 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.1643318326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.1534779349
Short name T441
Test name
Test status
Simulation time 166873971949 ps
CPU time 1806.8 seconds
Started Jul 14 05:40:50 PM PDT 24
Finished Jul 14 06:10:57 PM PDT 24
Peak memory 388464 kb
Host smart-f668a517-c4dc-4b66-bba4-5e416cc2a099
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1534779349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.1534779349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.902896842
Short name T1070
Test name
Test status
Simulation time 178146384456 ps
CPU time 1386.03 seconds
Started Jul 14 05:40:52 PM PDT 24
Finished Jul 14 06:03:59 PM PDT 24
Peak memory 375944 kb
Host smart-ab226972-86a0-4055-aab7-120a54fdd4c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=902896842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.902896842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.1519738860
Short name T1018
Test name
Test status
Simulation time 72491253993 ps
CPU time 1369.8 seconds
Started Jul 14 05:40:52 PM PDT 24
Finished Jul 14 06:03:42 PM PDT 24
Peak memory 329704 kb
Host smart-e8e19105-a809-4ffe-9211-e38b5c7a955e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1519738860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.1519738860 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.2746182160
Short name T873
Test name
Test status
Simulation time 33426956395 ps
CPU time 820.61 seconds
Started Jul 14 05:40:50 PM PDT 24
Finished Jul 14 05:54:31 PM PDT 24
Peak memory 291704 kb
Host smart-47dfc3f8-c258-4b37-a9cb-75078a8791a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2746182160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.2746182160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.2733351409
Short name T984
Test name
Test status
Simulation time 169694930323 ps
CPU time 4841.71 seconds
Started Jul 14 05:40:51 PM PDT 24
Finished Jul 14 07:01:33 PM PDT 24
Peak memory 636760 kb
Host smart-1fff7188-4276-4760-93f4-c82909a91c64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2733351409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.2733351409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.1009619080
Short name T191
Test name
Test status
Simulation time 144837531012 ps
CPU time 3870.71 seconds
Started Jul 14 05:40:50 PM PDT 24
Finished Jul 14 06:45:22 PM PDT 24
Peak memory 558180 kb
Host smart-11303c42-c624-4940-aeba-ec3462b10b1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1009619080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.1009619080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1006064482
Short name T603
Test name
Test status
Simulation time 157392889 ps
CPU time 0.81 seconds
Started Jul 14 05:41:23 PM PDT 24
Finished Jul 14 05:41:24 PM PDT 24
Peak memory 205280 kb
Host smart-2e65675e-5908-4c5b-82ee-be0c002d256c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006064482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1006064482 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.3304721425
Short name T102
Test name
Test status
Simulation time 5495723680 ps
CPU time 124.96 seconds
Started Jul 14 05:41:15 PM PDT 24
Finished Jul 14 05:43:21 PM PDT 24
Peak memory 234492 kb
Host smart-3c0926dd-f2e2-4c96-8577-da4fcc1e6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304721425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3304721425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.3733653503
Short name T965
Test name
Test status
Simulation time 36611046676 ps
CPU time 875.26 seconds
Started Jul 14 05:41:00 PM PDT 24
Finished Jul 14 05:55:36 PM PDT 24
Peak memory 233104 kb
Host smart-091285bd-2baa-43c1-95d1-d05849d38543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733653503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.3733653503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.2794347078
Short name T1014
Test name
Test status
Simulation time 19626516489 ps
CPU time 138.13 seconds
Started Jul 14 05:41:15 PM PDT 24
Finished Jul 14 05:43:34 PM PDT 24
Peak memory 235664 kb
Host smart-77986e60-a64b-458c-aa24-687e6b84adbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794347078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2794347078 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.2592260250
Short name T773
Test name
Test status
Simulation time 8637969724 ps
CPU time 218.19 seconds
Started Jul 14 05:41:15 PM PDT 24
Finished Jul 14 05:44:54 PM PDT 24
Peak memory 242448 kb
Host smart-bc79f788-f79c-4a66-927d-06eb86a72478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592260250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2592260250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.909770716
Short name T831
Test name
Test status
Simulation time 4281656384 ps
CPU time 6.46 seconds
Started Jul 14 05:41:15 PM PDT 24
Finished Jul 14 05:41:21 PM PDT 24
Peak memory 207468 kb
Host smart-2590e2b6-da2e-41a3-a45b-8233ea836432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909770716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.909770716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.3177688922
Short name T82
Test name
Test status
Simulation time 901391024 ps
CPU time 9.19 seconds
Started Jul 14 05:41:24 PM PDT 24
Finished Jul 14 05:41:33 PM PDT 24
Peak memory 222004 kb
Host smart-e6adaa63-bc49-4147-99d7-c415325f8e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177688922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3177688922 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.924493997
Short name T969
Test name
Test status
Simulation time 147392387706 ps
CPU time 1612.9 seconds
Started Jul 14 05:41:01 PM PDT 24
Finished Jul 14 06:07:55 PM PDT 24
Peak memory 390396 kb
Host smart-23892731-2130-4a7f-a2f3-a3cec30605d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924493997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an
d_output.924493997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.4095863876
Short name T582
Test name
Test status
Simulation time 35690876523 ps
CPU time 139.07 seconds
Started Jul 14 05:41:02 PM PDT 24
Finished Jul 14 05:43:22 PM PDT 24
Peak memory 229256 kb
Host smart-a3ee87c3-4237-4fff-9086-6dc9a2ec4a9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095863876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.4095863876 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.2273017963
Short name T742
Test name
Test status
Simulation time 6466518322 ps
CPU time 51.86 seconds
Started Jul 14 05:41:01 PM PDT 24
Finished Jul 14 05:41:53 PM PDT 24
Peak memory 223820 kb
Host smart-beb1a66d-9ace-4638-93e2-80f3e46f2829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273017963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2273017963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.3829464377
Short name T38
Test name
Test status
Simulation time 13945182107 ps
CPU time 1153.38 seconds
Started Jul 14 05:41:24 PM PDT 24
Finished Jul 14 06:00:39 PM PDT 24
Peak memory 343444 kb
Host smart-1a6aedc7-2fa2-4878-b7e5-89e1fe14b1b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3829464377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3829464377 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1014307330
Short name T368
Test name
Test status
Simulation time 166048699 ps
CPU time 4.2 seconds
Started Jul 14 05:41:13 PM PDT 24
Finished Jul 14 05:41:17 PM PDT 24
Peak memory 215544 kb
Host smart-cfc399fe-4c0f-43f6-83d9-58ebc6dac696
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014307330 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1014307330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.3348443492
Short name T251
Test name
Test status
Simulation time 267587917 ps
CPU time 4.05 seconds
Started Jul 14 05:41:16 PM PDT 24
Finished Jul 14 05:41:20 PM PDT 24
Peak memory 215600 kb
Host smart-e73a98b6-173e-49e2-bf9b-8981ac11b89e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348443492 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.3348443492 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.3260406102
Short name T183
Test name
Test status
Simulation time 129367923958 ps
CPU time 1803.21 seconds
Started Jul 14 05:41:00 PM PDT 24
Finished Jul 14 06:11:05 PM PDT 24
Peak memory 390112 kb
Host smart-716b8189-257b-4644-81f9-1bd7d3f1cda6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3260406102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.3260406102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.78525975
Short name T181
Test name
Test status
Simulation time 38226184903 ps
CPU time 1651.16 seconds
Started Jul 14 05:41:00 PM PDT 24
Finished Jul 14 06:08:33 PM PDT 24
Peak memory 378464 kb
Host smart-1b22c749-d154-483c-a59b-04a53cf9802d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=78525975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.78525975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.2524890913
Short name T990
Test name
Test status
Simulation time 62912386741 ps
CPU time 1287.8 seconds
Started Jul 14 05:41:09 PM PDT 24
Finished Jul 14 06:02:37 PM PDT 24
Peak memory 332876 kb
Host smart-43c80cd0-a10d-43ce-9105-3f7fbf2641a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2524890913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.2524890913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.227670861
Short name T311
Test name
Test status
Simulation time 40043286573 ps
CPU time 855.89 seconds
Started Jul 14 05:41:08 PM PDT 24
Finished Jul 14 05:55:25 PM PDT 24
Peak memory 296248 kb
Host smart-a8471d71-0251-4a6b-8594-f32c7783a74b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=227670861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.227670861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.801510090
Short name T517
Test name
Test status
Simulation time 1916824686540 ps
CPU time 4676.23 seconds
Started Jul 14 05:41:13 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 653632 kb
Host smart-886bc2d5-a712-43f4-9812-df98d7c5a338
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=801510090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.801510090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.4084012874
Short name T919
Test name
Test status
Simulation time 43329012228 ps
CPU time 3337.62 seconds
Started Jul 14 05:41:13 PM PDT 24
Finished Jul 14 06:36:51 PM PDT 24
Peak memory 554128 kb
Host smart-ae723c70-96ec-46f4-939c-666774da7483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4084012874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.4084012874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.723419288
Short name T1068
Test name
Test status
Simulation time 15953492 ps
CPU time 0.78 seconds
Started Jul 14 05:41:45 PM PDT 24
Finished Jul 14 05:41:46 PM PDT 24
Peak memory 205292 kb
Host smart-f98307f6-ffca-4c0f-9ef1-de1b28b7d11e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723419288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.723419288 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.395880568
Short name T396
Test name
Test status
Simulation time 5644738388 ps
CPU time 114.52 seconds
Started Jul 14 05:41:44 PM PDT 24
Finished Jul 14 05:43:39 PM PDT 24
Peak memory 231092 kb
Host smart-6ba9041d-4107-456c-b666-8ef725be89f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395880568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.395880568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.1436619458
Short name T423
Test name
Test status
Simulation time 7267431902 ps
CPU time 187.26 seconds
Started Jul 14 05:41:24 PM PDT 24
Finished Jul 14 05:44:32 PM PDT 24
Peak memory 224484 kb
Host smart-d1597743-d65d-46ae-b4cc-52aef9524daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436619458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1436619458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.3669549435
Short name T687
Test name
Test status
Simulation time 349413789 ps
CPU time 8.48 seconds
Started Jul 14 05:41:45 PM PDT 24
Finished Jul 14 05:41:54 PM PDT 24
Peak memory 223736 kb
Host smart-b3324b3d-f5e5-41c0-8865-ae76c0d73c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669549435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3669549435 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.2365237175
Short name T332
Test name
Test status
Simulation time 4362285090 ps
CPU time 92.53 seconds
Started Jul 14 05:41:43 PM PDT 24
Finished Jul 14 05:43:16 PM PDT 24
Peak memory 236552 kb
Host smart-6c0128c2-66cc-4ce4-b0be-79179bbcd70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365237175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2365237175 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.3193089151
Short name T763
Test name
Test status
Simulation time 1171344595 ps
CPU time 3.3 seconds
Started Jul 14 05:41:46 PM PDT 24
Finished Jul 14 05:41:49 PM PDT 24
Peak memory 207284 kb
Host smart-d5d28beb-1f06-4e6f-8f19-368c4bfaf5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193089151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3193089151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.2317441770
Short name T58
Test name
Test status
Simulation time 44692945 ps
CPU time 1.25 seconds
Started Jul 14 05:41:47 PM PDT 24
Finished Jul 14 05:41:49 PM PDT 24
Peak memory 215520 kb
Host smart-1b485dc6-0a17-4265-96e4-408138af4e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317441770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2317441770 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.960454209
Short name T288
Test name
Test status
Simulation time 90464688584 ps
CPU time 1965.66 seconds
Started Jul 14 05:41:26 PM PDT 24
Finished Jul 14 06:14:12 PM PDT 24
Peak memory 439264 kb
Host smart-3e1883bd-fcfc-425e-be33-375e79bb359c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960454209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_an
d_output.960454209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.2448634546
Short name T693
Test name
Test status
Simulation time 34265053916 ps
CPU time 352.65 seconds
Started Jul 14 05:41:27 PM PDT 24
Finished Jul 14 05:47:20 PM PDT 24
Peak memory 244852 kb
Host smart-6c5aff46-5315-49e6-b693-8567eed051d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448634546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2448634546 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.1909287136
Short name T618
Test name
Test status
Simulation time 761527486 ps
CPU time 18.59 seconds
Started Jul 14 05:41:24 PM PDT 24
Finished Jul 14 05:41:43 PM PDT 24
Peak memory 223780 kb
Host smart-e0db131e-d352-4f33-9585-91d61e7165dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909287136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1909287136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.2861065744
Short name T378
Test name
Test status
Simulation time 5013270991 ps
CPU time 235.98 seconds
Started Jul 14 05:41:45 PM PDT 24
Finished Jul 14 05:45:42 PM PDT 24
Peak memory 281408 kb
Host smart-170f5e22-a1c2-4cd7-8c08-b349b3be309a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2861065744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2861065744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.3086503776
Short name T74
Test name
Test status
Simulation time 1088060358 ps
CPU time 4.93 seconds
Started Jul 14 05:41:32 PM PDT 24
Finished Jul 14 05:41:38 PM PDT 24
Peak memory 215688 kb
Host smart-af749030-a8b7-487c-9be1-2b9f493e4674
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086503776 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.3086503776 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2203273659
Short name T270
Test name
Test status
Simulation time 185223115 ps
CPU time 4.47 seconds
Started Jul 14 05:41:37 PM PDT 24
Finished Jul 14 05:41:42 PM PDT 24
Peak memory 215588 kb
Host smart-b36b7527-9534-4a35-b38d-c896db7f483c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203273659 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2203273659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.2188197003
Short name T899
Test name
Test status
Simulation time 19589020425 ps
CPU time 1680.8 seconds
Started Jul 14 05:41:25 PM PDT 24
Finished Jul 14 06:09:27 PM PDT 24
Peak memory 395616 kb
Host smart-7575bbc9-9ba7-4bc3-8a60-a0c890f9076b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2188197003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.2188197003 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.2456947579
Short name T572
Test name
Test status
Simulation time 35756099392 ps
CPU time 1482.93 seconds
Started Jul 14 05:41:25 PM PDT 24
Finished Jul 14 06:06:08 PM PDT 24
Peak memory 369704 kb
Host smart-2047dcfc-4e5b-462e-a60c-86388b9dc5db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2456947579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.2456947579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.2395501927
Short name T631
Test name
Test status
Simulation time 60694704121 ps
CPU time 1328.86 seconds
Started Jul 14 05:41:32 PM PDT 24
Finished Jul 14 06:03:42 PM PDT 24
Peak memory 334488 kb
Host smart-b38757ed-c9f6-4fa0-a236-29ac814ecbce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2395501927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.2395501927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.480497419
Short name T1060
Test name
Test status
Simulation time 33402641771 ps
CPU time 852.19 seconds
Started Jul 14 05:41:36 PM PDT 24
Finished Jul 14 05:55:48 PM PDT 24
Peak memory 293120 kb
Host smart-0d5abe40-e5a1-4143-be3f-eddc4203a565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=480497419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.480497419 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.552770654
Short name T428
Test name
Test status
Simulation time 213322435638 ps
CPU time 3955.31 seconds
Started Jul 14 05:41:33 PM PDT 24
Finished Jul 14 06:47:29 PM PDT 24
Peak memory 656516 kb
Host smart-58a4ed73-5ea5-4f40-bf6d-5d45e951082a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=552770654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.552770654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.1772743695
Short name T540
Test name
Test status
Simulation time 206882253461 ps
CPU time 3391.32 seconds
Started Jul 14 05:41:33 PM PDT 24
Finished Jul 14 06:38:05 PM PDT 24
Peak memory 564528 kb
Host smart-6bbfef79-252a-4913-b736-fc467b470899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1772743695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1772743695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.4088004089
Short name T388
Test name
Test status
Simulation time 69829686 ps
CPU time 0.89 seconds
Started Jul 14 05:42:03 PM PDT 24
Finished Jul 14 05:42:04 PM PDT 24
Peak memory 205272 kb
Host smart-4635e08a-0a3b-4966-872a-548ce989cdad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088004089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.4088004089 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.4103245528
Short name T714
Test name
Test status
Simulation time 2938353796 ps
CPU time 63.23 seconds
Started Jul 14 05:41:54 PM PDT 24
Finished Jul 14 05:42:57 PM PDT 24
Peak memory 223980 kb
Host smart-a2b5c965-145a-4f5a-b469-4e3b6f7158b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103245528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.4103245528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.2621512551
Short name T713
Test name
Test status
Simulation time 22020683541 ps
CPU time 662.72 seconds
Started Jul 14 05:41:45 PM PDT 24
Finished Jul 14 05:52:48 PM PDT 24
Peak memory 231268 kb
Host smart-915c3c38-8d35-4212-81be-b155f9cd9df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621512551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2621512551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2755498986
Short name T630
Test name
Test status
Simulation time 2093400185 ps
CPU time 24.8 seconds
Started Jul 14 05:41:59 PM PDT 24
Finished Jul 14 05:42:25 PM PDT 24
Peak memory 220148 kb
Host smart-644b4c09-f96c-4065-a8f6-b01a8078c734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755498986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2755498986 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.1285641060
Short name T1084
Test name
Test status
Simulation time 1257950716 ps
CPU time 8.66 seconds
Started Jul 14 05:42:02 PM PDT 24
Finished Jul 14 05:42:11 PM PDT 24
Peak memory 220300 kb
Host smart-c062eb23-5c6c-45d1-b401-e109465cab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285641060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1285641060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.138689157
Short name T913
Test name
Test status
Simulation time 6858655814 ps
CPU time 8.53 seconds
Started Jul 14 05:42:02 PM PDT 24
Finished Jul 14 05:42:11 PM PDT 24
Peak memory 207276 kb
Host smart-45b61547-0cc8-4736-91fa-0c4122a05605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138689157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.138689157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.564659532
Short name T442
Test name
Test status
Simulation time 1720444053 ps
CPU time 21.31 seconds
Started Jul 14 05:42:04 PM PDT 24
Finished Jul 14 05:42:25 PM PDT 24
Peak memory 228560 kb
Host smart-00317718-f18b-42dc-b97b-014734034c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564659532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.564659532 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.3977548819
Short name T233
Test name
Test status
Simulation time 25836816467 ps
CPU time 2147.29 seconds
Started Jul 14 05:41:45 PM PDT 24
Finished Jul 14 06:17:33 PM PDT 24
Peak memory 462728 kb
Host smart-ebb0967c-ed3f-450a-a029-bece12afc518
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977548819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.3977548819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.1196153579
Short name T543
Test name
Test status
Simulation time 21264101554 ps
CPU time 106.03 seconds
Started Jul 14 05:41:43 PM PDT 24
Finished Jul 14 05:43:29 PM PDT 24
Peak memory 227968 kb
Host smart-55103298-d39d-4910-906c-eb766c7ad977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196153579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1196153579 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1678625989
Short name T876
Test name
Test status
Simulation time 1274602986 ps
CPU time 31.07 seconds
Started Jul 14 05:41:44 PM PDT 24
Finished Jul 14 05:42:15 PM PDT 24
Peak memory 217712 kb
Host smart-77c059b2-8cd8-4e4d-a542-964c20eae325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678625989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1678625989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.1056514792
Short name T403
Test name
Test status
Simulation time 181845272 ps
CPU time 4.62 seconds
Started Jul 14 05:41:52 PM PDT 24
Finished Jul 14 05:41:57 PM PDT 24
Peak memory 215596 kb
Host smart-d220405b-2ed0-4fb9-a47f-51657b01d1f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056514792 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.1056514792 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.626575167
Short name T490
Test name
Test status
Simulation time 249869754 ps
CPU time 5.15 seconds
Started Jul 14 05:41:52 PM PDT 24
Finished Jul 14 05:41:57 PM PDT 24
Peak memory 215508 kb
Host smart-1c22a850-65b1-43b4-b01a-17b1c11c5922
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626575167 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.kmac_test_vectors_kmac_xof.626575167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.3586728720
Short name T1047
Test name
Test status
Simulation time 66616778025 ps
CPU time 1738.22 seconds
Started Jul 14 05:41:46 PM PDT 24
Finished Jul 14 06:10:45 PM PDT 24
Peak memory 389672 kb
Host smart-2ca47746-0e0f-43c7-accf-8661e13cff62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3586728720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.3586728720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.443141170
Short name T240
Test name
Test status
Simulation time 125801542040 ps
CPU time 1696.07 seconds
Started Jul 14 05:41:43 PM PDT 24
Finished Jul 14 06:10:00 PM PDT 24
Peak memory 370144 kb
Host smart-c4c88aef-9b06-4428-afcc-788e9e77c673
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=443141170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.443141170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3108352356
Short name T786
Test name
Test status
Simulation time 48542187660 ps
CPU time 1363.22 seconds
Started Jul 14 05:41:53 PM PDT 24
Finished Jul 14 06:04:37 PM PDT 24
Peak memory 332380 kb
Host smart-ee838276-a438-4594-b5d8-9dd35b022e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3108352356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3108352356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.221254626
Short name T613
Test name
Test status
Simulation time 20286994759 ps
CPU time 833.26 seconds
Started Jul 14 05:41:51 PM PDT 24
Finished Jul 14 05:55:45 PM PDT 24
Peak memory 299628 kb
Host smart-1f905c1f-5e5f-48e9-a0eb-155b84789bbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=221254626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.221254626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.4161222465
Short name T797
Test name
Test status
Simulation time 896333008036 ps
CPU time 5023.23 seconds
Started Jul 14 05:41:53 PM PDT 24
Finished Jul 14 07:05:38 PM PDT 24
Peak memory 640316 kb
Host smart-68547f95-ee10-484d-a9bb-b98aad71c3dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4161222465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.4161222465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1119159950
Short name T158
Test name
Test status
Simulation time 43221657598 ps
CPU time 3384.89 seconds
Started Jul 14 05:41:54 PM PDT 24
Finished Jul 14 06:38:20 PM PDT 24
Peak memory 560008 kb
Host smart-a5cd5540-a9e0-49bd-9ff6-bee9800e95f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1119159950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1119159950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3307938331
Short name T72
Test name
Test status
Simulation time 23931064 ps
CPU time 0.77 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 05:34:27 PM PDT 24
Peak memory 205260 kb
Host smart-af129f84-4aa2-4e64-90e5-3988ea1bd5eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307938331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3307938331 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.3596063931
Short name T305
Test name
Test status
Simulation time 17561012632 ps
CPU time 334.7 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 05:39:53 PM PDT 24
Peak memory 246304 kb
Host smart-b7b33e5a-6c6a-415c-8c2a-313467e88af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596063931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3596063931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.1518032164
Short name T733
Test name
Test status
Simulation time 8825567072 ps
CPU time 154.95 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 05:36:54 PM PDT 24
Peak memory 231368 kb
Host smart-bb49fbfe-c0ec-43e7-b03d-ecd3829f1a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518032164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.1518032164 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.3159911716
Short name T440
Test name
Test status
Simulation time 6884572134 ps
CPU time 596.7 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 05:44:15 PM PDT 24
Peak memory 230548 kb
Host smart-fd008bea-89a8-49ac-8f3a-e75eadf08fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159911716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3159911716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.3658927226
Short name T862
Test name
Test status
Simulation time 893902460 ps
CPU time 16.66 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:34:47 PM PDT 24
Peak memory 218628 kb
Host smart-2362aabd-d830-4042-9274-9a3b9ec4577a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658927226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3658927226 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.1688213651
Short name T376
Test name
Test status
Simulation time 427976473 ps
CPU time 33.3 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 05:35:00 PM PDT 24
Peak memory 220888 kb
Host smart-4b5e2f4c-9dee-413b-940a-f9a1f73d907d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1688213651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1688213651 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1027348043
Short name T42
Test name
Test status
Simulation time 1422792256 ps
CPU time 17.77 seconds
Started Jul 14 05:34:23 PM PDT 24
Finished Jul 14 05:34:41 PM PDT 24
Peak memory 216600 kb
Host smart-ad950a63-e935-43dc-97c0-293de156d1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027348043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1027348043 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.1488321579
Short name T504
Test name
Test status
Simulation time 23583054575 ps
CPU time 237.99 seconds
Started Jul 14 05:34:25 PM PDT 24
Finished Jul 14 05:38:23 PM PDT 24
Peak memory 243572 kb
Host smart-a989c8e1-9d7c-4d61-bcfa-46c638dd470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488321579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1488321579 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_key_error.2277396983
Short name T808
Test name
Test status
Simulation time 1729196436 ps
CPU time 3.33 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:34:33 PM PDT 24
Peak memory 215380 kb
Host smart-8c05d77a-ed65-4740-9273-0fef881904d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277396983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2277396983 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1672526575
Short name T539
Test name
Test status
Simulation time 39492875 ps
CPU time 1.31 seconds
Started Jul 14 05:34:24 PM PDT 24
Finished Jul 14 05:34:26 PM PDT 24
Peak memory 215488 kb
Host smart-f05438da-abec-48a4-8804-de23e7f898ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672526575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1672526575 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.1922107588
Short name T295
Test name
Test status
Simulation time 59114210646 ps
CPU time 1811.1 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 06:04:30 PM PDT 24
Peak memory 378596 kb
Host smart-4697410f-13b8-4a45-a8fa-1e7d900bdb06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922107588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.1922107588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.1565185953
Short name T584
Test name
Test status
Simulation time 9676277640 ps
CPU time 52.88 seconds
Started Jul 14 05:34:24 PM PDT 24
Finished Jul 14 05:35:17 PM PDT 24
Peak memory 224068 kb
Host smart-2631464e-131f-4521-b655-bbe185a44fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565185953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1565185953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sideload.1593254013
Short name T447
Test name
Test status
Simulation time 486036961 ps
CPU time 35.82 seconds
Started Jul 14 05:34:17 PM PDT 24
Finished Jul 14 05:34:54 PM PDT 24
Peak memory 219892 kb
Host smart-e57029cc-eab4-4fd5-8bed-853a67d92d34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593254013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1593254013 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.2281278866
Short name T306
Test name
Test status
Simulation time 2824514854 ps
CPU time 30.27 seconds
Started Jul 14 05:34:19 PM PDT 24
Finished Jul 14 05:34:50 PM PDT 24
Peak memory 221856 kb
Host smart-37de23cc-5319-4d56-aa23-bef5aa7a418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281278866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2281278866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1248783922
Short name T921
Test name
Test status
Simulation time 1223394776 ps
CPU time 32.03 seconds
Started Jul 14 05:34:23 PM PDT 24
Finished Jul 14 05:34:56 PM PDT 24
Peak memory 235180 kb
Host smart-302be833-dd32-4e85-83dd-40de4d41660f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1248783922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1248783922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.2841413538
Short name T588
Test name
Test status
Simulation time 360987565 ps
CPU time 3.96 seconds
Started Jul 14 05:34:19 PM PDT 24
Finished Jul 14 05:34:23 PM PDT 24
Peak memory 215672 kb
Host smart-8ac83df5-0b17-4ad9-a806-f61381aff109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841413538 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.2841413538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.2107620736
Short name T271
Test name
Test status
Simulation time 1001348437 ps
CPU time 5.09 seconds
Started Jul 14 05:34:19 PM PDT 24
Finished Jul 14 05:34:25 PM PDT 24
Peak memory 215576 kb
Host smart-dcec3ae0-bf58-4ce9-bda5-ffeccace79da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107620736 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2107620736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.3752049438
Short name T820
Test name
Test status
Simulation time 73957008903 ps
CPU time 1488.13 seconds
Started Jul 14 05:34:16 PM PDT 24
Finished Jul 14 05:59:05 PM PDT 24
Peak memory 378840 kb
Host smart-7d1d5880-86b8-46ee-bf40-e2dcb8ac616a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3752049438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3752049438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1173980851
Short name T224
Test name
Test status
Simulation time 37044821793 ps
CPU time 1495.09 seconds
Started Jul 14 05:34:17 PM PDT 24
Finished Jul 14 05:59:13 PM PDT 24
Peak memory 374024 kb
Host smart-61fb2896-e20f-4022-ad13-3cab85a4d78d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1173980851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1173980851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2003315258
Short name T576
Test name
Test status
Simulation time 62007081386 ps
CPU time 1215.43 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 05:54:34 PM PDT 24
Peak memory 328872 kb
Host smart-8957e0e5-d040-4824-94f6-6cb48793198e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2003315258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2003315258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.708630392
Short name T319
Test name
Test status
Simulation time 82452398538 ps
CPU time 897.37 seconds
Started Jul 14 05:34:17 PM PDT 24
Finished Jul 14 05:49:15 PM PDT 24
Peak memory 290080 kb
Host smart-b9d6c811-30f8-4647-8406-1b4fb87ac547
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=708630392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.708630392 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.4172646387
Short name T176
Test name
Test status
Simulation time 543559744559 ps
CPU time 5121.79 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 06:59:41 PM PDT 24
Peak memory 666284 kb
Host smart-33641f54-ad68-451f-b762-2f074875ac80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4172646387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.4172646387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.600506636
Short name T1021
Test name
Test status
Simulation time 43656456638 ps
CPU time 3491.77 seconds
Started Jul 14 05:34:18 PM PDT 24
Finished Jul 14 06:32:31 PM PDT 24
Peak memory 549808 kb
Host smart-ac867d4d-2214-4f6d-9071-c8767db80bec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=600506636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.600506636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.809151614
Short name T734
Test name
Test status
Simulation time 16205529 ps
CPU time 0.78 seconds
Started Jul 14 05:42:36 PM PDT 24
Finished Jul 14 05:42:37 PM PDT 24
Peak memory 205280 kb
Host smart-7ce77909-1d6b-43d1-a336-a12f7c3e1e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809151614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.809151614 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3390845410
Short name T419
Test name
Test status
Simulation time 9633038880 ps
CPU time 51.27 seconds
Started Jul 14 05:42:30 PM PDT 24
Finished Jul 14 05:43:22 PM PDT 24
Peak memory 224296 kb
Host smart-1524a1ae-657b-495f-b18b-c34ded04f78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390845410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3390845410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.815409413
Short name T36
Test name
Test status
Simulation time 12317349770 ps
CPU time 570.37 seconds
Started Jul 14 05:42:19 PM PDT 24
Finished Jul 14 05:51:50 PM PDT 24
Peak memory 230620 kb
Host smart-24beb5f7-95db-4fa3-bbea-6c15b0ae99be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815409413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.815409413 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.822191917
Short name T229
Test name
Test status
Simulation time 6272823322 ps
CPU time 93.31 seconds
Started Jul 14 05:42:27 PM PDT 24
Finished Jul 14 05:44:00 PM PDT 24
Peak memory 227848 kb
Host smart-fa99f463-15fe-49c0-b059-7904d20820cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822191917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.822191917 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.467566821
Short name T26
Test name
Test status
Simulation time 17027511682 ps
CPU time 358.82 seconds
Started Jul 14 05:42:28 PM PDT 24
Finished Jul 14 05:48:27 PM PDT 24
Peak memory 256608 kb
Host smart-09b80c01-a540-49dd-bbad-f2177f0c2dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467566821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.467566821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.408015631
Short name T454
Test name
Test status
Simulation time 4471447576 ps
CPU time 6.31 seconds
Started Jul 14 05:42:31 PM PDT 24
Finished Jul 14 05:42:38 PM PDT 24
Peak memory 215552 kb
Host smart-2cba8b35-b8e8-4d95-8c73-72cbfbad7f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408015631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.408015631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.1805680337
Short name T61
Test name
Test status
Simulation time 32948076 ps
CPU time 1.13 seconds
Started Jul 14 05:42:31 PM PDT 24
Finished Jul 14 05:42:33 PM PDT 24
Peak memory 215464 kb
Host smart-ae4defcd-2556-4bac-8953-69eb3ab58c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805680337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1805680337 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.1990307713
Short name T76
Test name
Test status
Simulation time 105769450875 ps
CPU time 523.94 seconds
Started Jul 14 05:42:11 PM PDT 24
Finished Jul 14 05:50:55 PM PDT 24
Peak memory 267120 kb
Host smart-87236270-fd8d-4212-ba30-4dd603dfda65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990307713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.1990307713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.1969089831
Short name T264
Test name
Test status
Simulation time 17177446568 ps
CPU time 304.69 seconds
Started Jul 14 05:42:11 PM PDT 24
Finished Jul 14 05:47:16 PM PDT 24
Peak memory 247244 kb
Host smart-217a8e6d-49f2-481f-9b9b-55d89861f761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969089831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1969089831 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.1580835
Short name T725
Test name
Test status
Simulation time 394118854 ps
CPU time 4.84 seconds
Started Jul 14 05:42:02 PM PDT 24
Finished Jul 14 05:42:07 PM PDT 24
Peak memory 219756 kb
Host smart-e65a1b6e-166d-4555-a8ac-f815eaca81a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1580835 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.796535744
Short name T749
Test name
Test status
Simulation time 11302652086 ps
CPU time 661.27 seconds
Started Jul 14 05:42:30 PM PDT 24
Finished Jul 14 05:53:31 PM PDT 24
Peak memory 330324 kb
Host smart-433cc5a5-6267-435b-96d5-85f4f7c32c34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=796535744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.796535744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.1461830083
Short name T872
Test name
Test status
Simulation time 173373609 ps
CPU time 4.03 seconds
Started Jul 14 05:42:19 PM PDT 24
Finished Jul 14 05:42:23 PM PDT 24
Peak memory 215552 kb
Host smart-8dbae2f2-94de-48f8-8111-dd0996fd8579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461830083 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.1461830083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.2250019819
Short name T564
Test name
Test status
Simulation time 68886662 ps
CPU time 3.52 seconds
Started Jul 14 05:42:27 PM PDT 24
Finished Jul 14 05:42:31 PM PDT 24
Peak memory 208748 kb
Host smart-3c94b44a-5b78-4f0a-b5c2-9f6bddce3252
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250019819 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.2250019819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.2945387180
Short name T518
Test name
Test status
Simulation time 64579581482 ps
CPU time 1798.72 seconds
Started Jul 14 05:42:19 PM PDT 24
Finished Jul 14 06:12:18 PM PDT 24
Peak memory 386408 kb
Host smart-20993a88-03c8-408f-a089-1bac01d5e580
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2945387180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.2945387180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.866303545
Short name T507
Test name
Test status
Simulation time 17765615114 ps
CPU time 1515.42 seconds
Started Jul 14 05:42:18 PM PDT 24
Finished Jul 14 06:07:34 PM PDT 24
Peak memory 367984 kb
Host smart-cf2f5d2a-b42c-43d1-8306-082295b5c0f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=866303545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.866303545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.859653144
Short name T796
Test name
Test status
Simulation time 72378601366 ps
CPU time 1429.59 seconds
Started Jul 14 05:42:19 PM PDT 24
Finished Jul 14 06:06:09 PM PDT 24
Peak memory 332168 kb
Host smart-48711eb8-0826-42cd-8fa4-3b134d95ad0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=859653144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.859653144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.2744579529
Short name T601
Test name
Test status
Simulation time 369264201017 ps
CPU time 1002.44 seconds
Started Jul 14 05:42:19 PM PDT 24
Finished Jul 14 05:59:02 PM PDT 24
Peak memory 287144 kb
Host smart-1c333d29-a921-4ebb-a4f8-715330bb30f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2744579529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.2744579529 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.2776974217
Short name T399
Test name
Test status
Simulation time 517744881680 ps
CPU time 4541.43 seconds
Started Jul 14 05:42:17 PM PDT 24
Finished Jul 14 06:57:59 PM PDT 24
Peak memory 643820 kb
Host smart-d717f526-66bc-4d46-b8c6-fc95a2713948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2776974217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.2776974217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.3666869592
Short name T765
Test name
Test status
Simulation time 604166029220 ps
CPU time 4047.42 seconds
Started Jul 14 05:42:21 PM PDT 24
Finished Jul 14 06:49:49 PM PDT 24
Peak memory 559224 kb
Host smart-6ffdab72-1bbb-4d53-b660-6a4c59b73b83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3666869592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3666869592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.3420409884
Short name T1001
Test name
Test status
Simulation time 39215596 ps
CPU time 0.74 seconds
Started Jul 14 05:42:59 PM PDT 24
Finished Jul 14 05:43:01 PM PDT 24
Peak memory 205276 kb
Host smart-56f65bb5-81aa-4445-a387-3c369afa83e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420409884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3420409884 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2241451703
Short name T1077
Test name
Test status
Simulation time 4052231468 ps
CPU time 207.33 seconds
Started Jul 14 05:42:53 PM PDT 24
Finished Jul 14 05:46:21 PM PDT 24
Peak memory 240992 kb
Host smart-4af1cfe6-3cf7-42f8-aa77-24cbbc8d54bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241451703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2241451703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.1887221223
Short name T409
Test name
Test status
Simulation time 721917565 ps
CPU time 60.09 seconds
Started Jul 14 05:42:34 PM PDT 24
Finished Jul 14 05:43:34 PM PDT 24
Peak memory 223752 kb
Host smart-33220729-c195-4cfb-b66a-c45100b5f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887221223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.1887221223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.2346720214
Short name T751
Test name
Test status
Simulation time 3466541881 ps
CPU time 95.32 seconds
Started Jul 14 05:42:53 PM PDT 24
Finished Jul 14 05:44:29 PM PDT 24
Peak memory 229500 kb
Host smart-270c876d-fa06-4cb2-ac28-2ae98060b842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346720214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2346720214 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.208367364
Short name T968
Test name
Test status
Simulation time 48335303757 ps
CPU time 357.81 seconds
Started Jul 14 05:42:52 PM PDT 24
Finished Jul 14 05:48:50 PM PDT 24
Peak memory 249660 kb
Host smart-e7bbf521-4e07-4fc6-849c-dc49879e9558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208367364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.208367364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.3613100132
Short name T418
Test name
Test status
Simulation time 9134110734 ps
CPU time 9.92 seconds
Started Jul 14 05:42:51 PM PDT 24
Finished Jul 14 05:43:02 PM PDT 24
Peak memory 215592 kb
Host smart-661120f9-0914-45e6-9f55-3e756dcb63b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613100132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3613100132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.1010749315
Short name T1044
Test name
Test status
Simulation time 47087968 ps
CPU time 1.31 seconds
Started Jul 14 05:42:53 PM PDT 24
Finished Jul 14 05:42:55 PM PDT 24
Peak memory 215460 kb
Host smart-f247f1cd-c60e-4ab8-801c-fb17eb7fdc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010749315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1010749315 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.3507936673
Short name T272
Test name
Test status
Simulation time 65985179417 ps
CPU time 1830.38 seconds
Started Jul 14 05:42:33 PM PDT 24
Finished Jul 14 06:13:04 PM PDT 24
Peak memory 409116 kb
Host smart-0f4f1bcf-11ac-44df-96cf-6d55b59f36c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507936673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.3507936673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.571324065
Short name T947
Test name
Test status
Simulation time 1228545883 ps
CPU time 10.63 seconds
Started Jul 14 05:42:38 PM PDT 24
Finished Jul 14 05:42:49 PM PDT 24
Peak memory 220128 kb
Host smart-03818a7b-d82d-447e-aa4a-8ed7112f8fd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571324065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.571324065 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.2464148579
Short name T997
Test name
Test status
Simulation time 2596195804 ps
CPU time 42.52 seconds
Started Jul 14 05:42:38 PM PDT 24
Finished Jul 14 05:43:21 PM PDT 24
Peak memory 218836 kb
Host smart-772b4f51-ff5a-4df1-af44-2c7f20606831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464148579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2464148579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.925954128
Short name T87
Test name
Test status
Simulation time 87009337062 ps
CPU time 438.15 seconds
Started Jul 14 05:43:01 PM PDT 24
Finished Jul 14 05:50:19 PM PDT 24
Peak memory 286644 kb
Host smart-1f04ddb3-149a-4e0e-b41e-68eabe4028e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=925954128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.925954128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.2792505859
Short name T467
Test name
Test status
Simulation time 645086500 ps
CPU time 5 seconds
Started Jul 14 05:42:44 PM PDT 24
Finished Jul 14 05:42:50 PM PDT 24
Peak memory 208652 kb
Host smart-a9b323bf-55ae-4693-bf0f-d180f7976fdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792505859 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.2792505859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.3253569668
Short name T665
Test name
Test status
Simulation time 167284045 ps
CPU time 4.11 seconds
Started Jul 14 05:42:54 PM PDT 24
Finished Jul 14 05:42:59 PM PDT 24
Peak memory 215588 kb
Host smart-1a50cbf5-25a9-44eb-9493-09b4768f4e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253569668 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.3253569668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.3978236784
Short name T719
Test name
Test status
Simulation time 64163565811 ps
CPU time 1866.37 seconds
Started Jul 14 05:42:35 PM PDT 24
Finished Jul 14 06:13:42 PM PDT 24
Peak memory 387696 kb
Host smart-f1e2b839-741f-4f5b-ba0a-2c7daf611f24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3978236784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.3978236784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.3974760788
Short name T1037
Test name
Test status
Simulation time 257133186590 ps
CPU time 1563.52 seconds
Started Jul 14 05:42:33 PM PDT 24
Finished Jul 14 06:08:37 PM PDT 24
Peak memory 377468 kb
Host smart-f358915e-1dfb-4f06-a790-9e8b51a54c46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3974760788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3974760788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.2132410278
Short name T895
Test name
Test status
Simulation time 167898676930 ps
CPU time 1297.56 seconds
Started Jul 14 05:42:37 PM PDT 24
Finished Jul 14 06:04:15 PM PDT 24
Peak memory 334764 kb
Host smart-6e27647d-72f0-4816-90ff-98fb38c72729
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2132410278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2132410278 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.1137536626
Short name T465
Test name
Test status
Simulation time 52640686943 ps
CPU time 792.36 seconds
Started Jul 14 05:42:36 PM PDT 24
Finished Jul 14 05:55:49 PM PDT 24
Peak memory 294524 kb
Host smart-8b620944-8cb8-4daf-b606-b31f90be8a10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1137536626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1137536626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.2725305325
Short name T1002
Test name
Test status
Simulation time 389106476031 ps
CPU time 4653.73 seconds
Started Jul 14 05:42:34 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 646620 kb
Host smart-fcd19fb4-191a-4db8-a706-c4fd67b987dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2725305325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.2725305325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2815267271
Short name T474
Test name
Test status
Simulation time 42851168300 ps
CPU time 3278.37 seconds
Started Jul 14 05:42:44 PM PDT 24
Finished Jul 14 06:37:23 PM PDT 24
Peak memory 552420 kb
Host smart-dde12621-f973-4f94-a5e8-f11e011e2f94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2815267271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2815267271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.4033787311
Short name T816
Test name
Test status
Simulation time 31584650 ps
CPU time 0.9 seconds
Started Jul 14 05:43:28 PM PDT 24
Finished Jul 14 05:43:30 PM PDT 24
Peak memory 205192 kb
Host smart-8f2cda9c-d27d-495d-81f7-5bf6dbe72106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033787311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.4033787311 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2547351052
Short name T150
Test name
Test status
Simulation time 2281596118 ps
CPU time 97.05 seconds
Started Jul 14 05:43:25 PM PDT 24
Finished Jul 14 05:45:02 PM PDT 24
Peak memory 231512 kb
Host smart-a09aa34d-44bc-4221-b91c-e3c720874e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547351052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2547351052 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.4288135062
Short name T704
Test name
Test status
Simulation time 51657401106 ps
CPU time 93.3 seconds
Started Jul 14 05:43:02 PM PDT 24
Finished Jul 14 05:44:36 PM PDT 24
Peak memory 223876 kb
Host smart-dadc40e0-ed2c-4aec-bdff-e0d0254e54c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288135062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.4288135062 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.1275432246
Short name T800
Test name
Test status
Simulation time 23970766575 ps
CPU time 181.76 seconds
Started Jul 14 05:43:21 PM PDT 24
Finished Jul 14 05:46:24 PM PDT 24
Peak memory 236152 kb
Host smart-7a033942-c46e-4488-9b4d-d64f485e3c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275432246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1275432246 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.942525108
Short name T29
Test name
Test status
Simulation time 17017744768 ps
CPU time 338.34 seconds
Started Jul 14 05:43:25 PM PDT 24
Finished Jul 14 05:49:04 PM PDT 24
Peak memory 256576 kb
Host smart-4fe2203d-7a0e-48be-bd76-d48ba262f0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942525108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.942525108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.450037022
Short name T840
Test name
Test status
Simulation time 291062474 ps
CPU time 2.03 seconds
Started Jul 14 05:43:28 PM PDT 24
Finished Jul 14 05:43:30 PM PDT 24
Peak memory 207188 kb
Host smart-b3ce24d6-38a0-49f2-8ebc-346b4f83c3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450037022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.450037022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.696012974
Short name T768
Test name
Test status
Simulation time 63299034 ps
CPU time 1.3 seconds
Started Jul 14 05:43:30 PM PDT 24
Finished Jul 14 05:43:32 PM PDT 24
Peak memory 219820 kb
Host smart-55e1b10f-649d-4fe3-8eb5-3b50f3e37cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696012974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.696012974 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.4033709661
Short name T835
Test name
Test status
Simulation time 14012596315 ps
CPU time 1234.31 seconds
Started Jul 14 05:42:59 PM PDT 24
Finished Jul 14 06:03:34 PM PDT 24
Peak memory 352964 kb
Host smart-06b78680-75b0-4417-81e5-91f7af12911d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033709661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.4033709661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.3325946249
Short name T437
Test name
Test status
Simulation time 1435914222 ps
CPU time 119.11 seconds
Started Jul 14 05:42:59 PM PDT 24
Finished Jul 14 05:44:58 PM PDT 24
Peak memory 229004 kb
Host smart-4e3a7ada-017d-4a1f-8de9-64e4fd56f7d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325946249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3325946249 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1801346335
Short name T832
Test name
Test status
Simulation time 1753939710 ps
CPU time 36.86 seconds
Started Jul 14 05:43:01 PM PDT 24
Finished Jul 14 05:43:38 PM PDT 24
Peak memory 218692 kb
Host smart-6aad4b31-21bf-49de-86e4-2ac70dcfeb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801346335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1801346335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.2754762765
Short name T1031
Test name
Test status
Simulation time 97694873566 ps
CPU time 618.65 seconds
Started Jul 14 05:43:29 PM PDT 24
Finished Jul 14 05:53:48 PM PDT 24
Peak memory 302804 kb
Host smart-06fc817b-462c-4ba0-93bd-b2a3ac400c6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2754762765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2754762765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.4009358640
Short name T799
Test name
Test status
Simulation time 67367921 ps
CPU time 3.77 seconds
Started Jul 14 05:43:14 PM PDT 24
Finished Jul 14 05:43:18 PM PDT 24
Peak memory 215676 kb
Host smart-20de2f44-7cf3-45a2-bcbe-181a69c6b96c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009358640 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.4009358640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.561833857
Short name T277
Test name
Test status
Simulation time 358620358 ps
CPU time 4.14 seconds
Started Jul 14 05:43:13 PM PDT 24
Finished Jul 14 05:43:18 PM PDT 24
Peak memory 215576 kb
Host smart-98a1a89f-88c1-4042-b36b-30e3b71a7c2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561833857 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.kmac_test_vectors_kmac_xof.561833857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.884147183
Short name T700
Test name
Test status
Simulation time 65553814963 ps
CPU time 1781.18 seconds
Started Jul 14 05:43:10 PM PDT 24
Finished Jul 14 06:12:52 PM PDT 24
Peak memory 395496 kb
Host smart-d4cb6399-427b-48b8-a398-a16885d64acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=884147183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.884147183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.1788972561
Short name T670
Test name
Test status
Simulation time 18400431251 ps
CPU time 1609.39 seconds
Started Jul 14 05:43:07 PM PDT 24
Finished Jul 14 06:09:57 PM PDT 24
Peak memory 375828 kb
Host smart-8b94c20e-2ee8-4e72-94ec-7326a0066baa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1788972561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.1788972561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.1693030707
Short name T817
Test name
Test status
Simulation time 253421415026 ps
CPU time 1430.39 seconds
Started Jul 14 05:43:09 PM PDT 24
Finished Jul 14 06:07:00 PM PDT 24
Peak memory 334396 kb
Host smart-da7c97c9-7c30-40c0-9b15-40d42ce60c3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1693030707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.1693030707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.2681187727
Short name T1008
Test name
Test status
Simulation time 33213514898 ps
CPU time 919.73 seconds
Started Jul 14 05:43:08 PM PDT 24
Finished Jul 14 05:58:29 PM PDT 24
Peak memory 294460 kb
Host smart-6bddd9a6-1f92-442b-b761-b2a6fdee2357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2681187727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.2681187727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.4028282831
Short name T193
Test name
Test status
Simulation time 53304858952 ps
CPU time 4063.11 seconds
Started Jul 14 05:43:08 PM PDT 24
Finished Jul 14 06:50:52 PM PDT 24
Peak memory 656552 kb
Host smart-fd9ee0b3-3850-4a46-9430-0c6f15fadc49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4028282831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.4028282831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.2854992333
Short name T639
Test name
Test status
Simulation time 225479551206 ps
CPU time 4360.38 seconds
Started Jul 14 05:43:16 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 559836 kb
Host smart-93a743bd-47b8-47ba-b8e4-59b20712a02e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2854992333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.2854992333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.3729728365
Short name T1005
Test name
Test status
Simulation time 35210847 ps
CPU time 0.81 seconds
Started Jul 14 05:43:59 PM PDT 24
Finished Jul 14 05:44:00 PM PDT 24
Peak memory 205156 kb
Host smart-c0ec038a-c13d-4cae-be00-87b0a3176f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729728365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3729728365 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.416570764
Short name T196
Test name
Test status
Simulation time 916919007 ps
CPU time 34.79 seconds
Started Jul 14 05:43:51 PM PDT 24
Finished Jul 14 05:44:26 PM PDT 24
Peak memory 221300 kb
Host smart-17c024f9-ed7d-4250-a40e-35d7591cd794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416570764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.416570764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.406924085
Short name T141
Test name
Test status
Simulation time 65854662003 ps
CPU time 424.58 seconds
Started Jul 14 05:43:36 PM PDT 24
Finished Jul 14 05:50:41 PM PDT 24
Peak memory 227448 kb
Host smart-6d305d54-6611-45c0-b979-d6acff6e2d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406924085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.406924085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.1139011785
Short name T1039
Test name
Test status
Simulation time 6065263107 ps
CPU time 57.58 seconds
Started Jul 14 05:43:59 PM PDT 24
Finished Jul 14 05:44:57 PM PDT 24
Peak memory 225228 kb
Host smart-65c52de8-1229-414f-a64b-39d71cc5ecb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139011785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1139011785 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.2853779559
Short name T559
Test name
Test status
Simulation time 38970624460 ps
CPU time 191.97 seconds
Started Jul 14 05:43:57 PM PDT 24
Finished Jul 14 05:47:09 PM PDT 24
Peak memory 248464 kb
Host smart-7193e933-9261-4b72-b5c3-d24868949eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853779559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2853779559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.2799203108
Short name T778
Test name
Test status
Simulation time 94225057 ps
CPU time 1.13 seconds
Started Jul 14 05:43:55 PM PDT 24
Finished Jul 14 05:43:57 PM PDT 24
Peak memory 206120 kb
Host smart-46c3c273-ad7b-4b83-8fda-95534598de6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799203108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2799203108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.3698088293
Short name T732
Test name
Test status
Simulation time 45615946 ps
CPU time 1.39 seconds
Started Jul 14 05:43:55 PM PDT 24
Finished Jul 14 05:43:57 PM PDT 24
Peak memory 215540 kb
Host smart-572f63b3-24c1-4dab-a0cc-6ad7643f19f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698088293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3698088293 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.1694719484
Short name T500
Test name
Test status
Simulation time 40635554016 ps
CPU time 1723.76 seconds
Started Jul 14 05:43:35 PM PDT 24
Finished Jul 14 06:12:19 PM PDT 24
Peak memory 418180 kb
Host smart-9559fa75-81dc-4b05-b889-01c1fbbba62a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694719484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.1694719484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.3443821997
Short name T529
Test name
Test status
Simulation time 75247669578 ps
CPU time 285.75 seconds
Started Jul 14 05:43:37 PM PDT 24
Finished Jul 14 05:48:23 PM PDT 24
Peak memory 241588 kb
Host smart-6708b0fd-b9e2-4f9e-aa8e-ccd3d08d3c24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443821997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3443821997 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.3335478887
Short name T810
Test name
Test status
Simulation time 225640860 ps
CPU time 2.61 seconds
Started Jul 14 05:43:35 PM PDT 24
Finished Jul 14 05:43:38 PM PDT 24
Peak memory 215932 kb
Host smart-c203f839-8d02-4d41-84c5-4dd38ecc1d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335478887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3335478887 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.1741269485
Short name T708
Test name
Test status
Simulation time 5985022493 ps
CPU time 473.09 seconds
Started Jul 14 05:43:56 PM PDT 24
Finished Jul 14 05:51:49 PM PDT 24
Peak memory 288024 kb
Host smart-810070fe-7a74-4bdb-8be9-ce3ae842c7ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1741269485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1741269485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.2007213508
Short name T726
Test name
Test status
Simulation time 290156437 ps
CPU time 4.3 seconds
Started Jul 14 05:43:51 PM PDT 24
Finished Jul 14 05:43:56 PM PDT 24
Peak memory 215640 kb
Host smart-ce3ed4c4-2186-4167-8f59-5b1a1fad6528
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007213508 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.2007213508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.267745896
Short name T361
Test name
Test status
Simulation time 707341725 ps
CPU time 4.93 seconds
Started Jul 14 05:43:48 PM PDT 24
Finished Jul 14 05:43:54 PM PDT 24
Peak memory 215672 kb
Host smart-64270d20-d439-4cd3-9e22-0c5152c49387
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267745896 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.kmac_test_vectors_kmac_xof.267745896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.3059063881
Short name T414
Test name
Test status
Simulation time 569490352559 ps
CPU time 1782.71 seconds
Started Jul 14 05:43:37 PM PDT 24
Finished Jul 14 06:13:20 PM PDT 24
Peak memory 371316 kb
Host smart-1f06632a-a315-4919-9837-d44426f6516f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3059063881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3059063881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.1816568577
Short name T638
Test name
Test status
Simulation time 94865747656 ps
CPU time 1870.15 seconds
Started Jul 14 05:43:43 PM PDT 24
Finished Jul 14 06:14:54 PM PDT 24
Peak memory 390808 kb
Host smart-4808f87b-0a1f-42f9-b17c-1b93ef1ea848
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1816568577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.1816568577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.3520748698
Short name T957
Test name
Test status
Simulation time 52947004630 ps
CPU time 1085.01 seconds
Started Jul 14 05:43:42 PM PDT 24
Finished Jul 14 06:01:48 PM PDT 24
Peak memory 327304 kb
Host smart-23cbc30e-bbe9-483f-a83f-45c201e7c071
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3520748698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.3520748698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.570317363
Short name T1043
Test name
Test status
Simulation time 9677657717 ps
CPU time 778.11 seconds
Started Jul 14 05:43:42 PM PDT 24
Finished Jul 14 05:56:41 PM PDT 24
Peak memory 293404 kb
Host smart-89ee996c-b9e2-470f-8f15-79e13e25108c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=570317363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.570317363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.1184313846
Short name T694
Test name
Test status
Simulation time 461245408433 ps
CPU time 4039.71 seconds
Started Jul 14 05:43:43 PM PDT 24
Finished Jul 14 06:51:03 PM PDT 24
Peak memory 648004 kb
Host smart-bba74ebc-26a9-4e9f-827a-2bdc42052727
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1184313846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.1184313846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.3980652324
Short name T162
Test name
Test status
Simulation time 86271765876 ps
CPU time 3465.6 seconds
Started Jul 14 05:43:49 PM PDT 24
Finished Jul 14 06:41:36 PM PDT 24
Peak memory 558864 kb
Host smart-cbfd8e5b-c894-42bf-9140-34707c71c433
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3980652324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3980652324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.58319544
Short name T916
Test name
Test status
Simulation time 22275750 ps
CPU time 0.82 seconds
Started Jul 14 05:44:18 PM PDT 24
Finished Jul 14 05:44:19 PM PDT 24
Peak memory 205148 kb
Host smart-ae4a9502-c404-428f-aac4-d3695716fdd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58319544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.58319544 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.1852582397
Short name T104
Test name
Test status
Simulation time 12733093018 ps
CPU time 70.63 seconds
Started Jul 14 05:44:10 PM PDT 24
Finished Jul 14 05:45:21 PM PDT 24
Peak memory 226164 kb
Host smart-1c90e77a-da95-4290-85dc-5fa7bf90f4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852582397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1852582397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.263862843
Short name T755
Test name
Test status
Simulation time 8319534526 ps
CPU time 327.41 seconds
Started Jul 14 05:43:55 PM PDT 24
Finished Jul 14 05:49:22 PM PDT 24
Peak memory 227656 kb
Host smart-bfd43d70-a66d-41d5-af5d-d6d081357f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263862843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.263862843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.2636550865
Short name T394
Test name
Test status
Simulation time 36857428751 ps
CPU time 157.07 seconds
Started Jul 14 05:44:16 PM PDT 24
Finished Jul 14 05:46:53 PM PDT 24
Peak memory 235212 kb
Host smart-496ba345-d9b0-456b-bf18-7d697675165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636550865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2636550865 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.3395539901
Short name T655
Test name
Test status
Simulation time 4517839297 ps
CPU time 65.23 seconds
Started Jul 14 05:44:11 PM PDT 24
Finished Jul 14 05:45:17 PM PDT 24
Peak memory 240228 kb
Host smart-bf7f3b80-2b3e-42fc-b8d7-3569fe70c66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395539901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3395539901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.29094146
Short name T910
Test name
Test status
Simulation time 4683245064 ps
CPU time 7.38 seconds
Started Jul 14 05:44:11 PM PDT 24
Finished Jul 14 05:44:18 PM PDT 24
Peak memory 207416 kb
Host smart-6aa89343-ae96-4e3c-84f0-70efd55c90cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29094146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.29094146 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.4187083414
Short name T736
Test name
Test status
Simulation time 116233755 ps
CPU time 1.32 seconds
Started Jul 14 05:44:16 PM PDT 24
Finished Jul 14 05:44:18 PM PDT 24
Peak memory 215556 kb
Host smart-afa99d23-cef5-4077-8ac5-ba093129ae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187083414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4187083414 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.2754518495
Short name T761
Test name
Test status
Simulation time 110430435873 ps
CPU time 2296.86 seconds
Started Jul 14 05:43:57 PM PDT 24
Finished Jul 14 06:22:15 PM PDT 24
Peak memory 421352 kb
Host smart-df473cfc-5ffa-49c2-9f0a-3789b0017809
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754518495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.2754518495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.3614704365
Short name T516
Test name
Test status
Simulation time 9561677335 ps
CPU time 104.18 seconds
Started Jul 14 05:43:57 PM PDT 24
Finished Jul 14 05:45:41 PM PDT 24
Peak memory 229012 kb
Host smart-cf8b3ae5-351e-40ff-81d5-f2cbc9e2730a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614704365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3614704365 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.648349658
Short name T629
Test name
Test status
Simulation time 3452374993 ps
CPU time 45.94 seconds
Started Jul 14 05:43:56 PM PDT 24
Finished Jul 14 05:44:42 PM PDT 24
Peak memory 218948 kb
Host smart-b55e479b-61b3-40d2-b921-2390a787f4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648349658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.648349658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.4206132554
Short name T354
Test name
Test status
Simulation time 72755165592 ps
CPU time 1618.76 seconds
Started Jul 14 05:44:20 PM PDT 24
Finished Jul 14 06:11:19 PM PDT 24
Peak memory 397896 kb
Host smart-fc49e74c-2c93-4703-bfc9-e1d26fea62f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4206132554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4206132554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.2696711354
Short name T993
Test name
Test status
Simulation time 674921194 ps
CPU time 4.44 seconds
Started Jul 14 05:44:11 PM PDT 24
Finished Jul 14 05:44:15 PM PDT 24
Peak memory 215616 kb
Host smart-aa9f6f6c-74c5-4667-a77a-97f59d704160
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696711354 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.2696711354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.2089149526
Short name T853
Test name
Test status
Simulation time 141695624 ps
CPU time 4.16 seconds
Started Jul 14 05:44:13 PM PDT 24
Finished Jul 14 05:44:18 PM PDT 24
Peak memory 215520 kb
Host smart-57de9837-5d51-4053-a2c8-f4d717c78564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089149526 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.2089149526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.992924687
Short name T459
Test name
Test status
Simulation time 36010600660 ps
CPU time 1425.66 seconds
Started Jul 14 05:43:57 PM PDT 24
Finished Jul 14 06:07:44 PM PDT 24
Peak memory 375488 kb
Host smart-e57c42f4-652a-421e-b1fb-b764d1cceed5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=992924687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.992924687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.209146496
Short name T463
Test name
Test status
Simulation time 64675552792 ps
CPU time 1532.91 seconds
Started Jul 14 05:44:05 PM PDT 24
Finished Jul 14 06:09:38 PM PDT 24
Peak memory 368656 kb
Host smart-6e07de2d-edd5-4003-82ae-d69518d24425
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=209146496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.209146496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.2083810063
Short name T805
Test name
Test status
Simulation time 91997152727 ps
CPU time 1212.5 seconds
Started Jul 14 05:44:15 PM PDT 24
Finished Jul 14 06:04:28 PM PDT 24
Peak memory 329848 kb
Host smart-0bd9a5c8-57bc-4e0b-9f48-b45c7eb932e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2083810063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.2083810063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.2144833301
Short name T263
Test name
Test status
Simulation time 64011941268 ps
CPU time 970.29 seconds
Started Jul 14 05:44:09 PM PDT 24
Finished Jul 14 06:00:20 PM PDT 24
Peak memory 298208 kb
Host smart-edc47c7a-af27-4c97-a810-96e54c5ad7c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2144833301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.2144833301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.1202048859
Short name T828
Test name
Test status
Simulation time 262956201528 ps
CPU time 5115.98 seconds
Started Jul 14 05:44:14 PM PDT 24
Finished Jul 14 07:09:31 PM PDT 24
Peak memory 643428 kb
Host smart-18053705-fec3-42b3-997b-f24b9529895b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1202048859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.1202048859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.802187677
Short name T220
Test name
Test status
Simulation time 197430324345 ps
CPU time 4101.45 seconds
Started Jul 14 05:44:11 PM PDT 24
Finished Jul 14 06:52:33 PM PDT 24
Peak memory 558592 kb
Host smart-c740dbd6-d544-4b4e-a6f1-114bd48e980c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=802187677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.802187677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.2758311479
Short name T45
Test name
Test status
Simulation time 22004348 ps
CPU time 0.77 seconds
Started Jul 14 05:44:47 PM PDT 24
Finished Jul 14 05:44:48 PM PDT 24
Peak memory 205268 kb
Host smart-9d93029b-ca97-4841-b604-7c06a44ac82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758311479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2758311479 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.1655773158
Short name T338
Test name
Test status
Simulation time 16871527775 ps
CPU time 37.96 seconds
Started Jul 14 05:44:32 PM PDT 24
Finished Jul 14 05:45:11 PM PDT 24
Peak memory 223840 kb
Host smart-0eb94dbf-81d6-4944-8b49-aea505c8d3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655773158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1655773158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.549234310
Short name T293
Test name
Test status
Simulation time 7836213690 ps
CPU time 171.56 seconds
Started Jul 14 05:44:18 PM PDT 24
Finished Jul 14 05:47:10 PM PDT 24
Peak memory 224408 kb
Host smart-43ec9470-8215-4e9b-a471-5a17d2c6f232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549234310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.549234310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.3320774063
Short name T591
Test name
Test status
Simulation time 24427169089 ps
CPU time 115.12 seconds
Started Jul 14 05:44:39 PM PDT 24
Finished Jul 14 05:46:35 PM PDT 24
Peak memory 228492 kb
Host smart-51b12487-8495-4f74-aafb-e16ed970dd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320774063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3320774063 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.802072974
Short name T978
Test name
Test status
Simulation time 6355580780 ps
CPU time 261.85 seconds
Started Jul 14 05:44:38 PM PDT 24
Finished Jul 14 05:49:00 PM PDT 24
Peak memory 256592 kb
Host smart-f2580249-8525-49ca-a895-2ef1e2484fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802072974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.802072974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2047119351
Short name T434
Test name
Test status
Simulation time 3992893486 ps
CPU time 5.9 seconds
Started Jul 14 05:44:44 PM PDT 24
Finished Jul 14 05:44:50 PM PDT 24
Peak memory 207368 kb
Host smart-f1762108-f5b2-4b82-8480-a15d09bee944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047119351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2047119351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3152475659
Short name T1058
Test name
Test status
Simulation time 90297131 ps
CPU time 1.15 seconds
Started Jul 14 05:44:43 PM PDT 24
Finished Jul 14 05:44:45 PM PDT 24
Peak memory 215484 kb
Host smart-055f007f-fe1b-4382-b9b6-784b75c93f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152475659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3152475659 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3661043730
Short name T134
Test name
Test status
Simulation time 215127163672 ps
CPU time 2387.37 seconds
Started Jul 14 05:44:17 PM PDT 24
Finished Jul 14 06:24:05 PM PDT 24
Peak memory 430632 kb
Host smart-c64232c6-7581-467d-b06e-a281dd75abb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661043730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3661043730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.2867916426
Short name T870
Test name
Test status
Simulation time 1256601446 ps
CPU time 47.75 seconds
Started Jul 14 05:44:19 PM PDT 24
Finished Jul 14 05:45:07 PM PDT 24
Peak memory 223660 kb
Host smart-4e275f48-2ec7-4f76-9a6f-051e900ff938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867916426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2867916426 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.2949833754
Short name T503
Test name
Test status
Simulation time 188248592 ps
CPU time 10.04 seconds
Started Jul 14 05:44:18 PM PDT 24
Finished Jul 14 05:44:28 PM PDT 24
Peak memory 221772 kb
Host smart-44683c25-08fc-4d79-be27-d913b0fb3fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949833754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2949833754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.610782969
Short name T971
Test name
Test status
Simulation time 23951404976 ps
CPU time 1429.18 seconds
Started Jul 14 05:44:45 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 413984 kb
Host smart-b889344d-d7bb-4555-95df-3bfd3788da67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=610782969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.610782969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.1460569438
Short name T548
Test name
Test status
Simulation time 240451497 ps
CPU time 4.25 seconds
Started Jul 14 05:44:31 PM PDT 24
Finished Jul 14 05:44:36 PM PDT 24
Peak memory 208672 kb
Host smart-f0c7e574-5937-4439-9b39-c4784dae568c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460569438 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.1460569438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.1418037774
Short name T213
Test name
Test status
Simulation time 518919211 ps
CPU time 4.87 seconds
Started Jul 14 05:44:35 PM PDT 24
Finished Jul 14 05:44:40 PM PDT 24
Peak memory 215572 kb
Host smart-6bdc58b0-31e9-470c-84fd-7be44b019b41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418037774 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.1418037774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.4095778664
Short name T506
Test name
Test status
Simulation time 83661836773 ps
CPU time 1942.72 seconds
Started Jul 14 05:44:19 PM PDT 24
Finished Jul 14 06:16:43 PM PDT 24
Peak memory 389700 kb
Host smart-f5983db1-7138-432c-8f60-463f24509e8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4095778664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.4095778664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.4213794775
Short name T936
Test name
Test status
Simulation time 95456960600 ps
CPU time 1798.45 seconds
Started Jul 14 05:44:19 PM PDT 24
Finished Jul 14 06:14:18 PM PDT 24
Peak memory 371100 kb
Host smart-399f94ff-b050-446e-a20f-83dfa69c9c31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4213794775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.4213794775 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2603757570
Short name T1004
Test name
Test status
Simulation time 72340378296 ps
CPU time 1456.76 seconds
Started Jul 14 05:44:38 PM PDT 24
Finished Jul 14 06:08:55 PM PDT 24
Peak memory 334936 kb
Host smart-3c9cf629-f99d-4030-b1b9-a35049d01e5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2603757570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2603757570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.1588480594
Short name T282
Test name
Test status
Simulation time 34101552692 ps
CPU time 814.01 seconds
Started Jul 14 05:44:35 PM PDT 24
Finished Jul 14 05:58:09 PM PDT 24
Peak memory 293416 kb
Host smart-fc47fcd4-bc9e-4aed-9add-de462472198f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1588480594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.1588480594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.4214721758
Short name T435
Test name
Test status
Simulation time 208600566306 ps
CPU time 4138.45 seconds
Started Jul 14 05:44:35 PM PDT 24
Finished Jul 14 06:53:34 PM PDT 24
Peak memory 633884 kb
Host smart-758882be-068c-4ec7-b5d8-ec6c95b10bec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4214721758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.4214721758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.4290901956
Short name T197
Test name
Test status
Simulation time 218587394006 ps
CPU time 4323.33 seconds
Started Jul 14 05:44:33 PM PDT 24
Finished Jul 14 06:56:37 PM PDT 24
Peak memory 552116 kb
Host smart-35e9a773-e6bc-41b3-af6e-12807bf1fb8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4290901956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.4290901956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.963525243
Short name T1073
Test name
Test status
Simulation time 14231438 ps
CPU time 0.75 seconds
Started Jul 14 05:45:11 PM PDT 24
Finished Jul 14 05:45:12 PM PDT 24
Peak memory 205280 kb
Host smart-6a30d07d-9945-4fa7-90bb-1429bfa6d9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963525243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.963525243 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.225165077
Short name T329
Test name
Test status
Simulation time 13691565856 ps
CPU time 63.23 seconds
Started Jul 14 05:45:01 PM PDT 24
Finished Jul 14 05:46:04 PM PDT 24
Peak memory 223976 kb
Host smart-87b5efac-4a51-47b1-be9c-3277bc241c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225165077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.225165077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.247484550
Short name T1020
Test name
Test status
Simulation time 22750153872 ps
CPU time 335.29 seconds
Started Jul 14 05:44:54 PM PDT 24
Finished Jul 14 05:50:29 PM PDT 24
Peak memory 229128 kb
Host smart-8481c9a0-0469-437b-aaca-1fe04b7cc16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247484550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.247484550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.3443938267
Short name T660
Test name
Test status
Simulation time 76499169262 ps
CPU time 89.44 seconds
Started Jul 14 05:45:07 PM PDT 24
Finished Jul 14 05:46:36 PM PDT 24
Peak memory 224408 kb
Host smart-43230d49-b7b1-4b5e-8971-25f3c0bc6c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443938267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3443938267 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.3064135322
Short name T468
Test name
Test status
Simulation time 1852961478 ps
CPU time 14.36 seconds
Started Jul 14 05:45:09 PM PDT 24
Finished Jul 14 05:45:23 PM PDT 24
Peak memory 223680 kb
Host smart-d1768839-cffc-4e59-8b43-7939f191e465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064135322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3064135322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.818556557
Short name T1082
Test name
Test status
Simulation time 1228196365 ps
CPU time 3.76 seconds
Started Jul 14 05:45:11 PM PDT 24
Finished Jul 14 05:45:15 PM PDT 24
Peak memory 215412 kb
Host smart-754fee9c-ab75-4e26-b7eb-eeb8f02f6f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818556557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.818556557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.1401764565
Short name T1078
Test name
Test status
Simulation time 125516612 ps
CPU time 1.3 seconds
Started Jul 14 05:45:11 PM PDT 24
Finished Jul 14 05:45:12 PM PDT 24
Peak memory 215496 kb
Host smart-c377d496-77d9-4de8-99b5-c344ab9b1892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401764565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1401764565 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1487941904
Short name T510
Test name
Test status
Simulation time 107855444847 ps
CPU time 685.55 seconds
Started Jul 14 05:44:45 PM PDT 24
Finished Jul 14 05:56:11 PM PDT 24
Peak memory 292316 kb
Host smart-2711976c-146c-477a-934f-bb030891e5ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487941904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1487941904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.2536257272
Short name T711
Test name
Test status
Simulation time 5104109364 ps
CPU time 99.84 seconds
Started Jul 14 05:44:54 PM PDT 24
Finished Jul 14 05:46:35 PM PDT 24
Peak memory 229736 kb
Host smart-befdf65d-2e26-4cd7-8565-33f70a0aaa65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536257272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2536257272 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.2633615739
Short name T634
Test name
Test status
Simulation time 8541926297 ps
CPU time 40.08 seconds
Started Jul 14 05:44:46 PM PDT 24
Finished Jul 14 05:45:26 PM PDT 24
Peak memory 219140 kb
Host smart-a99b8c02-eb9b-4ade-bc2c-aedc93012faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633615739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2633615739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.966741722
Short name T431
Test name
Test status
Simulation time 11321880540 ps
CPU time 139.7 seconds
Started Jul 14 05:45:11 PM PDT 24
Finished Jul 14 05:47:31 PM PDT 24
Peak memory 251752 kb
Host smart-e8d90417-b058-4951-9f7e-66a7b98a8a04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=966741722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.966741722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.617070375
Short name T466
Test name
Test status
Simulation time 259162471 ps
CPU time 5.33 seconds
Started Jul 14 05:45:01 PM PDT 24
Finished Jul 14 05:45:06 PM PDT 24
Peak memory 208728 kb
Host smart-8909b519-21fe-471a-9203-eebc8cd554b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617070375 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.kmac_test_vectors_kmac.617070375 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1767640824
Short name T314
Test name
Test status
Simulation time 1006541456 ps
CPU time 4.96 seconds
Started Jul 14 05:44:59 PM PDT 24
Finished Jul 14 05:45:04 PM PDT 24
Peak memory 215508 kb
Host smart-a4fc9a7f-9bb1-46b6-8457-379d32f21f4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767640824 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1767640824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.1712170214
Short name T294
Test name
Test status
Simulation time 136887780719 ps
CPU time 1930.52 seconds
Started Jul 14 05:44:53 PM PDT 24
Finished Jul 14 06:17:04 PM PDT 24
Peak memory 395872 kb
Host smart-dc5db28c-514f-4a12-916f-54aa3fda9987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1712170214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.1712170214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.471964427
Short name T592
Test name
Test status
Simulation time 17695897782 ps
CPU time 1512.51 seconds
Started Jul 14 05:44:54 PM PDT 24
Finished Jul 14 06:10:06 PM PDT 24
Peak memory 373092 kb
Host smart-71873ce8-537f-49a2-baa6-31036aa64a5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=471964427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.471964427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.2268524280
Short name T860
Test name
Test status
Simulation time 13623144700 ps
CPU time 1009.97 seconds
Started Jul 14 05:44:52 PM PDT 24
Finished Jul 14 06:01:42 PM PDT 24
Peak memory 323852 kb
Host smart-b3f1899e-0305-41d0-90f4-b813c1d86cff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2268524280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2268524280 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2811170639
Short name T950
Test name
Test status
Simulation time 9448127385 ps
CPU time 778.55 seconds
Started Jul 14 05:44:57 PM PDT 24
Finished Jul 14 05:57:56 PM PDT 24
Peak memory 293860 kb
Host smart-32d2193d-4394-4458-b702-da0c6da8ec72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2811170639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2811170639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.468473175
Short name T406
Test name
Test status
Simulation time 784383572097 ps
CPU time 4959.87 seconds
Started Jul 14 05:44:52 PM PDT 24
Finished Jul 14 07:07:33 PM PDT 24
Peak memory 655180 kb
Host smart-bf316a29-0021-4938-8cc8-ecf3749cadc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=468473175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.468473175 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2391382815
Short name T636
Test name
Test status
Simulation time 295536771674 ps
CPU time 3851.42 seconds
Started Jul 14 05:44:59 PM PDT 24
Finished Jul 14 06:49:11 PM PDT 24
Peak memory 558788 kb
Host smart-c458668d-609c-4f1b-8fb1-47c00f6ca558
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2391382815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2391382815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.38936297
Short name T476
Test name
Test status
Simulation time 27444202 ps
CPU time 0.8 seconds
Started Jul 14 05:45:43 PM PDT 24
Finished Jul 14 05:45:45 PM PDT 24
Peak memory 205184 kb
Host smart-c0e68d58-69fa-4130-a8a0-35b30fcbe8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38936297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.38936297 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.3906954603
Short name T684
Test name
Test status
Simulation time 227759777 ps
CPU time 4.3 seconds
Started Jul 14 05:45:27 PM PDT 24
Finished Jul 14 05:45:32 PM PDT 24
Peak memory 216608 kb
Host smart-3cb81ce6-b125-4b2d-8d20-216546a48845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906954603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3906954603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.1627107878
Short name T330
Test name
Test status
Simulation time 8222094836 ps
CPU time 111.83 seconds
Started Jul 14 05:45:14 PM PDT 24
Finished Jul 14 05:47:06 PM PDT 24
Peak memory 223344 kb
Host smart-8c651f59-bb7f-48d8-ab7c-7ce202f913a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627107878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1627107878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.3508754735
Short name T914
Test name
Test status
Simulation time 26212603844 ps
CPU time 250.28 seconds
Started Jul 14 05:45:33 PM PDT 24
Finished Jul 14 05:49:44 PM PDT 24
Peak memory 243576 kb
Host smart-0cb8ccfb-786a-4366-93eb-3d74121602b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508754735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3508754735 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.3633272898
Short name T673
Test name
Test status
Simulation time 15951519064 ps
CPU time 229.55 seconds
Started Jul 14 05:45:34 PM PDT 24
Finished Jul 14 05:49:24 PM PDT 24
Peak memory 256556 kb
Host smart-4c1eadcb-6f4b-44bb-befe-2def90db2340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633272898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3633272898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.2000521403
Short name T721
Test name
Test status
Simulation time 8470645666 ps
CPU time 7.54 seconds
Started Jul 14 05:45:36 PM PDT 24
Finished Jul 14 05:45:44 PM PDT 24
Peak memory 215508 kb
Host smart-3fe54bce-3c42-48fc-8dbc-d6c509ddcc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000521403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2000521403 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.1034048405
Short name T747
Test name
Test status
Simulation time 50891464 ps
CPU time 1.3 seconds
Started Jul 14 05:45:41 PM PDT 24
Finished Jul 14 05:45:43 PM PDT 24
Peak memory 217252 kb
Host smart-e5ada4ae-9bac-44e2-afc9-7d21e5aa5735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034048405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1034048405 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.2152412798
Short name T824
Test name
Test status
Simulation time 98276712984 ps
CPU time 2682.56 seconds
Started Jul 14 05:45:15 PM PDT 24
Finished Jul 14 06:29:58 PM PDT 24
Peak memory 491188 kb
Host smart-9307accc-f75c-4054-a7de-1dac929869fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152412798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.2152412798 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.2750381268
Short name T433
Test name
Test status
Simulation time 60158684714 ps
CPU time 351.62 seconds
Started Jul 14 05:45:13 PM PDT 24
Finished Jul 14 05:51:05 PM PDT 24
Peak memory 249480 kb
Host smart-b7c14747-0105-4561-840e-e0e55f17f917
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750381268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2750381268 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.1437181320
Short name T981
Test name
Test status
Simulation time 1510849575 ps
CPU time 19.55 seconds
Started Jul 14 05:45:15 PM PDT 24
Finished Jul 14 05:45:35 PM PDT 24
Peak memory 223688 kb
Host smart-6218babc-8f42-498d-b0af-8ce41cd64e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437181320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1437181320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.4178428746
Short name T1057
Test name
Test status
Simulation time 185181503 ps
CPU time 4.75 seconds
Started Jul 14 05:45:29 PM PDT 24
Finished Jul 14 05:45:34 PM PDT 24
Peak memory 215596 kb
Host smart-0e9e8bc6-ab61-4600-9c9c-64bacce03cdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178428746 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.4178428746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.395908023
Short name T13
Test name
Test status
Simulation time 347936220 ps
CPU time 4.5 seconds
Started Jul 14 05:45:31 PM PDT 24
Finished Jul 14 05:45:36 PM PDT 24
Peak memory 215660 kb
Host smart-566a839c-34e3-4e91-82e4-3af655590a3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395908023 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.kmac_test_vectors_kmac_xof.395908023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.3486015536
Short name T480
Test name
Test status
Simulation time 38981257675 ps
CPU time 1466.97 seconds
Started Jul 14 05:45:12 PM PDT 24
Finished Jul 14 06:09:40 PM PDT 24
Peak memory 389724 kb
Host smart-81cc5fba-6b37-45e9-ab53-6969d27d02ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3486015536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.3486015536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.4144754050
Short name T964
Test name
Test status
Simulation time 109268448497 ps
CPU time 1781.19 seconds
Started Jul 14 05:45:22 PM PDT 24
Finished Jul 14 06:15:04 PM PDT 24
Peak memory 376132 kb
Host smart-eb1addca-1695-47ae-b949-55ed3fa9feec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4144754050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.4144754050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1121756641
Short name T953
Test name
Test status
Simulation time 49203969174 ps
CPU time 1384.6 seconds
Started Jul 14 05:45:20 PM PDT 24
Finished Jul 14 06:08:25 PM PDT 24
Peak memory 336564 kb
Host smart-940dd7ab-b2b3-4c8c-b6ae-888bb8b90706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1121756641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1121756641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.2927984569
Short name T280
Test name
Test status
Simulation time 140080769420 ps
CPU time 988.08 seconds
Started Jul 14 05:45:22 PM PDT 24
Finished Jul 14 06:01:51 PM PDT 24
Peak memory 299952 kb
Host smart-a15284df-a7ae-47bc-a38e-86cf7ad4a63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2927984569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.2927984569 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.1595384660
Short name T493
Test name
Test status
Simulation time 101848380411 ps
CPU time 4175.2 seconds
Started Jul 14 05:45:24 PM PDT 24
Finished Jul 14 06:55:00 PM PDT 24
Peak memory 651496 kb
Host smart-d3087bc5-0f06-4d15-ab44-95f989f6bbc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1595384660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.1595384660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.3900723899
Short name T1079
Test name
Test status
Simulation time 42951675124 ps
CPU time 3479.48 seconds
Started Jul 14 05:45:29 PM PDT 24
Finished Jul 14 06:43:29 PM PDT 24
Peak memory 555624 kb
Host smart-3730c5b4-8bba-493b-8ea8-e5cd8220288c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3900723899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3900723899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.1510350325
Short name T492
Test name
Test status
Simulation time 70237891 ps
CPU time 0.8 seconds
Started Jul 14 05:46:14 PM PDT 24
Finished Jul 14 05:46:15 PM PDT 24
Peak memory 205260 kb
Host smart-228658ee-fa7c-4c92-9c34-73a4fadf3a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510350325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1510350325 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.92321996
Short name T907
Test name
Test status
Simulation time 1043256945 ps
CPU time 10.43 seconds
Started Jul 14 05:46:08 PM PDT 24
Finished Jul 14 05:46:19 PM PDT 24
Peak memory 217136 kb
Host smart-dbf63834-0c55-4217-a3b1-e9eb5f3b8d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92321996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.92321996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.2257630112
Short name T861
Test name
Test status
Simulation time 9607067114 ps
CPU time 301.68 seconds
Started Jul 14 05:45:53 PM PDT 24
Finished Jul 14 05:50:55 PM PDT 24
Peak memory 226460 kb
Host smart-ad20149c-f067-44e3-92b0-974eabf60fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257630112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2257630112 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.3637063537
Short name T202
Test name
Test status
Simulation time 493924978 ps
CPU time 5.53 seconds
Started Jul 14 05:46:07 PM PDT 24
Finished Jul 14 05:46:13 PM PDT 24
Peak memory 215612 kb
Host smart-94101082-6635-40cb-bd4d-28e9653c456d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637063537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3637063537 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.416812458
Short name T996
Test name
Test status
Simulation time 16231147908 ps
CPU time 77.78 seconds
Started Jul 14 05:46:07 PM PDT 24
Finished Jul 14 05:47:25 PM PDT 24
Peak memory 240236 kb
Host smart-7dd23df7-cd7d-4dc7-9dfc-6c82686b0123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416812458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.416812458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.3485263239
Short name T770
Test name
Test status
Simulation time 11009003721 ps
CPU time 4.59 seconds
Started Jul 14 05:46:06 PM PDT 24
Finished Jul 14 05:46:11 PM PDT 24
Peak memory 207464 kb
Host smart-9a07ec6a-6924-41d9-bcd2-988160926c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485263239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3485263239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.1538896011
Short name T609
Test name
Test status
Simulation time 115914427 ps
CPU time 1.29 seconds
Started Jul 14 05:46:15 PM PDT 24
Finished Jul 14 05:46:17 PM PDT 24
Peak memory 215508 kb
Host smart-f70332b5-7dd1-4ca2-bd02-7f254b0a03ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538896011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1538896011 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.3167703383
Short name T869
Test name
Test status
Simulation time 42088567337 ps
CPU time 1528.87 seconds
Started Jul 14 05:45:47 PM PDT 24
Finished Jul 14 06:11:16 PM PDT 24
Peak memory 391264 kb
Host smart-e7a24c68-6d51-43b6-bc5c-5fdd4d9016f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167703383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.3167703383 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.222403538
Short name T432
Test name
Test status
Simulation time 12242466129 ps
CPU time 75.59 seconds
Started Jul 14 05:45:51 PM PDT 24
Finished Jul 14 05:47:06 PM PDT 24
Peak memory 225292 kb
Host smart-0bce31ac-2f2d-4c1d-95a9-56a1cd59efcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222403538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.222403538 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.917979580
Short name T203
Test name
Test status
Simulation time 1611424739 ps
CPU time 27.54 seconds
Started Jul 14 05:45:43 PM PDT 24
Finished Jul 14 05:46:11 PM PDT 24
Peak memory 219032 kb
Host smart-a80c0ad4-4997-4fee-b0a9-9b4e3263232b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917979580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.917979580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.82554522
Short name T888
Test name
Test status
Simulation time 26916614537 ps
CPU time 585.45 seconds
Started Jul 14 05:46:17 PM PDT 24
Finished Jul 14 05:56:02 PM PDT 24
Peak memory 301660 kb
Host smart-34fd804a-982b-4abc-8f5a-3ef516b6f79d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=82554522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.82554522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.3162079286
Short name T1064
Test name
Test status
Simulation time 69703474 ps
CPU time 4.05 seconds
Started Jul 14 05:46:02 PM PDT 24
Finished Jul 14 05:46:06 PM PDT 24
Peak memory 215640 kb
Host smart-a802c217-439d-46e5-9de7-0c958c380989
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162079286 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.3162079286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.851777176
Short name T856
Test name
Test status
Simulation time 69397550 ps
CPU time 4.05 seconds
Started Jul 14 05:46:06 PM PDT 24
Finished Jul 14 05:46:10 PM PDT 24
Peak memory 215600 kb
Host smart-364c36ae-86a3-4716-a852-d0a8c242c5da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851777176 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.kmac_test_vectors_kmac_xof.851777176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.4129747899
Short name T199
Test name
Test status
Simulation time 135845802857 ps
CPU time 1899.05 seconds
Started Jul 14 05:45:53 PM PDT 24
Finished Jul 14 06:17:33 PM PDT 24
Peak memory 394096 kb
Host smart-cd366bc0-7435-44dd-a196-ed661b046b8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4129747899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.4129747899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.2919815109
Short name T677
Test name
Test status
Simulation time 121219868018 ps
CPU time 1760.75 seconds
Started Jul 14 05:45:53 PM PDT 24
Finished Jul 14 06:15:14 PM PDT 24
Peak memory 378528 kb
Host smart-42d2d061-7478-4ca9-bdfd-bd6f3f91889b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2919815109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.2919815109 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.1764402045
Short name T703
Test name
Test status
Simulation time 88434464315 ps
CPU time 1074.74 seconds
Started Jul 14 05:45:53 PM PDT 24
Finished Jul 14 06:03:49 PM PDT 24
Peak memory 327524 kb
Host smart-b58575d7-0b17-4270-bcf9-c94e56e7cef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1764402045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.1764402045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.2804905251
Short name T317
Test name
Test status
Simulation time 50497048595 ps
CPU time 1048.86 seconds
Started Jul 14 05:46:01 PM PDT 24
Finished Jul 14 06:03:30 PM PDT 24
Peak memory 295504 kb
Host smart-e0d8b1b8-2dad-45b1-b538-b7340a0699c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2804905251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.2804905251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.2558503328
Short name T682
Test name
Test status
Simulation time 223299938394 ps
CPU time 4546.43 seconds
Started Jul 14 05:46:00 PM PDT 24
Finished Jul 14 07:01:47 PM PDT 24
Peak memory 651444 kb
Host smart-694e5a51-dd3a-4811-b4dc-2f2d0e48b56a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2558503328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2558503328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.3540875562
Short name T177
Test name
Test status
Simulation time 1215544236969 ps
CPU time 4497 seconds
Started Jul 14 05:46:00 PM PDT 24
Finished Jul 14 07:00:58 PM PDT 24
Peak memory 569416 kb
Host smart-60ed1a3f-523e-4eb4-a1db-980104bf2b2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3540875562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3540875562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.305539946
Short name T769
Test name
Test status
Simulation time 14041973 ps
CPU time 0.79 seconds
Started Jul 14 05:46:58 PM PDT 24
Finished Jul 14 05:46:59 PM PDT 24
Peak memory 205236 kb
Host smart-2867e8be-0aec-4b50-bdf3-85432670b28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305539946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.305539946 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.2566734769
Short name T322
Test name
Test status
Simulation time 2470711529 ps
CPU time 69.55 seconds
Started Jul 14 05:46:49 PM PDT 24
Finished Jul 14 05:47:58 PM PDT 24
Peak memory 227048 kb
Host smart-51e0869d-574e-4c2a-a876-c617e1101512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566734769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2566734769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.555879810
Short name T37
Test name
Test status
Simulation time 15215074477 ps
CPU time 655.76 seconds
Started Jul 14 05:46:21 PM PDT 24
Finished Jul 14 05:57:17 PM PDT 24
Peak memory 231800 kb
Host smart-960aabe6-1971-468f-a1cf-b4484ab4b6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555879810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.555879810 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.4056364665
Short name T608
Test name
Test status
Simulation time 53686121060 ps
CPU time 295.31 seconds
Started Jul 14 05:46:52 PM PDT 24
Finished Jul 14 05:51:48 PM PDT 24
Peak memory 244292 kb
Host smart-60452650-ad33-4a2e-9b9f-beda0af2e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056364665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.4056364665 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.1953256368
Short name T625
Test name
Test status
Simulation time 39872161005 ps
CPU time 286.7 seconds
Started Jul 14 05:46:51 PM PDT 24
Finished Jul 14 05:51:38 PM PDT 24
Peak memory 251100 kb
Host smart-6cae769c-360c-490b-abcc-0df0fa601a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953256368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1953256368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.1151717627
Short name T928
Test name
Test status
Simulation time 291156161 ps
CPU time 2.28 seconds
Started Jul 14 05:46:49 PM PDT 24
Finished Jul 14 05:46:52 PM PDT 24
Peak memory 207156 kb
Host smart-45ba6b69-2775-4de1-837d-4a89bbb7b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151717627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1151717627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.1712437908
Short name T290
Test name
Test status
Simulation time 64102628394 ps
CPU time 1556.24 seconds
Started Jul 14 05:46:20 PM PDT 24
Finished Jul 14 06:12:17 PM PDT 24
Peak memory 366528 kb
Host smart-24235e10-0add-4f2e-bb1e-c9df23025cb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712437908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.1712437908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.2472231014
Short name T525
Test name
Test status
Simulation time 15427434026 ps
CPU time 183.38 seconds
Started Jul 14 05:46:24 PM PDT 24
Finished Jul 14 05:49:27 PM PDT 24
Peak memory 232768 kb
Host smart-fa8c2828-83a9-4d0b-b0d3-bd42db840a0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472231014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2472231014 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.2891550010
Short name T179
Test name
Test status
Simulation time 3877414232 ps
CPU time 30.01 seconds
Started Jul 14 05:46:23 PM PDT 24
Finished Jul 14 05:46:54 PM PDT 24
Peak memory 215660 kb
Host smart-b0799aa3-997f-4d0b-bb13-96ff17426b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891550010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2891550010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.1335790463
Short name T792
Test name
Test status
Simulation time 160925684956 ps
CPU time 847.8 seconds
Started Jul 14 05:46:58 PM PDT 24
Finished Jul 14 06:01:06 PM PDT 24
Peak memory 321720 kb
Host smart-53c58c6f-c0bc-4fdc-ab97-be2ffa2e6d3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1335790463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1335790463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.763550551
Short name T1009
Test name
Test status
Simulation time 230071794 ps
CPU time 4.3 seconds
Started Jul 14 05:46:41 PM PDT 24
Finished Jul 14 05:46:46 PM PDT 24
Peak memory 215828 kb
Host smart-3bec83f9-e793-4905-96b0-78fca4106478
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763550551 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.kmac_test_vectors_kmac.763550551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.241412026
Short name T623
Test name
Test status
Simulation time 297411840 ps
CPU time 3.81 seconds
Started Jul 14 05:46:41 PM PDT 24
Finished Jul 14 05:46:45 PM PDT 24
Peak memory 215632 kb
Host smart-012dffa0-ed9e-45ad-a7d6-a6f72efdd1c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241412026 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.kmac_test_vectors_kmac_xof.241412026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.3500101277
Short name T462
Test name
Test status
Simulation time 403366367420 ps
CPU time 2024.37 seconds
Started Jul 14 05:46:25 PM PDT 24
Finished Jul 14 06:20:09 PM PDT 24
Peak memory 390640 kb
Host smart-bd9ceeca-b95d-4389-9c58-00868054413b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3500101277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3500101277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.3272862638
Short name T753
Test name
Test status
Simulation time 681863627472 ps
CPU time 1762.17 seconds
Started Jul 14 05:46:28 PM PDT 24
Finished Jul 14 06:15:51 PM PDT 24
Peak memory 375008 kb
Host smart-7a07f271-84e7-43c8-a573-56a52ea81d9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3272862638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.3272862638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.1888250992
Short name T49
Test name
Test status
Simulation time 196445111954 ps
CPU time 1386.22 seconds
Started Jul 14 05:46:36 PM PDT 24
Finished Jul 14 06:09:43 PM PDT 24
Peak memory 335480 kb
Host smart-d4dc4d6f-1dde-4361-b8e1-d2861bdfd3a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1888250992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.1888250992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.1723113156
Short name T937
Test name
Test status
Simulation time 139114297904 ps
CPU time 1015.43 seconds
Started Jul 14 05:46:35 PM PDT 24
Finished Jul 14 06:03:31 PM PDT 24
Peak memory 298900 kb
Host smart-20cfd867-aeb9-400f-8e0d-e1b5edb7200d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1723113156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.1723113156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.267815805
Short name T781
Test name
Test status
Simulation time 265278263200 ps
CPU time 5343.32 seconds
Started Jul 14 05:46:35 PM PDT 24
Finished Jul 14 07:15:39 PM PDT 24
Peak memory 652808 kb
Host smart-1c4b6182-d578-43e3-ad63-9972219a37e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=267815805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.267815805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3880469580
Short name T697
Test name
Test status
Simulation time 172726696354 ps
CPU time 3535.49 seconds
Started Jul 14 05:46:43 PM PDT 24
Finished Jul 14 06:45:39 PM PDT 24
Peak memory 558848 kb
Host smart-86f18c1c-0f50-4f07-8f84-f162dc1201ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3880469580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3880469580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1111265570
Short name T731
Test name
Test status
Simulation time 47955587 ps
CPU time 0.76 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:34:30 PM PDT 24
Peak memory 205164 kb
Host smart-5c52f514-c6ed-43c6-a96b-abe8e1203646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111265570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1111265570 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.3445087961
Short name T151
Test name
Test status
Simulation time 13339825544 ps
CPU time 89.66 seconds
Started Jul 14 05:34:23 PM PDT 24
Finished Jul 14 05:35:53 PM PDT 24
Peak memory 227544 kb
Host smart-6fd67866-a2a1-430b-9832-ca28345bec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445087961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3445087961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.3853831024
Short name T923
Test name
Test status
Simulation time 7222298472 ps
CPU time 111.3 seconds
Started Jul 14 05:34:22 PM PDT 24
Finished Jul 14 05:36:14 PM PDT 24
Peak memory 231196 kb
Host smart-d1393198-70b0-448a-980c-27449ede3f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853831024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3853831024 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.3775843576
Short name T1074
Test name
Test status
Simulation time 37444575861 ps
CPU time 875.87 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:49:06 PM PDT 24
Peak memory 233192 kb
Host smart-bdabe148-e755-4711-8783-266e3d21660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775843576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3775843576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.466412438
Short name T626
Test name
Test status
Simulation time 11961847151 ps
CPU time 35.31 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:35:04 PM PDT 24
Peak memory 224856 kb
Host smart-d651ef6c-28af-46cc-b45f-c200031c30d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=466412438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.466412438 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.4172852276
Short name T457
Test name
Test status
Simulation time 1057343413 ps
CPU time 26.83 seconds
Started Jul 14 05:34:23 PM PDT 24
Finished Jul 14 05:34:51 PM PDT 24
Peak memory 223728 kb
Host smart-7352ddf2-3b3b-42a0-9b7d-43813273d38f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4172852276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.4172852276 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2037693160
Short name T499
Test name
Test status
Simulation time 17882319764 ps
CPU time 54.5 seconds
Started Jul 14 05:34:21 PM PDT 24
Finished Jul 14 05:35:16 PM PDT 24
Peak memory 223772 kb
Host smart-18a58da2-0311-458e-8d30-00e4ff8a6960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037693160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2037693160 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.1360994835
Short name T705
Test name
Test status
Simulation time 4033834761 ps
CPU time 118.3 seconds
Started Jul 14 05:34:22 PM PDT 24
Finished Jul 14 05:36:21 PM PDT 24
Peak memory 231876 kb
Host smart-302f0171-b3ec-45ce-acdc-bbd411b6d477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360994835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1360994835 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.135523181
Short name T460
Test name
Test status
Simulation time 19975850718 ps
CPU time 254.88 seconds
Started Jul 14 05:34:23 PM PDT 24
Finished Jul 14 05:38:39 PM PDT 24
Peak memory 248456 kb
Host smart-8cd5f6a7-88a2-4756-bfc6-cf269b850263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135523181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.135523181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.3996481658
Short name T624
Test name
Test status
Simulation time 354482001 ps
CPU time 2.3 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:34:33 PM PDT 24
Peak memory 215512 kb
Host smart-a31082f4-4ab0-4f35-b165-d7617c7095cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996481658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3996481658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.3105122196
Short name T83
Test name
Test status
Simulation time 67981935 ps
CPU time 1.31 seconds
Started Jul 14 05:34:24 PM PDT 24
Finished Jul 14 05:34:26 PM PDT 24
Peak memory 215596 kb
Host smart-eedccd6e-ce99-4722-8b7c-118c41695d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105122196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3105122196 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.486737650
Short name T256
Test name
Test status
Simulation time 65423464442 ps
CPU time 1667.46 seconds
Started Jul 14 05:34:22 PM PDT 24
Finished Jul 14 06:02:10 PM PDT 24
Peak memory 407976 kb
Host smart-2983322b-496a-419d-8910-0813c96b8f03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486737650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and
_output.486737650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.2329048608
Short name T743
Test name
Test status
Simulation time 3715506182 ps
CPU time 35.19 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:35:06 PM PDT 24
Peak memory 224048 kb
Host smart-e18000db-c4ba-4186-811d-bac6302217cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329048608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2329048608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.554440903
Short name T692
Test name
Test status
Simulation time 60134321542 ps
CPU time 312.26 seconds
Started Jul 14 05:34:24 PM PDT 24
Finished Jul 14 05:39:37 PM PDT 24
Peak memory 242084 kb
Host smart-83f0f4ec-bf54-4c7b-a4a3-1505d77f266f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554440903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.554440903 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.3809647351
Short name T450
Test name
Test status
Simulation time 8243415245 ps
CPU time 69.82 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:35:39 PM PDT 24
Peak memory 220360 kb
Host smart-99e78432-24c4-4e83-9f41-0180ab2b7222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809647351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3809647351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.2594028564
Short name T871
Test name
Test status
Simulation time 92633409061 ps
CPU time 197.18 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 05:37:44 PM PDT 24
Peak memory 270024 kb
Host smart-4360dec6-a0e4-42bd-8038-74adada3833f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2594028564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2594028564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.587782663
Short name T585
Test name
Test status
Simulation time 497833071 ps
CPU time 4.96 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 05:34:32 PM PDT 24
Peak memory 215672 kb
Host smart-e8620ad5-6545-49f9-9184-42312512acb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587782663 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.kmac_test_vectors_kmac.587782663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.1487283252
Short name T438
Test name
Test status
Simulation time 178819812 ps
CPU time 4.76 seconds
Started Jul 14 05:34:21 PM PDT 24
Finished Jul 14 05:34:26 PM PDT 24
Peak memory 215700 kb
Host smart-5dbb0269-9681-44fd-a034-33b8ff69e809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487283252 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.1487283252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.3267118547
Short name T259
Test name
Test status
Simulation time 756281190109 ps
CPU time 1923.75 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 06:06:42 PM PDT 24
Peak memory 395972 kb
Host smart-e7781015-01c8-4522-9af4-87729fd35490
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3267118547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.3267118547 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.3540949246
Short name T654
Test name
Test status
Simulation time 334038545738 ps
CPU time 1860.1 seconds
Started Jul 14 05:34:23 PM PDT 24
Finished Jul 14 06:05:24 PM PDT 24
Peak memory 377848 kb
Host smart-06a29be8-d300-4079-bc6e-e584648915a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3540949246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.3540949246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.1580326718
Short name T784
Test name
Test status
Simulation time 13896909551 ps
CPU time 1114.43 seconds
Started Jul 14 05:34:20 PM PDT 24
Finished Jul 14 05:52:55 PM PDT 24
Peak memory 332144 kb
Host smart-5224bbc3-823a-47ed-ae86-35a865d507aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1580326718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.1580326718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.656535949
Short name T292
Test name
Test status
Simulation time 100577152840 ps
CPU time 998.53 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 05:51:05 PM PDT 24
Peak memory 292876 kb
Host smart-b2626d2f-cfc7-454e-bea6-59799e5039bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=656535949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.656535949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.3941841447
Short name T849
Test name
Test status
Simulation time 104979688491 ps
CPU time 4366.8 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 06:47:14 PM PDT 24
Peak memory 662360 kb
Host smart-af05a593-9131-4346-8461-fa191b6283d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3941841447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.3941841447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.3035971158
Short name T207
Test name
Test status
Simulation time 605063716093 ps
CPU time 3782.28 seconds
Started Jul 14 05:34:22 PM PDT 24
Finished Jul 14 06:37:26 PM PDT 24
Peak memory 560156 kb
Host smart-79b54803-7739-4c98-8234-5884e109673b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3035971158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.3035971158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.1361009555
Short name T696
Test name
Test status
Simulation time 20010010 ps
CPU time 0.79 seconds
Started Jul 14 05:34:32 PM PDT 24
Finished Jul 14 05:34:33 PM PDT 24
Peak memory 205272 kb
Host smart-d80dbe0c-67ff-441b-98c7-553b6ec59118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361009555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1361009555 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.95202213
Short name T101
Test name
Test status
Simulation time 4610863355 ps
CPU time 61.48 seconds
Started Jul 14 05:34:30 PM PDT 24
Finished Jul 14 05:35:33 PM PDT 24
Peak memory 226420 kb
Host smart-532ec699-39de-45b8-ae60-839eede94d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95202213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.95202213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1823959506
Short name T387
Test name
Test status
Simulation time 5647491159 ps
CPU time 158.27 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:37:09 PM PDT 24
Peak memory 235504 kb
Host smart-2107eb3f-e45f-43d3-a11b-4846a66f0f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823959506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1823959506 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.629307302
Short name T1071
Test name
Test status
Simulation time 9622641399 ps
CPU time 52.43 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 05:35:27 PM PDT 24
Peak memory 219916 kb
Host smart-5551b056-2eb7-4b01-b290-ae0dbbb73df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629307302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.629307302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2760626750
Short name T1075
Test name
Test status
Simulation time 506074801 ps
CPU time 36.27 seconds
Started Jul 14 05:34:39 PM PDT 24
Finished Jul 14 05:35:16 PM PDT 24
Peak memory 223604 kb
Host smart-a760a005-0edb-4b10-8397-204a01605531
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760626750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2760626750 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1077323285
Short name T1028
Test name
Test status
Simulation time 327928173 ps
CPU time 21.47 seconds
Started Jul 14 05:34:34 PM PDT 24
Finished Jul 14 05:34:57 PM PDT 24
Peak memory 236300 kb
Host smart-715dfb28-fc0a-47d1-841c-59e987b9adc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1077323285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1077323285 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.3535617157
Short name T422
Test name
Test status
Simulation time 11916841007 ps
CPU time 27.2 seconds
Started Jul 14 05:34:30 PM PDT 24
Finished Jul 14 05:34:59 PM PDT 24
Peak memory 216568 kb
Host smart-85b75cd6-e700-4099-895b-e6bf5b6800e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535617157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3535617157 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.861310737
Short name T855
Test name
Test status
Simulation time 6725541029 ps
CPU time 216.16 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 05:38:10 PM PDT 24
Peak memory 242068 kb
Host smart-fcfce352-20f4-4f39-ba55-dfbd64bb765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861310737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.861310737 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.3948795638
Short name T363
Test name
Test status
Simulation time 972485590 ps
CPU time 15.07 seconds
Started Jul 14 05:34:34 PM PDT 24
Finished Jul 14 05:34:50 PM PDT 24
Peak memory 223812 kb
Host smart-f24bd4a7-0957-4d3c-9f8e-25d2dc8fa75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948795638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3948795638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.2387966041
Short name T404
Test name
Test status
Simulation time 1796943018 ps
CPU time 3.69 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:40 PM PDT 24
Peak memory 215520 kb
Host smart-b8eac569-16c2-489b-9909-a90fce37a964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387966041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2387966041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.2803812067
Short name T268
Test name
Test status
Simulation time 52234275 ps
CPU time 1.44 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:38 PM PDT 24
Peak memory 215564 kb
Host smart-c56a35b6-9a20-4896-b297-a2d91c179d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803812067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2803812067 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.3679071141
Short name T318
Test name
Test status
Simulation time 57612091428 ps
CPU time 392.01 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 05:40:59 PM PDT 24
Peak memory 262112 kb
Host smart-93a2b0b4-1f75-428a-8dfa-c9c56390f584
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679071141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.3679071141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.3279940517
Short name T837
Test name
Test status
Simulation time 495858281 ps
CPU time 9.02 seconds
Started Jul 14 05:34:32 PM PDT 24
Finished Jul 14 05:34:41 PM PDT 24
Peak memory 224080 kb
Host smart-f4429fd7-da31-4196-84be-0bf145bb7042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279940517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3279940517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.2004191421
Short name T1012
Test name
Test status
Simulation time 23681782761 ps
CPU time 238.6 seconds
Started Jul 14 05:34:27 PM PDT 24
Finished Jul 14 05:38:26 PM PDT 24
Peak memory 240060 kb
Host smart-de535d1f-a128-4ded-8957-ccb46e509175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004191421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2004191421 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.975733962
Short name T248
Test name
Test status
Simulation time 3173188585 ps
CPU time 38.05 seconds
Started Jul 14 05:34:22 PM PDT 24
Finished Jul 14 05:35:00 PM PDT 24
Peak memory 221740 kb
Host smart-befeae24-28e9-4956-bafe-8396dcea1229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975733962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.975733962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.1603239040
Short name T887
Test name
Test status
Simulation time 15366209832 ps
CPU time 1236.6 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:55:06 PM PDT 24
Peak memory 388704 kb
Host smart-ca02f0ae-f278-4c5a-8cb7-5cbe1cd09f28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1603239040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1603239040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.3910456622
Short name T204
Test name
Test status
Simulation time 69022167 ps
CPU time 3.8 seconds
Started Jul 14 05:34:23 PM PDT 24
Finished Jul 14 05:34:28 PM PDT 24
Peak memory 208764 kb
Host smart-c3122a28-b227-42d4-b974-b2eb783cada5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910456622 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.3910456622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.1465378489
Short name T595
Test name
Test status
Simulation time 68918436 ps
CPU time 3.89 seconds
Started Jul 14 05:34:25 PM PDT 24
Finished Jul 14 05:34:29 PM PDT 24
Peak memory 208648 kb
Host smart-a9840cb4-32e6-49a3-94d0-df677a21b71f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465378489 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.1465378489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.415464954
Short name T730
Test name
Test status
Simulation time 199763111778 ps
CPU time 2079.31 seconds
Started Jul 14 05:34:22 PM PDT 24
Finished Jul 14 06:09:02 PM PDT 24
Peak memory 402776 kb
Host smart-13b06167-5fd4-4d22-82d5-2f4cb44b86e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=415464954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.415464954 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.983535661
Short name T878
Test name
Test status
Simulation time 57370218034 ps
CPU time 1499.87 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 05:59:34 PM PDT 24
Peak memory 374856 kb
Host smart-c35c6d50-57b5-46b1-9695-b70d8404073a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=983535661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.983535661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.1586495049
Short name T678
Test name
Test status
Simulation time 124533986309 ps
CPU time 1361.72 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 05:57:09 PM PDT 24
Peak memory 335316 kb
Host smart-bacb7672-cd6f-4d59-a357-6a7acc733eb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1586495049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.1586495049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.958050596
Short name T900
Test name
Test status
Simulation time 38988488870 ps
CPU time 733.83 seconds
Started Jul 14 05:34:21 PM PDT 24
Finished Jul 14 05:46:35 PM PDT 24
Peak memory 291800 kb
Host smart-2a9118cb-5f3d-4918-94d0-f63e20e5bda8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=958050596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.958050596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.1918951645
Short name T723
Test name
Test status
Simulation time 2879187339782 ps
CPU time 5539.07 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 07:06:54 PM PDT 24
Peak memory 655832 kb
Host smart-3eaaaccb-31f9-4561-ba86-733933fd05ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1918951645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.1918951645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.2787633465
Short name T498
Test name
Test status
Simulation time 605938225695 ps
CPU time 3702.38 seconds
Started Jul 14 05:34:24 PM PDT 24
Finished Jul 14 06:36:08 PM PDT 24
Peak memory 561320 kb
Host smart-e8b359c9-0dc1-48e0-a4cb-41c1fa5b8347
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2787633465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.2787633465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.2779739331
Short name T826
Test name
Test status
Simulation time 15442752 ps
CPU time 0.74 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:37 PM PDT 24
Peak memory 205288 kb
Host smart-73d22283-ada3-42d8-8938-a3fd1920f87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779739331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2779739331 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.4043954361
Short name T839
Test name
Test status
Simulation time 33458624412 ps
CPU time 160.12 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:37:09 PM PDT 24
Peak memory 235248 kb
Host smart-ddc31ea1-3ad5-45b9-a6ca-aaa9c562dbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043954361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.4043954361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.1988516301
Short name T717
Test name
Test status
Simulation time 8413192982 ps
CPU time 186.86 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:37:36 PM PDT 24
Peak memory 240592 kb
Host smart-5533f06f-721f-4106-bd87-bb41dded6e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988516301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1988516301 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.3497576807
Short name T939
Test name
Test status
Simulation time 16838701026 ps
CPU time 206.8 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:37:57 PM PDT 24
Peak memory 224504 kb
Host smart-42ff2ce7-28b8-4045-a7b6-8103b48e2e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497576807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3497576807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.623754569
Short name T511
Test name
Test status
Simulation time 4840497093 ps
CPU time 21.71 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:34:50 PM PDT 24
Peak memory 223744 kb
Host smart-b30b6e15-4552-498e-bd98-eb4fced8f7dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=623754569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.623754569 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.432878190
Short name T186
Test name
Test status
Simulation time 462028539 ps
CPU time 9.45 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 05:34:50 PM PDT 24
Peak memory 223564 kb
Host smart-816d50f3-8de1-48bc-bc14-2b3f0538e8c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=432878190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.432878190 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3894556710
Short name T356
Test name
Test status
Simulation time 1541196179 ps
CPU time 23.34 seconds
Started Jul 14 05:34:27 PM PDT 24
Finished Jul 14 05:34:51 PM PDT 24
Peak memory 216688 kb
Host smart-53015093-4028-4392-9222-af1dfba2f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894556710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3894556710 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.2351728167
Short name T344
Test name
Test status
Simulation time 10541367572 ps
CPU time 239.5 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:38:28 PM PDT 24
Peak memory 241388 kb
Host smart-bbdc63d9-e08f-41d2-87d9-e4056f55a1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351728167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2351728167 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.293151050
Short name T904
Test name
Test status
Simulation time 20361788531 ps
CPU time 291.89 seconds
Started Jul 14 05:34:31 PM PDT 24
Finished Jul 14 05:39:24 PM PDT 24
Peak memory 264828 kb
Host smart-cc377bae-55b5-42a2-ae72-53d8be726349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293151050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.293151050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.3834285967
Short name T501
Test name
Test status
Simulation time 5379691860 ps
CPU time 7.7 seconds
Started Jul 14 05:34:31 PM PDT 24
Finished Jul 14 05:34:39 PM PDT 24
Peak memory 207284 kb
Host smart-9db51882-e966-492d-8d09-065383364d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834285967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3834285967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1323205394
Short name T666
Test name
Test status
Simulation time 79385246 ps
CPU time 1.14 seconds
Started Jul 14 05:34:31 PM PDT 24
Finished Jul 14 05:34:33 PM PDT 24
Peak memory 215432 kb
Host smart-650e3af1-1311-469b-bd1a-39921e4809a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323205394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1323205394 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.4254637787
Short name T81
Test name
Test status
Simulation time 90842347975 ps
CPU time 1755.64 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 06:03:46 PM PDT 24
Peak memory 422848 kb
Host smart-680cdc0e-7484-4868-86e6-f5caa6603ebe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254637787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.4254637787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.1665741286
Short name T358
Test name
Test status
Simulation time 19548837300 ps
CPU time 239.21 seconds
Started Jul 14 05:34:26 PM PDT 24
Finished Jul 14 05:38:26 PM PDT 24
Peak memory 247028 kb
Host smart-472632a0-ef69-4199-a558-ec772334c5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665741286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1665741286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.2095930954
Short name T424
Test name
Test status
Simulation time 77251705754 ps
CPU time 182.61 seconds
Started Jul 14 05:34:39 PM PDT 24
Finished Jul 14 05:37:42 PM PDT 24
Peak memory 231284 kb
Host smart-051c39fe-aa6f-429b-b42c-b4646eee2989
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095930954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2095930954 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.3778508243
Short name T779
Test name
Test status
Simulation time 1002985298 ps
CPU time 28.59 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:35:00 PM PDT 24
Peak memory 223760 kb
Host smart-070083b0-1378-47ab-a8fc-2a6eb87e2ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778508243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3778508243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.1967621100
Short name T21
Test name
Test status
Simulation time 12635379066 ps
CPU time 510.18 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 05:43:10 PM PDT 24
Peak memory 301004 kb
Host smart-102dd249-405f-4336-bd21-a668ecaa6673
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1967621100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1967621100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.371947074
Short name T455
Test name
Test status
Simulation time 210199854 ps
CPU time 4.16 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 05:34:38 PM PDT 24
Peak memory 215604 kb
Host smart-4317a1ea-1063-47db-8a10-43174dbbc82c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371947074 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.kmac_test_vectors_kmac.371947074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3722612405
Short name T18
Test name
Test status
Simulation time 669751140 ps
CPU time 4.78 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 05:34:45 PM PDT 24
Peak memory 215520 kb
Host smart-1a08728e-a5cf-472e-89d7-a0904e168965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722612405 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3722612405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.314725091
Short name T374
Test name
Test status
Simulation time 373002819167 ps
CPU time 1946.41 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 06:07:01 PM PDT 24
Peak memory 399140 kb
Host smart-e067cc8e-0d37-4e3c-bfad-7daf7571a258
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=314725091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.314725091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.583882504
Short name T345
Test name
Test status
Simulation time 158914664382 ps
CPU time 1699.83 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 06:02:50 PM PDT 24
Peak memory 378980 kb
Host smart-21381f97-243f-42a7-8111-3a629b69d4d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=583882504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.583882504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.3731205562
Short name T395
Test name
Test status
Simulation time 57280335032 ps
CPU time 1141.84 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:53:33 PM PDT 24
Peak memory 337400 kb
Host smart-ba580e22-7c41-4063-81a6-6a472154964c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3731205562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3731205562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.2816984171
Short name T73
Test name
Test status
Simulation time 128668750649 ps
CPU time 926.05 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:49:56 PM PDT 24
Peak memory 292232 kb
Host smart-5e4633a2-64a1-489d-a7d8-20a3d0122f89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2816984171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.2816984171 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.3118141481
Short name T565
Test name
Test status
Simulation time 53313300160 ps
CPU time 3960.54 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 06:40:31 PM PDT 24
Peak memory 657976 kb
Host smart-be76cb39-eb32-41f4-bfb7-f0f1b7a6c492
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3118141481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.3118141481 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.1391616913
Short name T341
Test name
Test status
Simulation time 89101961925 ps
CPU time 3347.01 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 06:30:21 PM PDT 24
Peak memory 568312 kb
Host smart-d6f1a6e6-30d6-4b8c-9402-44891b5a82ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1391616913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.1391616913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.986470313
Short name T879
Test name
Test status
Simulation time 30747823 ps
CPU time 0.78 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:37 PM PDT 24
Peak memory 205256 kb
Host smart-10d68adb-4dbf-462d-a117-0fbf99d83002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986470313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.986470313 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3693567775
Short name T896
Test name
Test status
Simulation time 122163413721 ps
CPU time 269.67 seconds
Started Jul 14 05:34:31 PM PDT 24
Finished Jul 14 05:39:02 PM PDT 24
Peak memory 242488 kb
Host smart-2f734a20-57a0-4afb-a782-c547b89aa9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693567775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3693567775 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.3870572322
Short name T902
Test name
Test status
Simulation time 45796242966 ps
CPU time 232.72 seconds
Started Jul 14 05:34:31 PM PDT 24
Finished Jul 14 05:38:24 PM PDT 24
Peak memory 242956 kb
Host smart-d07292ce-61cd-49bf-b4ba-d09488f753a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870572322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3870572322 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.3400375061
Short name T382
Test name
Test status
Simulation time 103822914515 ps
CPU time 574.76 seconds
Started Jul 14 05:34:30 PM PDT 24
Finished Jul 14 05:44:06 PM PDT 24
Peak memory 230016 kb
Host smart-47de89a4-113b-4428-8673-0968ec52ba37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400375061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3400375061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.3848488887
Short name T612
Test name
Test status
Simulation time 1036432873 ps
CPU time 17.98 seconds
Started Jul 14 05:34:34 PM PDT 24
Finished Jul 14 05:34:53 PM PDT 24
Peak memory 220572 kb
Host smart-0a7c4d49-1691-4119-8318-44869b66bff0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3848488887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3848488887 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2595856166
Short name T845
Test name
Test status
Simulation time 81187757 ps
CPU time 6.32 seconds
Started Jul 14 05:34:28 PM PDT 24
Finished Jul 14 05:34:36 PM PDT 24
Peak memory 219004 kb
Host smart-1f26acfe-272f-4ddb-b544-3c71382f86cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2595856166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2595856166 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.623260563
Short name T41
Test name
Test status
Simulation time 4205345463 ps
CPU time 36.54 seconds
Started Jul 14 05:34:34 PM PDT 24
Finished Jul 14 05:35:11 PM PDT 24
Peak memory 216664 kb
Host smart-1437851f-68f1-4671-925d-afe862f914fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623260563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.623260563 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.3417101382
Short name T600
Test name
Test status
Simulation time 21260067933 ps
CPU time 242.42 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:38:33 PM PDT 24
Peak memory 240400 kb
Host smart-b8ba8177-66da-46bb-b405-742fac6db01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417101382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3417101382 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.3189059475
Short name T412
Test name
Test status
Simulation time 662362209 ps
CPU time 13.92 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:34:45 PM PDT 24
Peak memory 223692 kb
Host smart-8ab67619-31d6-4996-a552-8c79e1049d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189059475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3189059475 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.2639475316
Short name T67
Test name
Test status
Simulation time 7088888967 ps
CPU time 10.46 seconds
Started Jul 14 05:34:34 PM PDT 24
Finished Jul 14 05:34:45 PM PDT 24
Peak memory 207360 kb
Host smart-207185b1-f04f-4472-bd9f-69290260dc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639475316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2639475316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.1406767947
Short name T669
Test name
Test status
Simulation time 167338871 ps
CPU time 1.43 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:34:39 PM PDT 24
Peak memory 215520 kb
Host smart-5946eec9-f72e-4795-8ab9-5c33e5ba6878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406767947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1406767947 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.1876106781
Short name T756
Test name
Test status
Simulation time 88334529543 ps
CPU time 2495.9 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 06:16:07 PM PDT 24
Peak memory 460176 kb
Host smart-dcab9f47-4521-4a2f-aa42-61cdaff60afa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876106781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.1876106781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.2949715840
Short name T312
Test name
Test status
Simulation time 13749390153 ps
CPU time 66.1 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:35:37 PM PDT 24
Peak memory 224332 kb
Host smart-2f9f055f-110b-4859-a02a-5e5bcf26a146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949715840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2949715840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.2544041888
Short name T334
Test name
Test status
Simulation time 12202554425 ps
CPU time 342.59 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:40:14 PM PDT 24
Peak memory 245280 kb
Host smart-1293ca66-79dd-4cf5-973d-cb76f72055b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544041888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2544041888 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3617368646
Short name T890
Test name
Test status
Simulation time 498247088 ps
CPU time 26.04 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:35:02 PM PDT 24
Peak memory 218236 kb
Host smart-01d1a7de-c595-4458-aa66-52581bea2877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617368646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3617368646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.964971124
Short name T931
Test name
Test status
Simulation time 927786871 ps
CPU time 4.8 seconds
Started Jul 14 05:34:31 PM PDT 24
Finished Jul 14 05:34:36 PM PDT 24
Peak memory 215588 kb
Host smart-1a2aabc4-a118-4d03-b4de-118ab46d637c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964971124 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.kmac_test_vectors_kmac.964971124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2476876576
Short name T611
Test name
Test status
Simulation time 226828382 ps
CPU time 4.03 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:34:35 PM PDT 24
Peak memory 215496 kb
Host smart-f13a8fe9-b644-4ba9-bc68-7528c8b2e8b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476876576 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2476876576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.872231126
Short name T555
Test name
Test status
Simulation time 150917692587 ps
CPU time 1929.16 seconds
Started Jul 14 05:34:39 PM PDT 24
Finished Jul 14 06:06:49 PM PDT 24
Peak memory 370668 kb
Host smart-24f522ec-b011-499a-bab2-54e1d5c4d953
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=872231126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.872231126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.1852691270
Short name T975
Test name
Test status
Simulation time 54218460558 ps
CPU time 1157.48 seconds
Started Jul 14 05:34:29 PM PDT 24
Finished Jul 14 05:53:48 PM PDT 24
Peak memory 333508 kb
Host smart-cad3c522-e8ce-4475-be26-42776b5f0619
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1852691270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.1852691270 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.3511141489
Short name T586
Test name
Test status
Simulation time 21506339590 ps
CPU time 764.31 seconds
Started Jul 14 05:34:32 PM PDT 24
Finished Jul 14 05:47:18 PM PDT 24
Peak memory 294496 kb
Host smart-aee8a436-c612-4d01-a0a8-e78eef2418f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3511141489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.3511141489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.2487323069
Short name T724
Test name
Test status
Simulation time 262328895657 ps
CPU time 4928.56 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 06:56:49 PM PDT 24
Peak memory 631716 kb
Host smart-5fb96391-da9f-48cb-984a-d88416ff2b3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2487323069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.2487323069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.3581286930
Short name T425
Test name
Test status
Simulation time 219247869606 ps
CPU time 4335.15 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 06:46:50 PM PDT 24
Peak memory 561808 kb
Host smart-0bcfbe55-989a-4cae-aa4c-1d48f127b435
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3581286930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.3581286930 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.2637274638
Short name T231
Test name
Test status
Simulation time 25471598 ps
CPU time 0.83 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:37 PM PDT 24
Peak memory 205228 kb
Host smart-086bb875-0090-42cb-8a3d-ba67f11866c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637274638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2637274638 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.3037798626
Short name T977
Test name
Test status
Simulation time 68846020379 ps
CPU time 246.65 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:38:43 PM PDT 24
Peak memory 244236 kb
Host smart-675e3034-6dcb-4960-ab0a-531e89634f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037798626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3037798626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.1066581899
Short name T1015
Test name
Test status
Simulation time 7513827796 ps
CPU time 287.2 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:39:25 PM PDT 24
Peak memory 245192 kb
Host smart-5ca1bca2-770e-42a0-96c3-6496ac216a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066581899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1066581899 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.3274297738
Short name T974
Test name
Test status
Simulation time 25682604699 ps
CPU time 326.81 seconds
Started Jul 14 05:34:34 PM PDT 24
Finished Jul 14 05:40:02 PM PDT 24
Peak memory 227572 kb
Host smart-0e7d91dc-c6df-4a35-a6ee-b84210d23be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274297738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3274297738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.3186896428
Short name T672
Test name
Test status
Simulation time 4200934312 ps
CPU time 22.7 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 05:34:56 PM PDT 24
Peak memory 220068 kb
Host smart-7c16a55c-98cb-4f26-85c8-718fdc45cc8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3186896428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3186896428 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.588850893
Short name T858
Test name
Test status
Simulation time 3927837256 ps
CPU time 36.46 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 05:35:17 PM PDT 24
Peak memory 220152 kb
Host smart-b8fc4606-70d7-463b-91a0-c9f8d175df38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=588850893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.588850893 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.902383080
Short name T283
Test name
Test status
Simulation time 5957829669 ps
CPU time 18.27 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:34:56 PM PDT 24
Peak memory 215584 kb
Host smart-6c2a11d3-a043-4d22-bd8d-e2609ec1af23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902383080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.902383080 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.1524220969
Short name T325
Test name
Test status
Simulation time 11547222472 ps
CPU time 201.51 seconds
Started Jul 14 05:34:38 PM PDT 24
Finished Jul 14 05:38:01 PM PDT 24
Peak memory 235040 kb
Host smart-888590f8-e9c7-4e1d-907b-91c6fade594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524220969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1524220969 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.4117763005
Short name T889
Test name
Test status
Simulation time 29830339220 ps
CPU time 150.91 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 05:37:10 PM PDT 24
Peak memory 248452 kb
Host smart-1a573473-da86-42ac-a8b5-98650f694b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117763005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.4117763005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.1350815056
Short name T973
Test name
Test status
Simulation time 1106832814 ps
CPU time 6.12 seconds
Started Jul 14 05:34:36 PM PDT 24
Finished Jul 14 05:34:44 PM PDT 24
Peak memory 215452 kb
Host smart-2f235495-7d85-4bd1-80d5-6314c2d19fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350815056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1350815056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.2273728587
Short name T479
Test name
Test status
Simulation time 32841984 ps
CPU time 1.21 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:38 PM PDT 24
Peak memory 215508 kb
Host smart-082584b0-f94c-47e9-a707-fce0217f8efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273728587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2273728587 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.1222374970
Short name T782
Test name
Test status
Simulation time 186140163290 ps
CPU time 2564.52 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 06:17:26 PM PDT 24
Peak memory 474240 kb
Host smart-3d6de7bf-32c4-496c-9047-065852383261
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222374970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.1222374970 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.2600401979
Short name T512
Test name
Test status
Simulation time 6536592101 ps
CPU time 136.38 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 05:36:55 PM PDT 24
Peak memory 231080 kb
Host smart-1ffce1af-82c2-4bd5-a0aa-54752cf2b86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600401979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2600401979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.3428900343
Short name T1027
Test name
Test status
Simulation time 15746759234 ps
CPU time 313.38 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:39:49 PM PDT 24
Peak memory 246804 kb
Host smart-8482429a-29d6-42d5-886f-e1cd80731020
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428900343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3428900343 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1101312
Short name T834
Test name
Test status
Simulation time 1288943541 ps
CPU time 25.49 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 05:35:04 PM PDT 24
Peak memory 215928 kb
Host smart-4201e3f2-58ac-4431-8490-97b189d19b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1101312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.3898401700
Short name T570
Test name
Test status
Simulation time 246204052294 ps
CPU time 1136.36 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 05:53:31 PM PDT 24
Peak memory 333560 kb
Host smart-dc413560-cc8f-45a0-a0ea-f165c2fa4d36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3898401700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3898401700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3144734019
Short name T1013
Test name
Test status
Simulation time 69739756 ps
CPU time 3.92 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:34:40 PM PDT 24
Peak memory 215616 kb
Host smart-e537e026-64d9-4373-bf42-6923b4b1a8c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144734019 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3144734019 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.8056847
Short name T335
Test name
Test status
Simulation time 233583291 ps
CPU time 4.67 seconds
Started Jul 14 05:34:40 PM PDT 24
Finished Jul 14 05:34:46 PM PDT 24
Peak memory 215536 kb
Host smart-e23529e1-b995-41f2-a33d-db30b7d987fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8056847 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.kmac_test_vectors_kmac_xof.8056847 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.2394067886
Short name T349
Test name
Test status
Simulation time 19255713228 ps
CPU time 1562.01 seconds
Started Jul 14 05:34:34 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 388684 kb
Host smart-2a3cf38f-f3ec-4ede-85ae-272f9446c3a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2394067886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.2394067886 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.1337129516
Short name T298
Test name
Test status
Simulation time 403495894571 ps
CPU time 1828.88 seconds
Started Jul 14 05:34:33 PM PDT 24
Finished Jul 14 06:05:03 PM PDT 24
Peak memory 363592 kb
Host smart-e1557dde-cf7d-406a-a2b6-94f3f30312c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1337129516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.1337129516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.1348532866
Short name T946
Test name
Test status
Simulation time 59981857127 ps
CPU time 1194.62 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 05:54:31 PM PDT 24
Peak memory 338272 kb
Host smart-cd6c8c0c-b100-45aa-bd5c-01ab8be50893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1348532866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.1348532866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.1805201358
Short name T1059
Test name
Test status
Simulation time 18320599319 ps
CPU time 778.2 seconds
Started Jul 14 05:34:37 PM PDT 24
Finished Jul 14 05:47:37 PM PDT 24
Peak memory 295428 kb
Host smart-04ab267e-b4e1-49cb-bac9-8d24c467c381
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1805201358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.1805201358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.194111762
Short name T598
Test name
Test status
Simulation time 178704091353 ps
CPU time 4637.73 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 06:51:54 PM PDT 24
Peak memory 647708 kb
Host smart-7fac4cd3-242c-4260-8cbc-d494b6ec928f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=194111762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.194111762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.1500774561
Short name T313
Test name
Test status
Simulation time 381241971165 ps
CPU time 4126.73 seconds
Started Jul 14 05:34:35 PM PDT 24
Finished Jul 14 06:43:24 PM PDT 24
Peak memory 572448 kb
Host smart-ebd51bfd-75db-474c-b5a5-02e0da480665
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1500774561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1500774561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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