Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99708060	1			T1	222907		T2	114552		T3	570645
all_values[1]	99708060	1			T1	222907		T2	114552		T3	570645
all_values[2]	99708060	1			T1	222907		T2	114552		T3	570645

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

450452

1

T1

27

T2

13954

T3

10

auto[1]

298673728

1

T1

668694

T2

329702

T3

171192

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297598653

1

T1

666945

T2

343338

T3

170141

auto[1]

1525527

1

T1

1776

T2

318

T3

10524

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	160269	1			T1	1		T2	2458		T3	3
all_values[0]	auto[0]	auto[1]	2112	1			T1	2		T2	2		T3	4
all_values[0]	auto[1]	auto[0]	99039282	1			T1	222314		T2	111988		T3	567134
all_values[0]	auto[1]	auto[1]	506397	1			T1	590		T2	104		T3	3504
all_values[1]	auto[0]	auto[0]	130774	1			T1	1		T2	11488		T3	1
all_values[1]	auto[0]	auto[1]	1464	1			T1	2		T2	6		T3	2
all_values[1]	auto[1]	auto[0]	99068777	1			T1	222314		T2	102958		T3	567136
all_values[1]	auto[1]	auto[1]	507045	1			T1	590		T2	100		T3	3506
all_values[2]	auto[0]	auto[0]	154291	1			T1	13		T13	31		T15	16
all_values[2]	auto[0]	auto[1]	1542	1			T1	8		T13	4		T15	2
all_values[2]	auto[1]	auto[0]	99045260	1			T1	222302		T2	114446		T3	567137
all_values[2]	auto[1]	auto[1]	506967	1			T1	584		T2	106		T3	3508