Summary for Variable key_len
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for key_len
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Key128] |
65801 |
1 |
|
|
T1 |
75 |
|
T2 |
15 |
|
T3 |
466 |
auto[Key192] |
66035 |
1 |
|
|
T1 |
89 |
|
T2 |
16 |
|
T3 |
484 |
auto[Key256] |
80437 |
1 |
|
|
T1 |
87 |
|
T2 |
16 |
|
T3 |
431 |
auto[Key384] |
66200 |
1 |
|
|
T1 |
72 |
|
T2 |
12 |
|
T3 |
463 |
auto[Key512] |
65812 |
1 |
|
|
T1 |
67 |
|
T2 |
10 |
|
T3 |
493 |
Summary for Variable kmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
311827 |
1 |
|
|
T1 |
390 |
|
T2 |
16 |
|
T3 |
2337 |
auto[1] |
32458 |
1 |
|
|
T2 |
53 |
|
T13 |
64 |
|
T14 |
36 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
67243 |
1 |
|
|
T1 |
390 |
|
T13 |
4 |
|
T14 |
10 |
auto[Shake] |
241552 |
1 |
|
|
T2 |
16 |
|
T3 |
2337 |
|
T13 |
29 |
auto[CShake] |
35490 |
1 |
|
|
T2 |
53 |
|
T13 |
78 |
|
T14 |
36 |
Summary for Variable msg_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for msg_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171688 |
1 |
|
|
T1 |
178 |
|
T2 |
32 |
|
T3 |
1184 |
auto[1] |
172597 |
1 |
|
|
T1 |
212 |
|
T2 |
37 |
|
T3 |
1153 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333991 |
1 |
|
|
T1 |
390 |
|
T2 |
69 |
|
T3 |
2337 |
auto[1] |
10294 |
1 |
|
|
T13 |
25 |
|
T16 |
17 |
|
T18 |
9 |
Summary for Variable state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172139 |
1 |
|
|
T1 |
198 |
|
T2 |
32 |
|
T3 |
1172 |
auto[1] |
172146 |
1 |
|
|
T1 |
192 |
|
T2 |
37 |
|
T3 |
1165 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
138730 |
1 |
|
|
T2 |
31 |
|
T3 |
2337 |
|
T13 |
45 |
auto[L224] |
19815 |
1 |
|
|
T1 |
390 |
|
T13 |
1 |
|
T14 |
2 |
auto[L256] |
157320 |
1 |
|
|
T2 |
38 |
|
T13 |
63 |
|
T14 |
30 |
auto[L384] |
15802 |
1 |
|
|
T14 |
2 |
|
T15 |
3 |
|
T16 |
1 |
auto[L512] |
12618 |
1 |
|
|
T13 |
2 |
|
T14 |
2 |
|
T15 |
3 |
Summary for Variable xof_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for xof_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
325913 |
1 |
|
|
T1 |
390 |
|
T2 |
34 |
|
T3 |
2337 |
auto[1] |
18372 |
1 |
|
|
T2 |
35 |
|
T13 |
35 |
|
T14 |
19 |
Summary for Cross kmac_cross
Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for kmac_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
32458 |
1 |
|
|
T2 |
53 |
|
T13 |
64 |
|
T14 |
36 |
Summary for Cross cshake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for cshake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
35490 |
1 |
|
|
T2 |
53 |
|
T13 |
78 |
|
T14 |
36 |
Summary for Cross shake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for shake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
241552 |
1 |
|
|
T2 |
16 |
|
T3 |
2337 |
|
T13 |
29 |
Summary for Cross sha3_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for sha3_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
67243 |
1 |
|
|
T1 |
390 |
|
T13 |
4 |
|
T14 |
10 |