Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335112 |
1 |
|
|
T1 |
780 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
355568 |
1 |
|
|
T2 |
136 |
|
T3 |
4672 |
|
T13 |
156 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173238 |
1 |
|
|
T1 |
170 |
|
T2 |
28 |
|
T3 |
1172 |
lower_val |
171193 |
1 |
|
|
T1 |
197 |
|
T2 |
35 |
|
T3 |
1173 |
zero_val |
1770 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
7 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345338 |
1 |
|
|
T1 |
374 |
|
T2 |
72 |
|
T3 |
2238 |
lower_val |
345324 |
1 |
|
|
T1 |
406 |
|
T2 |
66 |
|
T3 |
2436 |
zero_val |
18 |
1 |
|
|
T70 |
2 |
|
T158 |
2 |
|
T159 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41935 |
1 |
|
|
T1 |
84 |
|
T13 |
10 |
|
T14 |
8 |
higher_val |
higher_val |
auto[1] |
44495 |
1 |
|
|
T2 |
17 |
|
T3 |
558 |
|
T13 |
19 |
higher_val |
lower_val |
auto[0] |
41778 |
1 |
|
|
T1 |
86 |
|
T13 |
5 |
|
T14 |
13 |
higher_val |
lower_val |
auto[1] |
45025 |
1 |
|
|
T2 |
11 |
|
T3 |
614 |
|
T13 |
23 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T159 |
1 |
|
T160 |
1 |
|
T161 |
1 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T162 |
1 |
|
T163 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
42025 |
1 |
|
|
T1 |
88 |
|
T13 |
7 |
|
T14 |
12 |
lower_val |
higher_val |
auto[1] |
43833 |
1 |
|
|
T2 |
21 |
|
T3 |
546 |
|
T13 |
18 |
lower_val |
lower_val |
auto[0] |
41260 |
1 |
|
|
T1 |
109 |
|
T13 |
4 |
|
T14 |
18 |
lower_val |
lower_val |
auto[1] |
44070 |
1 |
|
|
T2 |
14 |
|
T3 |
627 |
|
T13 |
18 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T158 |
1 |
|
T159 |
1 |
|
T164 |
1 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T70 |
1 |
|
T163 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
641 |
1 |
|
|
T13 |
2 |
|
T14 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
228 |
1 |
|
|
T3 |
5 |
|
T70 |
1 |
|
T38 |
2 |
zero_val |
lower_val |
auto[0] |
653 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
248 |
1 |
|
|
T3 |
1 |
|
T13 |
2 |
|
T35 |
2 |