Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99708060	1			T1	222907		T2	114552		T3	570645
all_pins[1]	99708060	1			T1	222907		T2	114552		T3	570645
all_pins[2]	99708060	1			T1	222907		T2	114552		T3	570645

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298362785	1			T1	668131		T2	343552		T3	170843
values[0x1]	761395	1			T1	590		T2	104		T3	3504
transitions[0x0=>0x1]	759849	1			T1	590		T2	104		T3	3504
transitions[0x1=>0x0]	759873	1			T1	590		T2	104		T3	3504

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99201663	1			T1	222317		T2	114448		T3	567141
all_pins[0]	values[0x1]	506397	1			T1	590		T2	104		T3	3504
all_pins[0]	transitions[0x0=>0x1]	506383	1			T1	590		T2	104		T3	3504
all_pins[0]	transitions[0x1=>0x0]	71	1			T41	4		T170	3		T171	4
all_pins[1]	values[0x0]	99707975	1			T1	222907		T2	114552		T3	570645
all_pins[1]	values[0x1]	85	1			T41	4		T170	3		T171	4
all_pins[1]	transitions[0x0=>0x1]	73	1			T41	4		T170	3		T171	4
all_pins[1]	transitions[0x1=>0x0]	254901	1			T13	1695		T19	2074		T27	145
all_pins[2]	values[0x0]	99453147	1			T1	222907		T2	114552		T3	570645
all_pins[2]	values[0x1]	254913	1			T13	1695		T19	2074		T27	145
all_pins[2]	transitions[0x0=>0x1]	253393	1			T13	1683		T19	2061		T27	145
all_pins[2]	transitions[0x1=>0x0]	504901	1			T1	590		T2	104		T3	3504