Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
338943 |
1 |
|
|
T1 |
378 |
|
T2 |
69 |
|
T3 |
2270 |
auto[1] |
3083 |
1 |
|
|
T13 |
16 |
|
T16 |
19 |
|
T18 |
10 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
306004 |
1 |
|
|
T1 |
378 |
|
T2 |
16 |
|
T3 |
2270 |
auto[1] |
36022 |
1 |
|
|
T2 |
53 |
|
T13 |
80 |
|
T14 |
35 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
328559 |
1 |
|
|
T1 |
378 |
|
T2 |
69 |
|
T3 |
2270 |
auto[1] |
13467 |
1 |
|
|
T13 |
41 |
|
T16 |
36 |
|
T18 |
19 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13467 |
1 |
|
|
T13 |
41 |
|
T16 |
36 |
|
T18 |
19 |
sw_kmac_invalid_sideload |
328559 |
1 |
|
|
T1 |
378 |
|
T2 |
69 |
|
T3 |
2270 |
app_valid_sideload |
13467 |
1 |
|
|
T13 |
41 |
|
T16 |
36 |
|
T18 |
19 |
app_invalid_sideload |
328559 |
1 |
|
|
T1 |
378 |
|
T2 |
69 |
|
T3 |
2270 |