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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.78 95.77 90.51 100.00 66.94 93.67 98.84 96.72


Total test records in report: 1231
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T1068 /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.4190462009 Jul 15 06:34:39 PM PDT 24 Jul 15 06:34:45 PM PDT 24 1230506006 ps
T1069 /workspace/coverage/default/2.kmac_test_vectors_shake_256.407451111 Jul 15 06:32:39 PM PDT 24 Jul 15 07:43:57 PM PDT 24 314534650262 ps
T57 /workspace/coverage/default/10.kmac_lc_escalation.3542799680 Jul 15 06:33:23 PM PDT 24 Jul 15 06:33:46 PM PDT 24 929047349 ps
T1070 /workspace/coverage/default/42.kmac_test_vectors_kmac.1948898861 Jul 15 06:39:32 PM PDT 24 Jul 15 06:39:37 PM PDT 24 64187853 ps
T1071 /workspace/coverage/default/1.kmac_burst_write.3035331712 Jul 15 06:32:38 PM PDT 24 Jul 15 06:45:49 PM PDT 24 52619379641 ps
T1072 /workspace/coverage/default/49.kmac_sideload.4112952108 Jul 15 06:41:33 PM PDT 24 Jul 15 06:46:01 PM PDT 24 14773183273 ps
T1073 /workspace/coverage/default/14.kmac_test_vectors_shake_256.3923355194 Jul 15 06:33:51 PM PDT 24 Jul 15 07:39:49 PM PDT 24 387876226264 ps
T1074 /workspace/coverage/default/0.kmac_test_vectors_kmac.4138144904 Jul 15 06:32:34 PM PDT 24 Jul 15 06:32:40 PM PDT 24 425651356 ps
T58 /workspace/coverage/default/48.kmac_lc_escalation.411501843 Jul 15 06:41:25 PM PDT 24 Jul 15 06:41:44 PM PDT 24 989230588 ps
T1075 /workspace/coverage/default/10.kmac_key_error.3297395714 Jul 15 06:33:16 PM PDT 24 Jul 15 06:33:21 PM PDT 24 3236474743 ps
T1076 /workspace/coverage/default/26.kmac_test_vectors_sha3_256.3794393599 Jul 15 06:35:45 PM PDT 24 Jul 15 07:04:49 PM PDT 24 78993406612 ps
T1077 /workspace/coverage/default/14.kmac_smoke.2271658575 Jul 15 06:33:47 PM PDT 24 Jul 15 06:34:11 PM PDT 24 1499452526 ps
T1078 /workspace/coverage/default/9.kmac_app_with_partial_data.2467949188 Jul 15 06:33:12 PM PDT 24 Jul 15 06:33:26 PM PDT 24 1078603424 ps
T1079 /workspace/coverage/default/39.kmac_burst_write.2699120253 Jul 15 06:38:42 PM PDT 24 Jul 15 06:47:05 PM PDT 24 85295190806 ps
T1080 /workspace/coverage/default/0.kmac_long_msg_and_output.4162614344 Jul 15 06:32:29 PM PDT 24 Jul 15 06:51:04 PM PDT 24 41541540539 ps
T1081 /workspace/coverage/default/12.kmac_entropy_mode_error.2208954352 Jul 15 06:33:34 PM PDT 24 Jul 15 06:33:42 PM PDT 24 682133908 ps
T1082 /workspace/coverage/default/22.kmac_alert_test.2047194702 Jul 15 06:35:03 PM PDT 24 Jul 15 06:35:05 PM PDT 24 14737351 ps
T120 /workspace/coverage/cover_reg_top/12.kmac_intr_test.2883245600 Jul 15 07:23:20 PM PDT 24 Jul 15 07:24:24 PM PDT 24 47553764 ps
T95 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2476999818 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:19 PM PDT 24 88435699 ps
T53 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1688878906 Jul 15 07:23:26 PM PDT 24 Jul 15 07:24:28 PM PDT 24 31453591 ps
T54 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2990095444 Jul 15 07:23:09 PM PDT 24 Jul 15 07:24:20 PM PDT 24 314616468 ps
T55 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.634630094 Jul 15 07:23:49 PM PDT 24 Jul 15 07:24:43 PM PDT 24 246281598 ps
T121 /workspace/coverage/cover_reg_top/34.kmac_intr_test.1998791286 Jul 15 07:23:58 PM PDT 24 Jul 15 07:24:44 PM PDT 24 44166362 ps
T98 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.321850351 Jul 15 07:23:18 PM PDT 24 Jul 15 07:24:26 PM PDT 24 72039512 ps
T122 /workspace/coverage/cover_reg_top/43.kmac_intr_test.1447235390 Jul 15 07:24:05 PM PDT 24 Jul 15 07:24:48 PM PDT 24 14719342 ps
T1083 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2306716926 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:14 PM PDT 24 46877925 ps
T113 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2554046642 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:24 PM PDT 24 255263795 ps
T96 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1032843811 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:22 PM PDT 24 570260044 ps
T106 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1599962203 Jul 15 07:23:05 PM PDT 24 Jul 15 07:24:15 PM PDT 24 118643162 ps
T115 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1286878519 Jul 15 07:23:31 PM PDT 24 Jul 15 07:24:30 PM PDT 24 41252710 ps
T165 /workspace/coverage/cover_reg_top/31.kmac_intr_test.683356106 Jul 15 07:23:53 PM PDT 24 Jul 15 07:24:43 PM PDT 24 15314247 ps
T107 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3573435045 Jul 15 07:23:37 PM PDT 24 Jul 15 07:24:32 PM PDT 24 19314469 ps
T97 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3854783912 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:42 PM PDT 24 280982977 ps
T1084 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.3497465618 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:18 PM PDT 24 27921213 ps
T1085 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2309434611 Jul 15 07:22:56 PM PDT 24 Jul 15 07:24:24 PM PDT 24 963408827 ps
T116 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.792600887 Jul 15 07:22:55 PM PDT 24 Jul 15 07:24:08 PM PDT 24 72759976 ps
T100 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.724324337 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:17 PM PDT 24 56588896 ps
T1086 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.10966634 Jul 15 07:23:38 PM PDT 24 Jul 15 07:24:35 PM PDT 24 26481020 ps
T1087 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2667718852 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:22 PM PDT 24 842164787 ps
T114 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3257293706 Jul 15 07:23:18 PM PDT 24 Jul 15 07:24:29 PM PDT 24 485453266 ps
T108 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1730267887 Jul 15 07:23:38 PM PDT 24 Jul 15 07:24:34 PM PDT 24 59724048 ps
T1088 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.369038610 Jul 15 07:22:55 PM PDT 24 Jul 15 07:24:04 PM PDT 24 20544877 ps
T1089 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3486877269 Jul 15 07:23:05 PM PDT 24 Jul 15 07:24:15 PM PDT 24 29003249 ps
T99 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4131121455 Jul 15 07:23:20 PM PDT 24 Jul 15 07:24:26 PM PDT 24 760506322 ps
T126 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2512621518 Jul 15 07:23:19 PM PDT 24 Jul 15 07:24:26 PM PDT 24 142485783 ps
T147 /workspace/coverage/cover_reg_top/2.kmac_intr_test.672649704 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:15 PM PDT 24 14683423 ps
T1090 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1796247873 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:15 PM PDT 24 53156739 ps
T140 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2315463409 Jul 15 07:23:51 PM PDT 24 Jul 15 07:24:43 PM PDT 24 64748634 ps
T1091 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1707384029 Jul 15 07:23:06 PM PDT 24 Jul 15 07:24:18 PM PDT 24 72586006 ps
T148 /workspace/coverage/cover_reg_top/27.kmac_intr_test.1382123964 Jul 15 07:23:53 PM PDT 24 Jul 15 07:24:43 PM PDT 24 44634283 ps
T1092 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3904935497 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:22 PM PDT 24 611599636 ps
T167 /workspace/coverage/cover_reg_top/21.kmac_intr_test.82040210 Jul 15 07:23:57 PM PDT 24 Jul 15 07:24:44 PM PDT 24 14269712 ps
T129 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4294769287 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:16 PM PDT 24 318763917 ps
T133 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1780698512 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:15 PM PDT 24 394819752 ps
T1093 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1340093598 Jul 15 07:23:08 PM PDT 24 Jul 15 07:24:18 PM PDT 24 22872725 ps
T1094 /workspace/coverage/cover_reg_top/36.kmac_intr_test.2399215679 Jul 15 07:23:58 PM PDT 24 Jul 15 07:24:44 PM PDT 24 13758692 ps
T130 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3788479388 Jul 15 07:23:08 PM PDT 24 Jul 15 07:24:21 PM PDT 24 190703335 ps
T131 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.2348939879 Jul 15 07:22:54 PM PDT 24 Jul 15 07:24:05 PM PDT 24 217043378 ps
T103 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2113961685 Jul 15 07:22:58 PM PDT 24 Jul 15 07:24:09 PM PDT 24 116451815 ps
T141 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1614178909 Jul 15 07:22:56 PM PDT 24 Jul 15 07:24:07 PM PDT 24 34850131 ps
T168 /workspace/coverage/cover_reg_top/44.kmac_intr_test.1816995823 Jul 15 07:24:04 PM PDT 24 Jul 15 07:24:48 PM PDT 24 46973359 ps
T166 /workspace/coverage/cover_reg_top/7.kmac_intr_test.1070566601 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:17 PM PDT 24 16878514 ps
T123 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2506829505 Jul 15 07:23:38 PM PDT 24 Jul 15 07:24:37 PM PDT 24 2417369030 ps
T149 /workspace/coverage/cover_reg_top/38.kmac_intr_test.2850062949 Jul 15 07:23:57 PM PDT 24 Jul 15 07:24:44 PM PDT 24 16796430 ps
T1095 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1213630791 Jul 15 07:23:34 PM PDT 24 Jul 15 07:24:32 PM PDT 24 26627547 ps
T101 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2308810552 Jul 15 07:23:37 PM PDT 24 Jul 15 07:24:35 PM PDT 24 40027285 ps
T1096 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2295639004 Jul 15 07:23:01 PM PDT 24 Jul 15 07:24:14 PM PDT 24 66828291 ps
T102 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.4094877669 Jul 15 07:23:44 PM PDT 24 Jul 15 07:24:40 PM PDT 24 75830383 ps
T124 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2582742202 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:22 PM PDT 24 468962355 ps
T1097 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1030226323 Jul 15 07:23:22 PM PDT 24 Jul 15 07:24:27 PM PDT 24 39813077 ps
T150 /workspace/coverage/cover_reg_top/8.kmac_intr_test.3537775888 Jul 15 07:23:13 PM PDT 24 Jul 15 07:24:20 PM PDT 24 23499526 ps
T175 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3755819091 Jul 15 07:23:19 PM PDT 24 Jul 15 07:24:26 PM PDT 24 275201316 ps
T119 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3353083152 Jul 15 07:23:33 PM PDT 24 Jul 15 07:24:31 PM PDT 24 135688651 ps
T1098 /workspace/coverage/cover_reg_top/32.kmac_intr_test.1383181543 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:42 PM PDT 24 14291392 ps
T1099 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2825404136 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:32 PM PDT 24 967678506 ps
T1100 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3164905030 Jul 15 07:23:38 PM PDT 24 Jul 15 07:24:35 PM PDT 24 30239881 ps
T1101 /workspace/coverage/cover_reg_top/3.kmac_intr_test.2119629496 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:14 PM PDT 24 24218509 ps
T1102 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.921687341 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:15 PM PDT 24 26176613 ps
T142 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2271583368 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:19 PM PDT 24 372777538 ps
T1103 /workspace/coverage/cover_reg_top/1.kmac_intr_test.2442662952 Jul 15 07:23:06 PM PDT 24 Jul 15 07:24:17 PM PDT 24 21689763 ps
T1104 /workspace/coverage/cover_reg_top/37.kmac_intr_test.3076950865 Jul 15 07:23:57 PM PDT 24 Jul 15 07:24:44 PM PDT 24 12175626 ps
T143 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1898167621 Jul 15 07:23:29 PM PDT 24 Jul 15 07:24:30 PM PDT 24 95431010 ps
T144 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3049653129 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:26 PM PDT 24 2287343628 ps
T1105 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.816386980 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:41 PM PDT 24 81569014 ps
T145 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.681709596 Jul 15 07:23:00 PM PDT 24 Jul 15 07:24:14 PM PDT 24 122640754 ps
T1106 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1149894892 Jul 15 07:23:19 PM PDT 24 Jul 15 07:24:27 PM PDT 24 217908376 ps
T1107 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.448009749 Jul 15 07:23:49 PM PDT 24 Jul 15 07:24:42 PM PDT 24 301225878 ps
T104 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2084280399 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:44 PM PDT 24 193758190 ps
T146 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.87015949 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:21 PM PDT 24 25792262 ps
T1108 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.727315668 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:18 PM PDT 24 47020233 ps
T1109 /workspace/coverage/cover_reg_top/49.kmac_intr_test.1918643527 Jul 15 07:24:05 PM PDT 24 Jul 15 07:24:48 PM PDT 24 44712178 ps
T151 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3389638117 Jul 15 07:23:29 PM PDT 24 Jul 15 07:24:29 PM PDT 24 90921855 ps
T117 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2947704930 Jul 15 07:23:06 PM PDT 24 Jul 15 07:24:17 PM PDT 24 79424349 ps
T1110 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.606364708 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:15 PM PDT 24 53234742 ps
T1111 /workspace/coverage/cover_reg_top/42.kmac_intr_test.3561760895 Jul 15 07:24:07 PM PDT 24 Jul 15 07:24:48 PM PDT 24 39961553 ps
T1112 /workspace/coverage/cover_reg_top/29.kmac_intr_test.3397541629 Jul 15 07:23:48 PM PDT 24 Jul 15 07:24:41 PM PDT 24 19354649 ps
T1113 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.812156446 Jul 15 07:23:28 PM PDT 24 Jul 15 07:24:30 PM PDT 24 70442590 ps
T1114 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1117637957 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:44 PM PDT 24 163306483 ps
T1115 /workspace/coverage/cover_reg_top/19.kmac_intr_test.382612137 Jul 15 07:23:51 PM PDT 24 Jul 15 07:24:42 PM PDT 24 27194844 ps
T1116 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2588519865 Jul 15 07:23:15 PM PDT 24 Jul 15 07:24:23 PM PDT 24 43292911 ps
T1117 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1642820069 Jul 15 07:23:52 PM PDT 24 Jul 15 07:24:45 PM PDT 24 73006297 ps
T1118 /workspace/coverage/cover_reg_top/39.kmac_intr_test.1879104620 Jul 15 07:24:01 PM PDT 24 Jul 15 07:24:46 PM PDT 24 89427330 ps
T1119 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3194537098 Jul 15 07:23:01 PM PDT 24 Jul 15 07:24:18 PM PDT 24 201155478 ps
T1120 /workspace/coverage/cover_reg_top/28.kmac_intr_test.11606177 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:42 PM PDT 24 37577853 ps
T1121 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1399741130 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:21 PM PDT 24 152430145 ps
T1122 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4241584939 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:16 PM PDT 24 27507918 ps
T1123 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3123370024 Jul 15 07:23:42 PM PDT 24 Jul 15 07:24:38 PM PDT 24 345787341 ps
T178 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1771273740 Jul 15 07:23:20 PM PDT 24 Jul 15 07:24:26 PM PDT 24 143326786 ps
T1124 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.658605777 Jul 15 07:23:32 PM PDT 24 Jul 15 07:24:31 PM PDT 24 159673390 ps
T1125 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2884746679 Jul 15 07:23:40 PM PDT 24 Jul 15 07:24:35 PM PDT 24 59436510 ps
T1126 /workspace/coverage/cover_reg_top/35.kmac_intr_test.2173051000 Jul 15 07:23:58 PM PDT 24 Jul 15 07:24:44 PM PDT 24 19581067 ps
T152 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3143616498 Jul 15 07:23:05 PM PDT 24 Jul 15 07:24:17 PM PDT 24 2068820133 ps
T1127 /workspace/coverage/cover_reg_top/46.kmac_intr_test.1444487147 Jul 15 07:24:06 PM PDT 24 Jul 15 07:24:48 PM PDT 24 87444805 ps
T1128 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3026512640 Jul 15 07:23:13 PM PDT 24 Jul 15 07:24:22 PM PDT 24 90166623 ps
T1129 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.4074364041 Jul 15 07:23:05 PM PDT 24 Jul 15 07:24:15 PM PDT 24 49398987 ps
T1130 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1565354101 Jul 15 07:23:08 PM PDT 24 Jul 15 07:24:18 PM PDT 24 173186168 ps
T1131 /workspace/coverage/cover_reg_top/15.kmac_intr_test.337809702 Jul 15 07:23:33 PM PDT 24 Jul 15 07:24:30 PM PDT 24 16450852 ps
T1132 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3167043110 Jul 15 07:23:32 PM PDT 24 Jul 15 07:24:31 PM PDT 24 195800990 ps
T174 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2716061764 Jul 15 07:23:45 PM PDT 24 Jul 15 07:24:45 PM PDT 24 375819527 ps
T105 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2510424677 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:15 PM PDT 24 176077610 ps
T1133 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1459099568 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:17 PM PDT 24 435354006 ps
T1134 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.720638399 Jul 15 07:23:15 PM PDT 24 Jul 15 07:24:21 PM PDT 24 39017613 ps
T172 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2248449241 Jul 15 07:23:21 PM PDT 24 Jul 15 07:24:30 PM PDT 24 260904066 ps
T1135 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2081698777 Jul 15 07:23:41 PM PDT 24 Jul 15 07:24:38 PM PDT 24 1152677047 ps
T1136 /workspace/coverage/cover_reg_top/24.kmac_intr_test.114666015 Jul 15 07:23:58 PM PDT 24 Jul 15 07:24:44 PM PDT 24 13173513 ps
T1137 /workspace/coverage/cover_reg_top/30.kmac_intr_test.1139944490 Jul 15 07:23:49 PM PDT 24 Jul 15 07:24:41 PM PDT 24 14952420 ps
T1138 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2419071194 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:30 PM PDT 24 548604524 ps
T134 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1967179646 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:15 PM PDT 24 29210659 ps
T1139 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1254161753 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:14 PM PDT 24 121997777 ps
T1140 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2045643245 Jul 15 07:23:15 PM PDT 24 Jul 15 07:24:21 PM PDT 24 99479479 ps
T1141 /workspace/coverage/cover_reg_top/33.kmac_intr_test.3222694404 Jul 15 07:24:00 PM PDT 24 Jul 15 07:24:46 PM PDT 24 14496923 ps
T1142 /workspace/coverage/cover_reg_top/17.kmac_intr_test.2417692174 Jul 15 07:23:39 PM PDT 24 Jul 15 07:24:34 PM PDT 24 43817490 ps
T1143 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1267970688 Jul 15 07:23:10 PM PDT 24 Jul 15 07:24:19 PM PDT 24 25465001 ps
T1144 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.1427202043 Jul 15 07:22:55 PM PDT 24 Jul 15 07:24:07 PM PDT 24 122139485 ps
T176 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3944330145 Jul 15 07:23:09 PM PDT 24 Jul 15 07:24:20 PM PDT 24 183372204 ps
T1145 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1650451129 Jul 15 07:23:28 PM PDT 24 Jul 15 07:24:30 PM PDT 24 312134514 ps
T1146 /workspace/coverage/cover_reg_top/22.kmac_intr_test.1862473184 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:42 PM PDT 24 22790137 ps
T177 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.886910080 Jul 15 07:23:21 PM PDT 24 Jul 15 07:24:27 PM PDT 24 276098649 ps
T1147 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2139368810 Jul 15 07:23:51 PM PDT 24 Jul 15 07:24:43 PM PDT 24 128188986 ps
T173 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3007246891 Jul 15 07:23:40 PM PDT 24 Jul 15 07:24:36 PM PDT 24 101764123 ps
T1148 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2666113629 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:21 PM PDT 24 62192633 ps
T1149 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4277313324 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:21 PM PDT 24 279106608 ps
T1150 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3470196205 Jul 15 07:23:13 PM PDT 24 Jul 15 07:24:25 PM PDT 24 353351289 ps
T1151 /workspace/coverage/cover_reg_top/9.kmac_intr_test.3966111852 Jul 15 07:23:12 PM PDT 24 Jul 15 07:24:20 PM PDT 24 26281243 ps
T1152 /workspace/coverage/cover_reg_top/25.kmac_intr_test.3927777621 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:42 PM PDT 24 13609577 ps
T1153 /workspace/coverage/cover_reg_top/47.kmac_intr_test.228879845 Jul 15 07:24:06 PM PDT 24 Jul 15 07:24:48 PM PDT 24 48572727 ps
T1154 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1268300927 Jul 15 07:23:33 PM PDT 24 Jul 15 07:24:31 PM PDT 24 68638142 ps
T1155 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2597585035 Jul 15 07:23:08 PM PDT 24 Jul 15 07:24:18 PM PDT 24 123413623 ps
T1156 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1264794188 Jul 15 07:23:08 PM PDT 24 Jul 15 07:24:18 PM PDT 24 271127466 ps
T1157 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.215785764 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:19 PM PDT 24 203148016 ps
T1158 /workspace/coverage/cover_reg_top/13.kmac_intr_test.4177710786 Jul 15 07:23:21 PM PDT 24 Jul 15 07:24:26 PM PDT 24 40856044 ps
T1159 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2590087260 Jul 15 07:23:38 PM PDT 24 Jul 15 07:24:35 PM PDT 24 45631596 ps
T1160 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3499799429 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:15 PM PDT 24 94155057 ps
T1161 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2376203706 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:17 PM PDT 24 18090832 ps
T1162 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2328812414 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:18 PM PDT 24 68445306 ps
T1163 /workspace/coverage/cover_reg_top/5.kmac_intr_test.3345852017 Jul 15 07:23:09 PM PDT 24 Jul 15 07:24:18 PM PDT 24 11781874 ps
T118 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.740092762 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:17 PM PDT 24 84181199 ps
T1164 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2716813131 Jul 15 07:23:22 PM PDT 24 Jul 15 07:24:29 PM PDT 24 99996200 ps
T125 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.244517901 Jul 15 07:23:05 PM PDT 24 Jul 15 07:24:17 PM PDT 24 88952706 ps
T1165 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.739425504 Jul 15 07:23:33 PM PDT 24 Jul 15 07:24:30 PM PDT 24 110622853 ps
T1166 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1978317474 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:14 PM PDT 24 45385858 ps
T1167 /workspace/coverage/cover_reg_top/11.kmac_intr_test.104536436 Jul 15 07:23:19 PM PDT 24 Jul 15 07:24:25 PM PDT 24 44215571 ps
T128 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2559238945 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:15 PM PDT 24 47543077 ps
T1168 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3841872685 Jul 15 07:23:26 PM PDT 24 Jul 15 07:24:28 PM PDT 24 117695095 ps
T1169 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3105655188 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:14 PM PDT 24 11698953 ps
T1170 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.350906230 Jul 15 07:23:28 PM PDT 24 Jul 15 07:24:29 PM PDT 24 72461618 ps
T1171 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3250701203 Jul 15 07:23:26 PM PDT 24 Jul 15 07:24:29 PM PDT 24 182063032 ps
T1172 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2983932017 Jul 15 07:23:41 PM PDT 24 Jul 15 07:24:37 PM PDT 24 458302095 ps
T1173 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1884945894 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:14 PM PDT 24 98573440 ps
T1174 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2485247509 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:15 PM PDT 24 119849195 ps
T1175 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3250975252 Jul 15 07:23:06 PM PDT 24 Jul 15 07:24:16 PM PDT 24 16278643 ps
T127 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1114972217 Jul 15 07:23:45 PM PDT 24 Jul 15 07:24:42 PM PDT 24 107820337 ps
T1176 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.800852176 Jul 15 07:23:05 PM PDT 24 Jul 15 07:24:16 PM PDT 24 206057700 ps
T1177 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3344246371 Jul 15 07:23:09 PM PDT 24 Jul 15 07:24:18 PM PDT 24 36454698 ps
T1178 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.4013822684 Jul 15 07:23:39 PM PDT 24 Jul 15 07:24:35 PM PDT 24 132855103 ps
T169 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2631523927 Jul 15 07:23:09 PM PDT 24 Jul 15 07:24:21 PM PDT 24 359848006 ps
T1179 /workspace/coverage/cover_reg_top/6.kmac_intr_test.1253782376 Jul 15 07:23:10 PM PDT 24 Jul 15 07:24:18 PM PDT 24 15260010 ps
T1180 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2409375900 Jul 15 07:23:03 PM PDT 24 Jul 15 07:24:16 PM PDT 24 709140331 ps
T1181 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1346067843 Jul 15 07:23:10 PM PDT 24 Jul 15 07:24:33 PM PDT 24 289304278 ps
T1182 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3485542948 Jul 15 07:23:00 PM PDT 24 Jul 15 07:24:12 PM PDT 24 581995066 ps
T1183 /workspace/coverage/cover_reg_top/48.kmac_intr_test.3228128129 Jul 15 07:24:11 PM PDT 24 Jul 15 07:24:51 PM PDT 24 52727989 ps
T179 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2327099576 Jul 15 07:23:45 PM PDT 24 Jul 15 07:24:43 PM PDT 24 144290472 ps
T1184 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.382171390 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:15 PM PDT 24 45417343 ps
T1185 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2011309025 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:16 PM PDT 24 138060916 ps
T1186 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3961592843 Jul 15 07:23:10 PM PDT 24 Jul 15 07:24:20 PM PDT 24 374328241 ps
T1187 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2360595598 Jul 15 07:23:16 PM PDT 24 Jul 15 07:24:22 PM PDT 24 77709957 ps
T1188 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1227482243 Jul 15 07:23:29 PM PDT 24 Jul 15 07:24:30 PM PDT 24 66026007 ps
T1189 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3378994979 Jul 15 07:23:06 PM PDT 24 Jul 15 07:24:18 PM PDT 24 179718191 ps
T1190 /workspace/coverage/cover_reg_top/0.kmac_intr_test.1264398615 Jul 15 07:22:55 PM PDT 24 Jul 15 07:24:06 PM PDT 24 15759795 ps
T1191 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2447444251 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:22 PM PDT 24 148337886 ps
T1192 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3575535635 Jul 15 07:23:15 PM PDT 24 Jul 15 07:24:22 PM PDT 24 61548587 ps
T1193 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2489667330 Jul 15 07:24:05 PM PDT 24 Jul 15 07:24:48 PM PDT 24 13767030 ps
T1194 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.204206635 Jul 15 07:23:06 PM PDT 24 Jul 15 07:24:17 PM PDT 24 32239827 ps
T1195 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2719354042 Jul 15 07:23:10 PM PDT 24 Jul 15 07:24:19 PM PDT 24 248024603 ps
T1196 /workspace/coverage/cover_reg_top/45.kmac_intr_test.3713813018 Jul 15 07:24:11 PM PDT 24 Jul 15 07:24:51 PM PDT 24 45298101 ps
T1197 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.9159663 Jul 15 07:23:00 PM PDT 24 Jul 15 07:24:10 PM PDT 24 29461888 ps
T1198 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3822057515 Jul 15 07:23:22 PM PDT 24 Jul 15 07:24:27 PM PDT 24 87798367 ps
T1199 /workspace/coverage/cover_reg_top/14.kmac_intr_test.1645025251 Jul 15 07:23:33 PM PDT 24 Jul 15 07:24:30 PM PDT 24 36506412 ps
T1200 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.586796761 Jul 15 07:23:42 PM PDT 24 Jul 15 07:24:37 PM PDT 24 117981178 ps
T1201 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.3008046790 Jul 15 07:23:57 PM PDT 24 Jul 15 07:24:44 PM PDT 24 56247996 ps
T1202 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2837025961 Jul 15 07:23:16 PM PDT 24 Jul 15 07:24:22 PM PDT 24 62599364 ps
T1203 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1489667764 Jul 15 07:23:13 PM PDT 24 Jul 15 07:24:21 PM PDT 24 57111326 ps
T135 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4192565914 Jul 15 07:22:57 PM PDT 24 Jul 15 07:24:09 PM PDT 24 162041223 ps
T1204 /workspace/coverage/cover_reg_top/40.kmac_intr_test.1405418401 Jul 15 07:23:57 PM PDT 24 Jul 15 07:24:44 PM PDT 24 16127040 ps
T1205 /workspace/coverage/cover_reg_top/26.kmac_intr_test.727780646 Jul 15 07:23:54 PM PDT 24 Jul 15 07:24:44 PM PDT 24 16709703 ps
T1206 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2755566374 Jul 15 07:23:05 PM PDT 24 Jul 15 07:24:17 PM PDT 24 204462064 ps
T1207 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.949461412 Jul 15 07:23:37 PM PDT 24 Jul 15 07:24:35 PM PDT 24 159285312 ps
T1208 /workspace/coverage/cover_reg_top/16.kmac_intr_test.4028806468 Jul 15 07:23:40 PM PDT 24 Jul 15 07:24:34 PM PDT 24 39308619 ps
T1209 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1593062064 Jul 15 07:23:32 PM PDT 24 Jul 15 07:24:31 PM PDT 24 137983779 ps
T1210 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2173551789 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:22 PM PDT 24 85571128 ps
T1211 /workspace/coverage/cover_reg_top/10.kmac_intr_test.3088609385 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:21 PM PDT 24 42106992 ps
T1212 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1905995094 Jul 15 07:23:26 PM PDT 24 Jul 15 07:24:28 PM PDT 24 21061934 ps
T1213 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2845811854 Jul 15 07:23:38 PM PDT 24 Jul 15 07:24:36 PM PDT 24 74173911 ps
T1214 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1400657393 Jul 15 07:23:33 PM PDT 24 Jul 15 07:24:31 PM PDT 24 487183748 ps
T1215 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.1327395552 Jul 15 07:23:27 PM PDT 24 Jul 15 07:24:28 PM PDT 24 51471302 ps
T1216 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2974157217 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:18 PM PDT 24 554356529 ps
T1217 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2503869023 Jul 15 07:23:07 PM PDT 24 Jul 15 07:24:19 PM PDT 24 121589395 ps
T1218 /workspace/coverage/cover_reg_top/23.kmac_intr_test.3063076034 Jul 15 07:23:50 PM PDT 24 Jul 15 07:24:42 PM PDT 24 16231327 ps
T1219 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1939951276 Jul 15 07:23:38 PM PDT 24 Jul 15 07:24:34 PM PDT 24 22993563 ps
T1220 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.958108882 Jul 15 07:23:14 PM PDT 24 Jul 15 07:24:21 PM PDT 24 97418488 ps
T1221 /workspace/coverage/cover_reg_top/20.kmac_intr_test.858690281 Jul 15 07:23:58 PM PDT 24 Jul 15 07:24:44 PM PDT 24 41170075 ps
T1222 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.808076979 Jul 15 07:23:02 PM PDT 24 Jul 15 07:24:15 PM PDT 24 152078018 ps
T1223 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2338515898 Jul 15 07:23:08 PM PDT 24 Jul 15 07:24:18 PM PDT 24 27003993 ps
T1224 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2849865780 Jul 15 07:23:09 PM PDT 24 Jul 15 07:24:19 PM PDT 24 193419890 ps
T1225 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2532683857 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:16 PM PDT 24 66855232 ps
T1226 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3878681645 Jul 15 07:22:57 PM PDT 24 Jul 15 07:24:09 PM PDT 24 66645539 ps
T1227 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2552458536 Jul 15 07:23:15 PM PDT 24 Jul 15 07:24:22 PM PDT 24 24356734 ps
T1228 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.63306336 Jul 15 07:23:08 PM PDT 24 Jul 15 07:24:18 PM PDT 24 55276288 ps
T1229 /workspace/coverage/cover_reg_top/18.kmac_intr_test.2319740964 Jul 15 07:23:49 PM PDT 24 Jul 15 07:24:42 PM PDT 24 48593926 ps
T1230 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.438857927 Jul 15 07:23:04 PM PDT 24 Jul 15 07:24:24 PM PDT 24 2371300758 ps
T1231 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2139557099 Jul 15 07:23:06 PM PDT 24 Jul 15 07:24:20 PM PDT 24 97532261 ps

Test location /workspace/coverage/default/19.kmac_stress_all.4002864423
Short name T13
Test name
Test status
Simulation time 11425019277 ps
CPU time 130.43 seconds
Started Jul 15 06:34:35 PM PDT 24
Finished Jul 15 06:36:45 PM PDT 24
Peak memory 253688 kb
Host smart-052cba0b-af6c-479b-b79e-6d65c9ee3bad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4002864423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.4002864423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2554046642
Short name T113
Test name
Test status
Simulation time 255263795 ps
CPU time 4.31 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:24 PM PDT 24
Peak memory 215552 kb
Host smart-6cdf69e0-bd69-44fa-bf17-857103ee087d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554046642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.25540
46642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.3132772588
Short name T4
Test name
Test status
Simulation time 42667771 ps
CPU time 1.35 seconds
Started Jul 15 06:35:04 PM PDT 24
Finished Jul 15 06:35:06 PM PDT 24
Peak memory 215772 kb
Host smart-84745589-e794-4520-9b0c-57d6cbc02f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132772588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3132772588 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1561407493
Short name T10
Test name
Test status
Simulation time 4123353222 ps
CPU time 27.75 seconds
Started Jul 15 06:32:49 PM PDT 24
Finished Jul 15 06:33:18 PM PDT 24
Peak memory 245224 kb
Host smart-5967d267-0bd1-4734-84dc-823ad7265c71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561407493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1561407493 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/41.kmac_key_error.3216053193
Short name T20
Test name
Test status
Simulation time 7066765604 ps
CPU time 11.01 seconds
Started Jul 15 06:39:11 PM PDT 24
Finished Jul 15 06:39:23 PM PDT 24
Peak memory 207380 kb
Host smart-71a7a502-cfea-4325-935b-5e97295b9c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216053193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3216053193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.724324337
Short name T100
Test name
Test status
Simulation time 56588896 ps
CPU time 1.39 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 215996 kb
Host smart-ace1d181-679e-4ccb-9c12-09dffd9f090d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724324337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e
rrors.724324337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.1663622799
Short name T70
Test name
Test status
Simulation time 44897854045 ps
CPU time 3310.24 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 07:27:55 PM PDT 24
Peak memory 549252 kb
Host smart-03133890-4be4-4198-8695-750a1092d27d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1663622799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1663622799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_error.4285746637
Short name T29
Test name
Test status
Simulation time 30986527906 ps
CPU time 209.63 seconds
Started Jul 15 06:33:06 PM PDT 24
Finished Jul 15 06:36:39 PM PDT 24
Peak memory 248684 kb
Host smart-741c9ff4-f52f-4b59-9420-0b992f32090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285746637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.4285746637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1286878519
Short name T115
Test name
Test status
Simulation time 41252710 ps
CPU time 1.29 seconds
Started Jul 15 07:23:31 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 215664 kb
Host smart-c6c3d54d-deee-4035-a4f9-f12c660b9b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286878519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1286878519 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.2948745251
Short name T8
Test name
Test status
Simulation time 48071320 ps
CPU time 1.33 seconds
Started Jul 15 06:39:30 PM PDT 24
Finished Jul 15 06:39:32 PM PDT 24
Peak memory 215892 kb
Host smart-7f7e1989-8883-4f1d-9a2b-aef5edf354f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948745251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2948745251 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.3542799680
Short name T57
Test name
Test status
Simulation time 929047349 ps
CPU time 22.47 seconds
Started Jul 15 06:33:23 PM PDT 24
Finished Jul 15 06:33:46 PM PDT 24
Peak memory 231956 kb
Host smart-f8923bcf-5c21-4285-87ce-dc4966a0fecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542799680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3542799680 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.2883245600
Short name T120
Test name
Test status
Simulation time 47553764 ps
CPU time 0.73 seconds
Started Jul 15 07:23:20 PM PDT 24
Finished Jul 15 07:24:24 PM PDT 24
Peak memory 207056 kb
Host smart-0216bea8-1c48-44ce-a5d7-5f84ee4574a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883245600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2883245600 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.3355545215
Short name T7
Test name
Test status
Simulation time 65977433 ps
CPU time 1.44 seconds
Started Jul 15 06:33:11 PM PDT 24
Finished Jul 15 06:33:14 PM PDT 24
Peak memory 215584 kb
Host smart-b6a0e6ae-6aae-4b48-95a0-770776256a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355545215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3355545215 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_stress_all.2904341191
Short name T39
Test name
Test status
Simulation time 26909365740 ps
CPU time 834.8 seconds
Started Jul 15 06:39:49 PM PDT 24
Finished Jul 15 06:53:44 PM PDT 24
Peak memory 350232 kb
Host smart-6369249c-1e9b-4795-9716-1100d85e5dfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2904341191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2904341191 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1771273740
Short name T178
Test name
Test status
Simulation time 143326786 ps
CPU time 1.25 seconds
Started Jul 15 07:23:20 PM PDT 24
Finished Jul 15 07:24:26 PM PDT 24
Peak memory 215996 kb
Host smart-26623797-e23b-45db-b74f-ee8f3c397af7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771273740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1771273740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.kmac_alert_test.758025220
Short name T50
Test name
Test status
Simulation time 21184851 ps
CPU time 0.88 seconds
Started Jul 15 06:33:27 PM PDT 24
Finished Jul 15 06:33:28 PM PDT 24
Peak memory 205248 kb
Host smart-fdb4f6aa-b1bd-4d84-82f8-1927da1e23a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758025220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.758025220 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.1710031435
Short name T16
Test name
Test status
Simulation time 44025352269 ps
CPU time 222.14 seconds
Started Jul 15 06:33:16 PM PDT 24
Finished Jul 15 06:36:59 PM PDT 24
Peak memory 237524 kb
Host smart-05be08b7-221f-45be-badd-c21774242567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710031435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1710031435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4192565914
Short name T135
Test name
Test status
Simulation time 162041223 ps
CPU time 1.43 seconds
Started Jul 15 07:22:57 PM PDT 24
Finished Jul 15 07:24:09 PM PDT 24
Peak memory 215508 kb
Host smart-f1d2cf78-5b19-41f2-a113-4d35d3c619b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192565914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.4192565914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.792600887
Short name T116
Test name
Test status
Simulation time 72759976 ps
CPU time 2.09 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:08 PM PDT 24
Peak memory 215568 kb
Host smart-51a0b505-182d-4f34-864c-7808f0577dec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792600887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.792600887 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.4094877669
Short name T102
Test name
Test status
Simulation time 75830383 ps
CPU time 1.35 seconds
Started Jul 15 07:23:44 PM PDT 24
Finished Jul 15 07:24:40 PM PDT 24
Peak memory 216000 kb
Host smart-8be362b0-9062-4842-837b-f2a6e12d1ec8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094877669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.4094877669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2597284916
Short name T89
Test name
Test status
Simulation time 62764132867 ps
CPU time 1277.53 seconds
Started Jul 15 06:34:44 PM PDT 24
Finished Jul 15 06:56:02 PM PDT 24
Peak memory 355212 kb
Host smart-1c8d4926-f5cd-4771-8077-5737b6b412d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2597284916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2597284916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.2119629496
Short name T1101
Test name
Test status
Simulation time 24218509 ps
CPU time 0.76 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 207104 kb
Host smart-506ccfd6-f40c-4384-9ca5-5875551003d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119629496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2119629496 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3944330145
Short name T176
Test name
Test status
Simulation time 183372204 ps
CPU time 2.43 seconds
Started Jul 15 07:23:09 PM PDT 24
Finished Jul 15 07:24:20 PM PDT 24
Peak memory 215636 kb
Host smart-6bcdef77-9e3a-4704-8fa4-9abf9ef2bcaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944330145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.39443
30145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.4129594715
Short name T159
Test name
Test status
Simulation time 181048816660 ps
CPU time 3348.5 seconds
Started Jul 15 06:39:30 PM PDT 24
Finished Jul 15 07:35:19 PM PDT 24
Peak memory 564604 kb
Host smart-c6b97fbc-321a-4672-bab9-77976b1554d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4129594715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.4129594715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_app.398033472
Short name T25
Test name
Test status
Simulation time 12768517791 ps
CPU time 208.48 seconds
Started Jul 15 06:34:51 PM PDT 24
Finished Jul 15 06:38:20 PM PDT 24
Peak memory 239500 kb
Host smart-77191e85-3f94-4c33-bff2-830acd35e094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398033472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.398033472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_error.2062591653
Short name T30
Test name
Test status
Simulation time 4396292997 ps
CPU time 343.93 seconds
Started Jul 15 06:32:43 PM PDT 24
Finished Jul 15 06:38:28 PM PDT 24
Peak memory 255876 kb
Host smart-5e16f31e-055a-49f7-8b72-3401914b7497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062591653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2062591653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.2266925839
Short name T45
Test name
Test status
Simulation time 6785212703 ps
CPU time 30.08 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 223840 kb
Host smart-22380fa3-1c83-4d6e-b7ef-f7843b4577a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266925839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2266925839 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1688878906
Short name T53
Test name
Test status
Simulation time 31453591 ps
CPU time 1.63 seconds
Started Jul 15 07:23:26 PM PDT 24
Finished Jul 15 07:24:28 PM PDT 24
Peak memory 218036 kb
Host smart-31490ab8-1c75-418f-9845-e139bd3fee45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688878906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1688878906 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.382612137
Short name T1115
Test name
Test status
Simulation time 27194844 ps
CPU time 0.78 seconds
Started Jul 15 07:23:51 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 207068 kb
Host smart-2c1e97eb-fbc0-40e9-8a41-e4279b8a4bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382612137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.382612137 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1895165930
Short name T162
Test name
Test status
Simulation time 170155007787 ps
CPU time 4676.35 seconds
Started Jul 15 06:32:36 PM PDT 24
Finished Jul 15 07:50:34 PM PDT 24
Peak memory 638112 kb
Host smart-ded7653d-68af-4ec0-b1c1-80ad4ae32dca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1895165930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1895165930 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2512621518
Short name T126
Test name
Test status
Simulation time 142485783 ps
CPU time 1.44 seconds
Started Jul 15 07:23:19 PM PDT 24
Finished Jul 15 07:24:26 PM PDT 24
Peak memory 215508 kb
Host smart-f6885fbd-af04-48fd-a240-d0ff87e39397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512621518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2512621518 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/default/12.kmac_burst_write.3620604008
Short name T971
Test name
Test status
Simulation time 24700098831 ps
CPU time 512.75 seconds
Started Jul 15 06:33:30 PM PDT 24
Finished Jul 15 06:42:03 PM PDT 24
Peak memory 230656 kb
Host smart-50538718-1bd8-4458-925c-14eb10cd2bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620604008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3620604008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2667718852
Short name T1087
Test name
Test status
Simulation time 842164787 ps
CPU time 8.26 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 207412 kb
Host smart-6de2f29e-f91d-4cb0-9195-6595b0b009e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667718852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2667718
852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2309434611
Short name T1085
Test name
Test status
Simulation time 963408827 ps
CPU time 17.91 seconds
Started Jul 15 07:22:56 PM PDT 24
Finished Jul 15 07:24:24 PM PDT 24
Peak memory 207384 kb
Host smart-4cd6a982-2e3d-47ca-86b1-ac2230f6dabf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309434611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2309434
611 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1614178909
Short name T141
Test name
Test status
Simulation time 34850131 ps
CPU time 1.11 seconds
Started Jul 15 07:22:56 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 207424 kb
Host smart-3ad54522-84cb-46be-ba14-3d349f85e34f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614178909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1614178
909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2409375900
Short name T1180
Test name
Test status
Simulation time 709140331 ps
CPU time 2.77 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:16 PM PDT 24
Peak memory 223788 kb
Host smart-cda47fd4-7c45-4d5c-b565-0301e4607112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409375900 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2409375900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.1427202043
Short name T1144
Test name
Test status
Simulation time 122139485 ps
CPU time 1.13 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 207388 kb
Host smart-21aede14-4674-4ae3-a83e-d8303de0df56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427202043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1427202043 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.1264398615
Short name T1190
Test name
Test status
Simulation time 15759795 ps
CPU time 0.74 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 207072 kb
Host smart-8df68a20-daa5-43fb-8930-bc61c56c03e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264398615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1264398615 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.369038610
Short name T1088
Test name
Test status
Simulation time 20544877 ps
CPU time 0.71 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:04 PM PDT 24
Peak memory 207160 kb
Host smart-29618a4e-c694-4272-aa14-cacfc925961c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369038610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.369038610 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1254161753
Short name T1139
Test name
Test status
Simulation time 121997777 ps
CPU time 1.66 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 215812 kb
Host smart-64df203a-eaad-4242-bbdf-86dfd0f0a80e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254161753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.1254161753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2113961685
Short name T103
Test name
Test status
Simulation time 116451815 ps
CPU time 1.05 seconds
Started Jul 15 07:22:58 PM PDT 24
Finished Jul 15 07:24:09 PM PDT 24
Peak memory 215656 kb
Host smart-396ce76d-f40a-4fb4-a883-ef8290e24f87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113961685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2113961685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3878681645
Short name T1226
Test name
Test status
Simulation time 66645539 ps
CPU time 1.77 seconds
Started Jul 15 07:22:57 PM PDT 24
Finished Jul 15 07:24:09 PM PDT 24
Peak memory 215972 kb
Host smart-b50397c7-ffcf-44fc-8673-900b91cb2921
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878681645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.3878681645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.2348939879
Short name T131
Test name
Test status
Simulation time 217043378 ps
CPU time 2.44 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:05 PM PDT 24
Peak memory 215772 kb
Host smart-553e33cc-b8c4-496b-beb3-7b69c2a47827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348939879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.23489
39879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3194537098
Short name T1119
Test name
Test status
Simulation time 201155478 ps
CPU time 5 seconds
Started Jul 15 07:23:01 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 207460 kb
Host smart-b0c788af-adc0-4ea8-ad94-4c214f7754ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194537098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3194537
098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2419071194
Short name T1138
Test name
Test status
Simulation time 548604524 ps
CPU time 15.78 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 207388 kb
Host smart-be346a4f-a822-4fb5-a032-4ee4e03674e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419071194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2419071
194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2295639004
Short name T1096
Test name
Test status
Simulation time 66828291 ps
CPU time 0.94 seconds
Started Jul 15 07:23:01 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 207212 kb
Host smart-a8087529-d330-4e93-b146-24c179845953
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295639004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2295639
004 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4294769287
Short name T129
Test name
Test status
Simulation time 318763917 ps
CPU time 2.29 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:16 PM PDT 24
Peak memory 217132 kb
Host smart-cd7182a4-c424-496b-942c-df548a77b96a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294769287 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.4294769287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1340093598
Short name T1093
Test name
Test status
Simulation time 22872725 ps
CPU time 0.86 seconds
Started Jul 15 07:23:08 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 207080 kb
Host smart-d7192988-5a50-493c-aa08-31e9bc148f08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340093598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1340093598 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.2442662952
Short name T1103
Test name
Test status
Simulation time 21689763 ps
CPU time 0.74 seconds
Started Jul 15 07:23:06 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 207028 kb
Host smart-e948d76d-6625-4a21-bdd7-f07388bcba9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442662952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2442662952 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1780698512
Short name T133
Test name
Test status
Simulation time 394819752 ps
CPU time 1.19 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215476 kb
Host smart-29b169f0-16f0-4036-a59b-383a819eab92
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780698512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.1780698512 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2306716926
Short name T1083
Test name
Test status
Simulation time 46877925 ps
CPU time 0.7 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 207168 kb
Host smart-2e0b952a-3149-4593-aa8e-c8c06e5ee9d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306716926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2306716926
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3485542948
Short name T1182
Test name
Test status
Simulation time 581995066 ps
CPU time 1.65 seconds
Started Jul 15 07:23:00 PM PDT 24
Finished Jul 15 07:24:12 PM PDT 24
Peak memory 215580 kb
Host smart-adb2003f-1657-4f9d-ba43-bbda458f14c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485542948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.3485542948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.808076979
Short name T1222
Test name
Test status
Simulation time 152078018 ps
CPU time 1.35 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215912 kb
Host smart-83518b46-af46-412b-a7fa-c2a8fabd3795
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808076979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e
rrors.808076979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1264794188
Short name T1156
Test name
Test status
Simulation time 271127466 ps
CPU time 1.67 seconds
Started Jul 15 07:23:08 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 215572 kb
Host smart-e471c1a1-712b-4677-898e-95258b3a0514
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264794188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.1264794188 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.9159663
Short name T1197
Test name
Test status
Simulation time 29461888 ps
CPU time 1.96 seconds
Started Jul 15 07:23:00 PM PDT 24
Finished Jul 15 07:24:10 PM PDT 24
Peak memory 215600 kb
Host smart-cb5f3aca-25d6-4e8a-9477-c23d58ba5a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9159663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.9159663 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.681709596
Short name T145
Test name
Test status
Simulation time 122640754 ps
CPU time 2.83 seconds
Started Jul 15 07:23:00 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 215772 kb
Host smart-cdf186e9-c8cb-4d1a-97b4-4911d98ce339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681709596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.681709
596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.321850351
Short name T98
Test name
Test status
Simulation time 72039512 ps
CPU time 2.33 seconds
Started Jul 15 07:23:18 PM PDT 24
Finished Jul 15 07:24:26 PM PDT 24
Peak memory 223808 kb
Host smart-e9193311-9073-4c7c-bff0-1d169b1fc432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321850351 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.321850351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.87015949
Short name T146
Test name
Test status
Simulation time 25792262 ps
CPU time 0.98 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 207120 kb
Host smart-90f15cd6-9569-4e50-ba32-7863e7398404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87015949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.87015949 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.3088609385
Short name T1211
Test name
Test status
Simulation time 42106992 ps
CPU time 0.8 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 207020 kb
Host smart-a5dd8af6-34ee-420b-936b-2244f20e1657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088609385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3088609385 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2837025961
Short name T1202
Test name
Test status
Simulation time 62599364 ps
CPU time 1.52 seconds
Started Jul 15 07:23:16 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 215824 kb
Host smart-f2a5108a-f08a-461e-9468-bb6e917a3fa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837025961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.2837025961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4277313324
Short name T1149
Test name
Test status
Simulation time 279106608 ps
CPU time 1.1 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 215872 kb
Host smart-bdcae2bb-7b21-44f5-8fe8-36a0c580731a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277313324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.4277313324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1032843811
Short name T96
Test name
Test status
Simulation time 570260044 ps
CPU time 1.94 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 215920 kb
Host smart-bdbf02b4-e7f9-4d87-9f7c-ded458ee9cbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032843811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.1032843811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1489667764
Short name T1203
Test name
Test status
Simulation time 57111326 ps
CPU time 1.69 seconds
Started Jul 15 07:23:13 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 215532 kb
Host smart-081ca70b-13f7-4fe1-9418-d75f991740f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489667764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1489667764 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3470196205
Short name T1150
Test name
Test status
Simulation time 353351289 ps
CPU time 5.01 seconds
Started Jul 15 07:23:13 PM PDT 24
Finished Jul 15 07:24:25 PM PDT 24
Peak memory 207460 kb
Host smart-9924aac8-7803-4477-81a8-cc5767016f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470196205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3470
196205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1905995094
Short name T1212
Test name
Test status
Simulation time 21061934 ps
CPU time 1.55 seconds
Started Jul 15 07:23:26 PM PDT 24
Finished Jul 15 07:24:28 PM PDT 24
Peak memory 216240 kb
Host smart-0df246a8-1b09-403d-a7bd-4a3a0d15cf5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905995094 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1905995094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.1327395552
Short name T1215
Test name
Test status
Simulation time 51471302 ps
CPU time 1.06 seconds
Started Jul 15 07:23:27 PM PDT 24
Finished Jul 15 07:24:28 PM PDT 24
Peak memory 207408 kb
Host smart-72c8fd2a-4ad1-44c1-b0a1-79f3f0be65ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327395552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1327395552 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.104536436
Short name T1167
Test name
Test status
Simulation time 44215571 ps
CPU time 0.72 seconds
Started Jul 15 07:23:19 PM PDT 24
Finished Jul 15 07:24:25 PM PDT 24
Peak memory 207048 kb
Host smart-680ee4e9-be52-407e-963b-1592fa4f705b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104536436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.104536436 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1030226323
Short name T1097
Test name
Test status
Simulation time 39813077 ps
CPU time 2.09 seconds
Started Jul 15 07:23:22 PM PDT 24
Finished Jul 15 07:24:27 PM PDT 24
Peak memory 215908 kb
Host smart-e0543335-dcc1-4d7b-bdb9-2f432a417e85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030226323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1030226323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3575535635
Short name T1192
Test name
Test status
Simulation time 61548587 ps
CPU time 1.11 seconds
Started Jul 15 07:23:15 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 216008 kb
Host smart-392403e8-41a2-42be-ae81-9fdd7a241144
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575535635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.3575535635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2360595598
Short name T1187
Test name
Test status
Simulation time 77709957 ps
CPU time 1.51 seconds
Started Jul 15 07:23:16 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 215888 kb
Host smart-150aa2e7-3192-43fa-a77e-ce6fee5cdffb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360595598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.2360595598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2447444251
Short name T1191
Test name
Test status
Simulation time 148337886 ps
CPU time 1.79 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 215564 kb
Host smart-a4a3f55f-fab7-403c-95fa-fd2742939960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447444251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2447444251 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3755819091
Short name T175
Test name
Test status
Simulation time 275201316 ps
CPU time 2.45 seconds
Started Jul 15 07:23:19 PM PDT 24
Finished Jul 15 07:24:26 PM PDT 24
Peak memory 215560 kb
Host smart-c3d2758e-a408-42b9-a712-c4c58adac3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755819091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3755
819091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1650451129
Short name T1145
Test name
Test status
Simulation time 312134514 ps
CPU time 2.47 seconds
Started Jul 15 07:23:28 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 217864 kb
Host smart-baa878b3-6667-4bd5-b239-291e9c20dd2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650451129 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1650451129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1898167621
Short name T143
Test name
Test status
Simulation time 95431010 ps
CPU time 1.11 seconds
Started Jul 15 07:23:29 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 207380 kb
Host smart-4f7deab1-5cf9-4dd5-8290-98f24cec5b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898167621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1898167621 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1227482243
Short name T1188
Test name
Test status
Simulation time 66026007 ps
CPU time 1.57 seconds
Started Jul 15 07:23:29 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 216020 kb
Host smart-e8fbb3db-f835-44eb-a122-34381503e69f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227482243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.1227482243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4131121455
Short name T99
Test name
Test status
Simulation time 760506322 ps
CPU time 1.62 seconds
Started Jul 15 07:23:20 PM PDT 24
Finished Jul 15 07:24:26 PM PDT 24
Peak memory 215616 kb
Host smart-4f8d0649-fab1-41d1-95ed-2b4492419dc0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131121455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.4131121455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2248449241
Short name T172
Test name
Test status
Simulation time 260904066 ps
CPU time 5.11 seconds
Started Jul 15 07:23:21 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 207492 kb
Host smart-cb17059d-feab-41b0-95e7-69225b5c7b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248449241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2248
449241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.812156446
Short name T1113
Test name
Test status
Simulation time 70442590 ps
CPU time 2.28 seconds
Started Jul 15 07:23:28 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 217360 kb
Host smart-22234e0f-b2a7-4a90-a129-eecb16c620cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812156446 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.812156446 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.350906230
Short name T1170
Test name
Test status
Simulation time 72461618 ps
CPU time 0.93 seconds
Started Jul 15 07:23:28 PM PDT 24
Finished Jul 15 07:24:29 PM PDT 24
Peak memory 207112 kb
Host smart-f96c5924-f555-4c7b-98ac-1da0fed1e94b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350906230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.350906230 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.4177710786
Short name T1158
Test name
Test status
Simulation time 40856044 ps
CPU time 0.77 seconds
Started Jul 15 07:23:21 PM PDT 24
Finished Jul 15 07:24:26 PM PDT 24
Peak memory 207080 kb
Host smart-7185324a-4bb9-4757-afc9-e7fd3c7e1783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177710786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.4177710786 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3250701203
Short name T1171
Test name
Test status
Simulation time 182063032 ps
CPU time 2.25 seconds
Started Jul 15 07:23:26 PM PDT 24
Finished Jul 15 07:24:29 PM PDT 24
Peak memory 215580 kb
Host smart-89244d57-eb30-415d-8940-2132b78a47aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250701203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3250701203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3822057515
Short name T1198
Test name
Test status
Simulation time 87798367 ps
CPU time 1.13 seconds
Started Jul 15 07:23:22 PM PDT 24
Finished Jul 15 07:24:27 PM PDT 24
Peak memory 215952 kb
Host smart-4a374246-fd00-4226-8e79-3cdf7bebd205
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822057515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3822057515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2716813131
Short name T1164
Test name
Test status
Simulation time 99996200 ps
CPU time 2.55 seconds
Started Jul 15 07:23:22 PM PDT 24
Finished Jul 15 07:24:29 PM PDT 24
Peak memory 215964 kb
Host smart-78295f8c-e314-4748-8b0b-bd8bd499265a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716813131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2716813131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.886910080
Short name T177
Test name
Test status
Simulation time 276098649 ps
CPU time 2.87 seconds
Started Jul 15 07:23:21 PM PDT 24
Finished Jul 15 07:24:27 PM PDT 24
Peak memory 215564 kb
Host smart-abeaefa0-75be-4335-8236-a5863d691a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886910080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.88691
0080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3353083152
Short name T119
Test name
Test status
Simulation time 135688651 ps
CPU time 2.4 seconds
Started Jul 15 07:23:33 PM PDT 24
Finished Jul 15 07:24:31 PM PDT 24
Peak memory 217768 kb
Host smart-b5970038-2ca6-4b80-9c91-4207b42a2326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353083152 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3353083152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.739425504
Short name T1165
Test name
Test status
Simulation time 110622853 ps
CPU time 1.12 seconds
Started Jul 15 07:23:33 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 207440 kb
Host smart-8e3179f7-2b3b-4860-8c2d-c33f616abfb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739425504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.739425504 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.1645025251
Short name T1199
Test name
Test status
Simulation time 36506412 ps
CPU time 0.72 seconds
Started Jul 15 07:23:33 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 207108 kb
Host smart-40ad4ee1-ecbc-4a5c-afa4-95126cd27b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645025251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1645025251 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.658605777
Short name T1124
Test name
Test status
Simulation time 159673390 ps
CPU time 2.13 seconds
Started Jul 15 07:23:32 PM PDT 24
Finished Jul 15 07:24:31 PM PDT 24
Peak memory 215508 kb
Host smart-4ed53d67-f3c1-4779-a6e7-c87da8f9811f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658605777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr
_outstanding.658605777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3389638117
Short name T151
Test name
Test status
Simulation time 90921855 ps
CPU time 0.96 seconds
Started Jul 15 07:23:29 PM PDT 24
Finished Jul 15 07:24:29 PM PDT 24
Peak memory 215712 kb
Host smart-87baf94b-b630-4a7e-bf76-cb00d8f363fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389638117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.3389638117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3841872685
Short name T1168
Test name
Test status
Simulation time 117695095 ps
CPU time 1.95 seconds
Started Jul 15 07:23:26 PM PDT 24
Finished Jul 15 07:24:28 PM PDT 24
Peak memory 223248 kb
Host smart-6ea649ce-0381-40bf-8603-7e7916aad359
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841872685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.3841872685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3167043110
Short name T1132
Test name
Test status
Simulation time 195800990 ps
CPU time 2.34 seconds
Started Jul 15 07:23:32 PM PDT 24
Finished Jul 15 07:24:31 PM PDT 24
Peak memory 218288 kb
Host smart-39647e82-f03f-4c42-8745-3192036cd22f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167043110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3167
043110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3164905030
Short name T1100
Test name
Test status
Simulation time 30239881 ps
CPU time 1.44 seconds
Started Jul 15 07:23:38 PM PDT 24
Finished Jul 15 07:24:35 PM PDT 24
Peak memory 215756 kb
Host smart-3f408c0a-8ccd-4b78-a6e9-703f35069408
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164905030 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.3164905030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2884746679
Short name T1125
Test name
Test status
Simulation time 59436510 ps
CPU time 1.08 seconds
Started Jul 15 07:23:40 PM PDT 24
Finished Jul 15 07:24:35 PM PDT 24
Peak memory 215552 kb
Host smart-f7365b6c-c29c-4ce2-9b5e-261c9bf6e8b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884746679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2884746679 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.337809702
Short name T1131
Test name
Test status
Simulation time 16450852 ps
CPU time 0.78 seconds
Started Jul 15 07:23:33 PM PDT 24
Finished Jul 15 07:24:30 PM PDT 24
Peak memory 207060 kb
Host smart-c5e60fe7-a76e-4aa5-89b1-ccc65d35b3ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337809702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.337809702 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2845811854
Short name T1213
Test name
Test status
Simulation time 74173911 ps
CPU time 2.15 seconds
Started Jul 15 07:23:38 PM PDT 24
Finished Jul 15 07:24:36 PM PDT 24
Peak memory 215612 kb
Host smart-07904213-e2ff-4ca4-88a5-40eb4e729d5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845811854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.2845811854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1213630791
Short name T1095
Test name
Test status
Simulation time 26627547 ps
CPU time 1.02 seconds
Started Jul 15 07:23:34 PM PDT 24
Finished Jul 15 07:24:32 PM PDT 24
Peak memory 215932 kb
Host smart-dbf6f24f-277e-46ed-bae4-f1a9a82837cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213630791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.1213630791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1268300927
Short name T1154
Test name
Test status
Simulation time 68638142 ps
CPU time 1.91 seconds
Started Jul 15 07:23:33 PM PDT 24
Finished Jul 15 07:24:31 PM PDT 24
Peak memory 215660 kb
Host smart-b1309299-36c1-4f33-8954-1a634410018c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268300927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.1268300927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1593062064
Short name T1209
Test name
Test status
Simulation time 137983779 ps
CPU time 2.05 seconds
Started Jul 15 07:23:32 PM PDT 24
Finished Jul 15 07:24:31 PM PDT 24
Peak memory 215536 kb
Host smart-a3179717-982c-4521-abec-ac264a29d3db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593062064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1593062064 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1400657393
Short name T1214
Test name
Test status
Simulation time 487183748 ps
CPU time 2.76 seconds
Started Jul 15 07:23:33 PM PDT 24
Finished Jul 15 07:24:31 PM PDT 24
Peak memory 215556 kb
Host smart-f3787a54-433d-4b93-aa28-123f00e99e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400657393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1400
657393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2590087260
Short name T1159
Test name
Test status
Simulation time 45631596 ps
CPU time 1.94 seconds
Started Jul 15 07:23:38 PM PDT 24
Finished Jul 15 07:24:35 PM PDT 24
Peak memory 216192 kb
Host smart-2dfc13f3-549a-49a6-bd19-555e5c68a649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590087260 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2590087260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.4013822684
Short name T1178
Test name
Test status
Simulation time 132855103 ps
CPU time 1.03 seconds
Started Jul 15 07:23:39 PM PDT 24
Finished Jul 15 07:24:35 PM PDT 24
Peak memory 215616 kb
Host smart-22a000a1-519a-4af2-b00a-5854a29abeb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013822684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.4013822684 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.4028806468
Short name T1208
Test name
Test status
Simulation time 39308619 ps
CPU time 0.75 seconds
Started Jul 15 07:23:40 PM PDT 24
Finished Jul 15 07:24:34 PM PDT 24
Peak memory 207072 kb
Host smart-6dac6486-e9cf-4d38-a365-1e38b22944f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028806468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.4028806468 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.10966634
Short name T1086
Test name
Test status
Simulation time 26481020 ps
CPU time 1.49 seconds
Started Jul 15 07:23:38 PM PDT 24
Finished Jul 15 07:24:35 PM PDT 24
Peak memory 215968 kb
Host smart-3a7aac37-3c30-4852-bf53-7737c0458664
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10966634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_
outstanding.10966634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1730267887
Short name T108
Test name
Test status
Simulation time 59724048 ps
CPU time 0.84 seconds
Started Jul 15 07:23:38 PM PDT 24
Finished Jul 15 07:24:34 PM PDT 24
Peak memory 207244 kb
Host smart-d511a2b5-9997-47da-b2dc-8522a7f5999d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730267887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.1730267887 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.586796761
Short name T1200
Test name
Test status
Simulation time 117981178 ps
CPU time 1.84 seconds
Started Jul 15 07:23:42 PM PDT 24
Finished Jul 15 07:24:37 PM PDT 24
Peak memory 215644 kb
Host smart-1e07e83e-9339-403d-be25-5c367d7bea0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586796761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac
_shadow_reg_errors_with_csr_rw.586796761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2506829505
Short name T123
Test name
Test status
Simulation time 2417369030 ps
CPU time 3.73 seconds
Started Jul 15 07:23:38 PM PDT 24
Finished Jul 15 07:24:37 PM PDT 24
Peak memory 215704 kb
Host smart-cdfb62fd-f8c2-4776-9655-dc2482145ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506829505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2506829505 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2081698777
Short name T1135
Test name
Test status
Simulation time 1152677047 ps
CPU time 2.73 seconds
Started Jul 15 07:23:41 PM PDT 24
Finished Jul 15 07:24:38 PM PDT 24
Peak memory 215664 kb
Host smart-16174cae-4745-405a-9fdc-687c15b6c16d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081698777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2081
698777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3123370024
Short name T1123
Test name
Test status
Simulation time 345787341 ps
CPU time 1.69 seconds
Started Jul 15 07:23:42 PM PDT 24
Finished Jul 15 07:24:38 PM PDT 24
Peak memory 223784 kb
Host smart-70f30f2e-5770-476c-9d0d-d489a2565166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123370024 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.3123370024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1939951276
Short name T1219
Test name
Test status
Simulation time 22993563 ps
CPU time 0.96 seconds
Started Jul 15 07:23:38 PM PDT 24
Finished Jul 15 07:24:34 PM PDT 24
Peak memory 207192 kb
Host smart-84dbad42-27d4-48e9-840d-b35c4b72300d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939951276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1939951276 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.2417692174
Short name T1142
Test name
Test status
Simulation time 43817490 ps
CPU time 0.73 seconds
Started Jul 15 07:23:39 PM PDT 24
Finished Jul 15 07:24:34 PM PDT 24
Peak memory 207088 kb
Host smart-90494722-a327-4b16-928e-b0da545a8c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417692174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2417692174 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2983932017
Short name T1172
Test name
Test status
Simulation time 458302095 ps
CPU time 2.36 seconds
Started Jul 15 07:23:41 PM PDT 24
Finished Jul 15 07:24:37 PM PDT 24
Peak memory 215924 kb
Host smart-205f752b-b87b-435d-a834-03ae9b8ca326
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983932017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.2983932017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3573435045
Short name T107
Test name
Test status
Simulation time 19314469 ps
CPU time 0.99 seconds
Started Jul 15 07:23:37 PM PDT 24
Finished Jul 15 07:24:32 PM PDT 24
Peak memory 215716 kb
Host smart-4a9587b0-6f5d-4447-a0dc-88d7eaa484c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573435045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.3573435045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2308810552
Short name T101
Test name
Test status
Simulation time 40027285 ps
CPU time 1.59 seconds
Started Jul 15 07:23:37 PM PDT 24
Finished Jul 15 07:24:35 PM PDT 24
Peak memory 215716 kb
Host smart-f2b00b50-d8b5-4cb9-8349-199209e02c02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308810552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.2308810552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.949461412
Short name T1207
Test name
Test status
Simulation time 159285312 ps
CPU time 1.87 seconds
Started Jul 15 07:23:37 PM PDT 24
Finished Jul 15 07:24:35 PM PDT 24
Peak memory 218864 kb
Host smart-56e26b4f-90e9-4f3e-8ecf-bf07a5431a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949461412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.949461412 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3007246891
Short name T173
Test name
Test status
Simulation time 101764123 ps
CPU time 2.58 seconds
Started Jul 15 07:23:40 PM PDT 24
Finished Jul 15 07:24:36 PM PDT 24
Peak memory 215568 kb
Host smart-92a99d89-722b-4936-8daf-4985e08a4847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007246891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3007
246891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2139368810
Short name T1147
Test name
Test status
Simulation time 128188986 ps
CPU time 2.18 seconds
Started Jul 15 07:23:51 PM PDT 24
Finished Jul 15 07:24:43 PM PDT 24
Peak memory 216644 kb
Host smart-8e188654-0abd-4f05-9d47-6450d9c22d0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139368810 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2139368810 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.3008046790
Short name T1201
Test name
Test status
Simulation time 56247996 ps
CPU time 1.03 seconds
Started Jul 15 07:23:57 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207284 kb
Host smart-9d75c155-84bf-42cd-852a-9c27aacd9001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008046790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3008046790 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.2319740964
Short name T1229
Test name
Test status
Simulation time 48593926 ps
CPU time 0.75 seconds
Started Jul 15 07:23:49 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 207048 kb
Host smart-62a8aabe-1b48-44b2-a7d9-c25defc6e166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319740964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2319740964 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.448009749
Short name T1107
Test name
Test status
Simulation time 301225878 ps
CPU time 1.43 seconds
Started Jul 15 07:23:49 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 215984 kb
Host smart-46ace674-b57b-460b-acb8-551370198abf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448009749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr
_outstanding.448009749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2327099576
Short name T179
Test name
Test status
Simulation time 144290472 ps
CPU time 2.91 seconds
Started Jul 15 07:23:45 PM PDT 24
Finished Jul 15 07:24:43 PM PDT 24
Peak memory 215988 kb
Host smart-159aae84-dff3-4b10-beb6-ecd2afa74aac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327099576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.2327099576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1114972217
Short name T127
Test name
Test status
Simulation time 107820337 ps
CPU time 2.59 seconds
Started Jul 15 07:23:45 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 215652 kb
Host smart-b4110561-6456-46a0-865f-95d4ceb23c69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114972217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1114972217 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2716061764
Short name T174
Test name
Test status
Simulation time 375819527 ps
CPU time 5.05 seconds
Started Jul 15 07:23:45 PM PDT 24
Finished Jul 15 07:24:45 PM PDT 24
Peak memory 218360 kb
Host smart-832b638a-4e28-41d5-be92-57a091076a50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716061764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2716
061764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1642820069
Short name T1117
Test name
Test status
Simulation time 73006297 ps
CPU time 2.46 seconds
Started Jul 15 07:23:52 PM PDT 24
Finished Jul 15 07:24:45 PM PDT 24
Peak memory 217012 kb
Host smart-d017f732-9163-4fd6-b489-b90bf14ac61a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642820069 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1642820069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.816386980
Short name T1105
Test name
Test status
Simulation time 81569014 ps
CPU time 1.06 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:41 PM PDT 24
Peak memory 207416 kb
Host smart-529ad3fd-9929-4f7d-a88f-5b782a47ef8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816386980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.816386980 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2315463409
Short name T140
Test name
Test status
Simulation time 64748634 ps
CPU time 1.67 seconds
Started Jul 15 07:23:51 PM PDT 24
Finished Jul 15 07:24:43 PM PDT 24
Peak memory 215900 kb
Host smart-76b48bbd-a3ee-462f-aeee-a08f0a2983e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315463409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.2315463409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3854783912
Short name T97
Test name
Test status
Simulation time 280982977 ps
CPU time 0.93 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 207300 kb
Host smart-306be0a9-2742-4f23-8603-1ac99adc1788
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854783912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3854783912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2084280399
Short name T104
Test name
Test status
Simulation time 193758190 ps
CPU time 2.57 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 215924 kb
Host smart-b4d9a5d6-8a3b-4efb-b546-72fd95a2623d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084280399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.2084280399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.634630094
Short name T55
Test name
Test status
Simulation time 246281598 ps
CPU time 2.14 seconds
Started Jul 15 07:23:49 PM PDT 24
Finished Jul 15 07:24:43 PM PDT 24
Peak memory 219252 kb
Host smart-7f627b2c-300e-4949-8f24-4ba205276e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634630094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.634630094 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1117637957
Short name T1114
Test name
Test status
Simulation time 163306483 ps
CPU time 2.55 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 215692 kb
Host smart-53faf2b7-71a5-4d08-995d-366d3735fa53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117637957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1117
637957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1399741130
Short name T1121
Test name
Test status
Simulation time 152430145 ps
CPU time 7.83 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 207348 kb
Host smart-1f610a70-0f15-40e9-8b07-d8f6c9110c66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399741130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1399741
130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3904935497
Short name T1092
Test name
Test status
Simulation time 611599636 ps
CPU time 8.37 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 207396 kb
Host smart-c579f3e1-5a1c-40a2-bb7b-ebc8892ea463
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904935497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3904935
497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1459099568
Short name T1133
Test name
Test status
Simulation time 435354006 ps
CPU time 1.14 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 207352 kb
Host smart-c904f4f4-0473-48bf-b965-347b499245ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459099568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1459099
568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4241584939
Short name T1122
Test name
Test status
Simulation time 27507918 ps
CPU time 1.7 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:16 PM PDT 24
Peak memory 215308 kb
Host smart-967e0f57-d08b-4b9c-a1e9-2b67e084067d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241584939 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.4241584939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.382171390
Short name T1184
Test name
Test status
Simulation time 45417343 ps
CPU time 0.9 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 207132 kb
Host smart-ce7e9bac-51c9-4908-8dff-3d25830bfd64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382171390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.382171390 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.672649704
Short name T147
Test name
Test status
Simulation time 14683423 ps
CPU time 0.76 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 206156 kb
Host smart-cca42f8d-c8ef-4910-b36d-2d68d46b5c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672649704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.672649704 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1967179646
Short name T134
Test name
Test status
Simulation time 29210659 ps
CPU time 1.2 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215532 kb
Host smart-8b84cda8-2e44-42e6-8dde-28c06ab36d1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967179646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.1967179646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2376203706
Short name T1161
Test name
Test status
Simulation time 18090832 ps
CPU time 0.7 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 207116 kb
Host smart-763a222e-1b3c-46af-8655-f984a44d8500
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376203706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2376203706
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3499799429
Short name T1160
Test name
Test status
Simulation time 94155057 ps
CPU time 1.41 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215612 kb
Host smart-700f0345-6523-49b6-908c-6a0425384157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499799429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.3499799429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2510424677
Short name T105
Test name
Test status
Simulation time 176077610 ps
CPU time 1.3 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215988 kb
Host smart-6a7e2517-ff74-4829-a5ea-7ee9b84cbe47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510424677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.2510424677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2503869023
Short name T1217
Test name
Test status
Simulation time 121589395 ps
CPU time 2.83 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:19 PM PDT 24
Peak memory 223876 kb
Host smart-3ae4fac7-a504-4f57-9e24-332932e86427
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503869023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.2503869023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2559238945
Short name T128
Test name
Test status
Simulation time 47543077 ps
CPU time 1.36 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215612 kb
Host smart-f3006a7a-61f3-46d4-b06b-e3a41f526b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559238945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2559238945 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2139557099
Short name T1231
Test name
Test status
Simulation time 97532261 ps
CPU time 3.9 seconds
Started Jul 15 07:23:06 PM PDT 24
Finished Jul 15 07:24:20 PM PDT 24
Peak memory 215660 kb
Host smart-1997f5f0-b74e-4b10-a1e0-b3efd971ac35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139557099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.21395
57099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.858690281
Short name T1221
Test name
Test status
Simulation time 41170075 ps
CPU time 0.8 seconds
Started Jul 15 07:23:58 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207024 kb
Host smart-791fc29f-445a-44d5-b7d7-2df45dee26d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858690281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.858690281 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.82040210
Short name T167
Test name
Test status
Simulation time 14269712 ps
CPU time 0.76 seconds
Started Jul 15 07:23:57 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207024 kb
Host smart-cd5480aa-17fe-4aac-ae40-e15b508a5e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82040210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.82040210 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1862473184
Short name T1146
Test name
Test status
Simulation time 22790137 ps
CPU time 0.74 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 207052 kb
Host smart-ee13cb9b-b5f7-405d-bdbf-bd8438d87b96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862473184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1862473184 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.3063076034
Short name T1218
Test name
Test status
Simulation time 16231327 ps
CPU time 0.78 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 207104 kb
Host smart-615bd5ab-7744-4445-8f34-403efb51011e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063076034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3063076034 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.114666015
Short name T1136
Test name
Test status
Simulation time 13173513 ps
CPU time 0.77 seconds
Started Jul 15 07:23:58 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207028 kb
Host smart-7c5f7719-11b9-40bc-b019-27e14ce1ad86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114666015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.114666015 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.3927777621
Short name T1152
Test name
Test status
Simulation time 13609577 ps
CPU time 0.74 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 207116 kb
Host smart-9f8a9ccc-f995-4042-921e-8510efa3b82b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927777621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3927777621 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.727780646
Short name T1205
Test name
Test status
Simulation time 16709703 ps
CPU time 0.8 seconds
Started Jul 15 07:23:54 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207048 kb
Host smart-2040086f-ccf7-46b9-a92b-e3cd5f7ded33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727780646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.727780646 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.1382123964
Short name T148
Test name
Test status
Simulation time 44634283 ps
CPU time 0.76 seconds
Started Jul 15 07:23:53 PM PDT 24
Finished Jul 15 07:24:43 PM PDT 24
Peak memory 207048 kb
Host smart-e48c1aad-7e43-4a0a-923b-5537637c8909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382123964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1382123964 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.11606177
Short name T1120
Test name
Test status
Simulation time 37577853 ps
CPU time 0.73 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 207072 kb
Host smart-421b21b5-e0bd-49a8-a5f8-5a7e673a9cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11606177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.11606177 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3397541629
Short name T1112
Test name
Test status
Simulation time 19354649 ps
CPU time 0.8 seconds
Started Jul 15 07:23:48 PM PDT 24
Finished Jul 15 07:24:41 PM PDT 24
Peak memory 207104 kb
Host smart-224e7977-f8df-44b0-8c72-38a4070325ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397541629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3397541629 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.438857927
Short name T1230
Test name
Test status
Simulation time 2371300758 ps
CPU time 9.72 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:24 PM PDT 24
Peak memory 207516 kb
Host smart-5e6ae5e7-75e2-44f8-b360-7d0263f5cff7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438857927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.43885792
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2825404136
Short name T1099
Test name
Test status
Simulation time 967678506 ps
CPU time 18.61 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:32 PM PDT 24
Peak memory 207408 kb
Host smart-c844311f-f6f8-42c1-bb4b-ec3e07afe702
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825404136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2825404
136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1978317474
Short name T1166
Test name
Test status
Simulation time 45385858 ps
CPU time 0.98 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 207232 kb
Host smart-e74593d4-8b93-4572-a821-5f10f3c3fa66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978317474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1978317
474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2271583368
Short name T142
Test name
Test status
Simulation time 372777538 ps
CPU time 2.23 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:19 PM PDT 24
Peak memory 217232 kb
Host smart-134963ee-17fa-490c-9dc3-cfb8081610ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271583368 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2271583368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1796247873
Short name T1090
Test name
Test status
Simulation time 53156739 ps
CPU time 0.91 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 207220 kb
Host smart-9e203d66-d11f-4c78-9d5d-f6c686c6f41c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796247873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1796247873 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3486877269
Short name T1089
Test name
Test status
Simulation time 29003249 ps
CPU time 1.12 seconds
Started Jul 15 07:23:05 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215520 kb
Host smart-0db3c7d8-f158-4920-b40f-a7397435d128
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486877269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.3486877269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3105655188
Short name T1169
Test name
Test status
Simulation time 11698953 ps
CPU time 0.72 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 207128 kb
Host smart-00d64fc9-3df0-408c-bbd2-ccfcc5cd68c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105655188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3105655188
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.921687341
Short name T1102
Test name
Test status
Simulation time 26176613 ps
CPU time 1.35 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215784 kb
Host smart-2f226b20-15ea-4273-b64f-28606c8bd959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921687341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_
outstanding.921687341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.606364708
Short name T1110
Test name
Test status
Simulation time 53234742 ps
CPU time 1.08 seconds
Started Jul 15 07:23:03 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215936 kb
Host smart-a4145174-5367-4a88-aa14-852bc758848f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606364708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.606364708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2532683857
Short name T1225
Test name
Test status
Simulation time 66855232 ps
CPU time 1.73 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:16 PM PDT 24
Peak memory 215884 kb
Host smart-1a00df73-1597-494d-8005-2e9d05f8346d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532683857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.2532683857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.740092762
Short name T118
Test name
Test status
Simulation time 84181199 ps
CPU time 2.64 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 215508 kb
Host smart-9a8b5a62-1f71-4371-8add-44f007ab3032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740092762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.740092762 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2011309025
Short name T1185
Test name
Test status
Simulation time 138060916 ps
CPU time 2.81 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:16 PM PDT 24
Peak memory 215660 kb
Host smart-f3e72f25-d730-4fbe-94e2-de0f574e15af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011309025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.20113
09025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.1139944490
Short name T1137
Test name
Test status
Simulation time 14952420 ps
CPU time 0.8 seconds
Started Jul 15 07:23:49 PM PDT 24
Finished Jul 15 07:24:41 PM PDT 24
Peak memory 207060 kb
Host smart-e09d26ca-c4c6-4bce-b5b5-37736abb4343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139944490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1139944490 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.683356106
Short name T165
Test name
Test status
Simulation time 15314247 ps
CPU time 0.8 seconds
Started Jul 15 07:23:53 PM PDT 24
Finished Jul 15 07:24:43 PM PDT 24
Peak memory 207048 kb
Host smart-01bd08aa-0c85-47ef-8052-3aca285da4e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683356106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.683356106 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.1383181543
Short name T1098
Test name
Test status
Simulation time 14291392 ps
CPU time 0.78 seconds
Started Jul 15 07:23:50 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 207064 kb
Host smart-43021972-862e-4735-97b4-c936b3c9535a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383181543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1383181543 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.3222694404
Short name T1141
Test name
Test status
Simulation time 14496923 ps
CPU time 0.75 seconds
Started Jul 15 07:24:00 PM PDT 24
Finished Jul 15 07:24:46 PM PDT 24
Peak memory 207104 kb
Host smart-7b541da6-be57-4500-b8aa-e71dabcda5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222694404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3222694404 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.1998791286
Short name T121
Test name
Test status
Simulation time 44166362 ps
CPU time 0.74 seconds
Started Jul 15 07:23:58 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207052 kb
Host smart-e4e7d28f-bad1-4dd7-a701-c91085abebfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998791286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1998791286 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.2173051000
Short name T1126
Test name
Test status
Simulation time 19581067 ps
CPU time 0.74 seconds
Started Jul 15 07:23:58 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207000 kb
Host smart-21ddf10a-ff7c-4367-8fbb-8c2615196081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173051000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2173051000 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.2399215679
Short name T1094
Test name
Test status
Simulation time 13758692 ps
CPU time 0.79 seconds
Started Jul 15 07:23:58 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207128 kb
Host smart-a25b5c83-1a25-458b-8c60-e125fdfe885a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399215679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2399215679 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.3076950865
Short name T1104
Test name
Test status
Simulation time 12175626 ps
CPU time 0.74 seconds
Started Jul 15 07:23:57 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207088 kb
Host smart-5b2beb97-0f6c-4bf3-a18a-2dc0f5b728e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076950865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3076950865 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.2850062949
Short name T149
Test name
Test status
Simulation time 16796430 ps
CPU time 0.79 seconds
Started Jul 15 07:23:57 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207064 kb
Host smart-25bd6b7f-8fb6-4349-a971-c15ea6b8bdca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850062949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2850062949 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1879104620
Short name T1118
Test name
Test status
Simulation time 89427330 ps
CPU time 0.83 seconds
Started Jul 15 07:24:01 PM PDT 24
Finished Jul 15 07:24:46 PM PDT 24
Peak memory 207104 kb
Host smart-ab2616dd-3587-4517-aabc-d599a5dc519a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879104620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1879104620 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3049653129
Short name T144
Test name
Test status
Simulation time 2287343628 ps
CPU time 10.1 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:26 PM PDT 24
Peak memory 207452 kb
Host smart-20229c45-7261-4e4a-93d1-156f46112087
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049653129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3049653
129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1346067843
Short name T1181
Test name
Test status
Simulation time 289304278 ps
CPU time 14.88 seconds
Started Jul 15 07:23:10 PM PDT 24
Finished Jul 15 07:24:33 PM PDT 24
Peak memory 207392 kb
Host smart-376327a0-41ca-4ef1-a3bb-81fa5ec2fbf5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346067843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1346067
843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.204206635
Short name T1194
Test name
Test status
Simulation time 32239827 ps
CPU time 1.12 seconds
Started Jul 15 07:23:06 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 207396 kb
Host smart-4bfd0303-7bb5-40da-8c7e-42f2ae11449a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204206635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.20420663
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.63306336
Short name T1228
Test name
Test status
Simulation time 55276288 ps
CPU time 1.62 seconds
Started Jul 15 07:23:08 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 223728 kb
Host smart-173e70d5-c932-4b87-afb7-4792e75c3e03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63306336 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.63306336 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.958108882
Short name T1220
Test name
Test status
Simulation time 97418488 ps
CPU time 1.06 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 207400 kb
Host smart-b161596e-f855-456a-8c57-adf951387b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958108882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.958108882 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3250975252
Short name T1175
Test name
Test status
Simulation time 16278643 ps
CPU time 0.75 seconds
Started Jul 15 07:23:06 PM PDT 24
Finished Jul 15 07:24:16 PM PDT 24
Peak memory 207028 kb
Host smart-0ad08a13-235f-419a-a646-247f1edd10a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250975252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3250975252 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1884945894
Short name T1173
Test name
Test status
Simulation time 98573440 ps
CPU time 1.41 seconds
Started Jul 15 07:23:02 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 215528 kb
Host smart-b3d6ec7f-c922-49d1-bfd8-10bd39fcb969
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884945894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.1884945894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2485247509
Short name T1174
Test name
Test status
Simulation time 119849195 ps
CPU time 0.67 seconds
Started Jul 15 07:23:04 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 207164 kb
Host smart-502880e6-59ae-495f-9524-533b1276200c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485247509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2485247509
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1707384029
Short name T1091
Test name
Test status
Simulation time 72586006 ps
CPU time 2.11 seconds
Started Jul 15 07:23:06 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 215560 kb
Host smart-7bfce688-a84c-4117-93b7-58b7c6a9ef20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707384029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.1707384029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1599962203
Short name T106
Test name
Test status
Simulation time 118643162 ps
CPU time 1.1 seconds
Started Jul 15 07:23:05 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215924 kb
Host smart-0f618995-8be8-466a-ab9d-cb85648ed034
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599962203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.1599962203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2476999818
Short name T95
Test name
Test status
Simulation time 88435699 ps
CPU time 2.24 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:19 PM PDT 24
Peak memory 215936 kb
Host smart-82891483-9fa3-4693-b349-21a7d446593f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476999818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.2476999818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2947704930
Short name T117
Test name
Test status
Simulation time 79424349 ps
CPU time 2.42 seconds
Started Jul 15 07:23:06 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 215508 kb
Host smart-f0685c48-37a9-40f3-9b76-8cd367be4ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947704930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2947704930 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2755566374
Short name T1206
Test name
Test status
Simulation time 204462064 ps
CPU time 2.39 seconds
Started Jul 15 07:23:05 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 215644 kb
Host smart-706d1746-317b-4b51-bd5c-3c4cab8eca5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755566374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.27555
66374 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.1405418401
Short name T1204
Test name
Test status
Simulation time 16127040 ps
CPU time 0.79 seconds
Started Jul 15 07:23:57 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 207068 kb
Host smart-48de7b8e-11d0-4021-b8ec-883f31c2b416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405418401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1405418401 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2489667330
Short name T1193
Test name
Test status
Simulation time 13767030 ps
CPU time 0.78 seconds
Started Jul 15 07:24:05 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 207056 kb
Host smart-d14aab0e-2b96-4ac7-b756-8ed7c5305770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489667330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2489667330 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.3561760895
Short name T1111
Test name
Test status
Simulation time 39961553 ps
CPU time 0.8 seconds
Started Jul 15 07:24:07 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 207068 kb
Host smart-d6ff34a6-dcb8-47e3-b039-453fb895c1f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561760895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3561760895 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.1447235390
Short name T122
Test name
Test status
Simulation time 14719342 ps
CPU time 0.79 seconds
Started Jul 15 07:24:05 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 207100 kb
Host smart-ae18b4b7-13ba-47f4-9417-f7bd0c7e6e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447235390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1447235390 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.1816995823
Short name T168
Test name
Test status
Simulation time 46973359 ps
CPU time 0.77 seconds
Started Jul 15 07:24:04 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 207108 kb
Host smart-1e0d0248-8e7e-4a83-bb77-9e3a8cc55da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816995823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1816995823 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.3713813018
Short name T1196
Test name
Test status
Simulation time 45298101 ps
CPU time 0.73 seconds
Started Jul 15 07:24:11 PM PDT 24
Finished Jul 15 07:24:51 PM PDT 24
Peak memory 207024 kb
Host smart-a1780c14-b633-415a-a448-a6c919f0798d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713813018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3713813018 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1444487147
Short name T1127
Test name
Test status
Simulation time 87444805 ps
CPU time 0.8 seconds
Started Jul 15 07:24:06 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 207048 kb
Host smart-b53061d6-dda2-490c-9055-cd49c7c3936f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444487147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1444487147 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.228879845
Short name T1153
Test name
Test status
Simulation time 48572727 ps
CPU time 0.84 seconds
Started Jul 15 07:24:06 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 207088 kb
Host smart-6e20efb4-1892-42b9-abb1-4ed578824797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228879845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.228879845 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.3228128129
Short name T1183
Test name
Test status
Simulation time 52727989 ps
CPU time 0.81 seconds
Started Jul 15 07:24:11 PM PDT 24
Finished Jul 15 07:24:51 PM PDT 24
Peak memory 207024 kb
Host smart-954ebd75-90e4-4f1c-b2a7-54a1110a610d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228128129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3228128129 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1918643527
Short name T1109
Test name
Test status
Simulation time 44712178 ps
CPU time 0.73 seconds
Started Jul 15 07:24:05 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 207108 kb
Host smart-f6258297-7cbd-45b0-875d-4decf0bd3d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918643527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1918643527 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2328812414
Short name T1162
Test name
Test status
Simulation time 68445306 ps
CPU time 1.4 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 215628 kb
Host smart-e6e25b77-9fb3-411f-b12b-40568b4f0722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328812414 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.2328812414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2338515898
Short name T1223
Test name
Test status
Simulation time 27003993 ps
CPU time 1.04 seconds
Started Jul 15 07:23:08 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 207336 kb
Host smart-bb1fa024-940e-4e49-80d1-5fedb75c0c42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338515898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2338515898 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3345852017
Short name T1163
Test name
Test status
Simulation time 11781874 ps
CPU time 0.74 seconds
Started Jul 15 07:23:09 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 207088 kb
Host smart-8cd603ae-bdd6-4088-ae44-860f61bd36cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345852017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3345852017 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1267970688
Short name T1143
Test name
Test status
Simulation time 25465001 ps
CPU time 1.46 seconds
Started Jul 15 07:23:10 PM PDT 24
Finished Jul 15 07:24:19 PM PDT 24
Peak memory 215772 kb
Host smart-7d0a810c-4d2b-4ebd-acfa-f4b5977c8c3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267970688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.1267970688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.4074364041
Short name T1129
Test name
Test status
Simulation time 49398987 ps
CPU time 1.14 seconds
Started Jul 15 07:23:05 PM PDT 24
Finished Jul 15 07:24:15 PM PDT 24
Peak memory 215896 kb
Host smart-89cde6f0-5e35-423d-8eeb-4a4441908cba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074364041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.4074364041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3961592843
Short name T1186
Test name
Test status
Simulation time 374328241 ps
CPU time 2.59 seconds
Started Jul 15 07:23:10 PM PDT 24
Finished Jul 15 07:24:20 PM PDT 24
Peak memory 219560 kb
Host smart-4bcaa730-88ed-4404-8d7a-92dff148917c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961592843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3961592843 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3788479388
Short name T130
Test name
Test status
Simulation time 190703335 ps
CPU time 4.08 seconds
Started Jul 15 07:23:08 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 215596 kb
Host smart-1e318603-ad8a-4af6-bf42-305d5b1e7306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788479388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.37884
79388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.727315668
Short name T1108
Test name
Test status
Simulation time 47020233 ps
CPU time 1.75 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 216244 kb
Host smart-26165a0e-f081-4064-821c-d9c91f439768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727315668 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.727315668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1565354101
Short name T1130
Test name
Test status
Simulation time 173186168 ps
CPU time 1.15 seconds
Started Jul 15 07:23:08 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 207248 kb
Host smart-7b90ecec-fd93-49d1-8662-c98827aee18b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565354101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1565354101 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.1253782376
Short name T1179
Test name
Test status
Simulation time 15260010 ps
CPU time 0.79 seconds
Started Jul 15 07:23:10 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 207112 kb
Host smart-8c41fce1-7191-4a83-96e9-62c9efb1dbfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253782376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1253782376 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3143616498
Short name T152
Test name
Test status
Simulation time 2068820133 ps
CPU time 2.54 seconds
Started Jul 15 07:23:05 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 215872 kb
Host smart-d3c1305c-a204-4bd4-a913-2838e3ce52a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143616498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.3143616498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3344246371
Short name T1177
Test name
Test status
Simulation time 36454698 ps
CPU time 0.98 seconds
Started Jul 15 07:23:09 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 215760 kb
Host smart-9f6ea016-964d-4692-94fa-9233525aea1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344246371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3344246371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.800852176
Short name T1176
Test name
Test status
Simulation time 206057700 ps
CPU time 1.8 seconds
Started Jul 15 07:23:05 PM PDT 24
Finished Jul 15 07:24:16 PM PDT 24
Peak memory 223824 kb
Host smart-4cea2343-b3bf-4c52-b804-808dedf31674
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800852176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_
shadow_reg_errors_with_csr_rw.800852176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.244517901
Short name T125
Test name
Test status
Simulation time 88952706 ps
CPU time 2.59 seconds
Started Jul 15 07:23:05 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 215564 kb
Host smart-6b13c9e7-0161-4b4f-b6ca-9e270af755b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244517901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.244517901 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2974157217
Short name T1216
Test name
Test status
Simulation time 554356529 ps
CPU time 2.3 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 223816 kb
Host smart-97c4d510-2d7e-4fd0-a8a8-d49f0fbf7b37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974157217 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.2974157217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.3497465618
Short name T1084
Test name
Test status
Simulation time 27921213 ps
CPU time 1.1 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 207392 kb
Host smart-b8e2e59e-ae76-4eb2-b689-0bc959946464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497465618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3497465618 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1070566601
Short name T166
Test name
Test status
Simulation time 16878514 ps
CPU time 0.79 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 207072 kb
Host smart-08445bd3-7af9-4463-bdcb-2af6c0125bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070566601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1070566601 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2597585035
Short name T1155
Test name
Test status
Simulation time 123413623 ps
CPU time 1.55 seconds
Started Jul 15 07:23:08 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 215952 kb
Host smart-aea74da5-d798-4271-af2e-a39f83901918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597585035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2597585035 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2849865780
Short name T1224
Test name
Test status
Simulation time 193419890 ps
CPU time 1.07 seconds
Started Jul 15 07:23:09 PM PDT 24
Finished Jul 15 07:24:19 PM PDT 24
Peak memory 215940 kb
Host smart-25218030-5264-4b73-9288-089b91cefaf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849865780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2849865780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3378994979
Short name T1189
Test name
Test status
Simulation time 179718191 ps
CPU time 2.43 seconds
Started Jul 15 07:23:06 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 215916 kb
Host smart-755c1ef1-2311-4535-8148-19feb9fc02d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378994979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.3378994979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2631523927
Short name T169
Test name
Test status
Simulation time 359848006 ps
CPU time 3.22 seconds
Started Jul 15 07:23:09 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 215544 kb
Host smart-7f9e54a3-ce9a-471d-a481-d1dc87a1b1f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631523927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2631523927 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2990095444
Short name T54
Test name
Test status
Simulation time 314616468 ps
CPU time 2.34 seconds
Started Jul 15 07:23:09 PM PDT 24
Finished Jul 15 07:24:20 PM PDT 24
Peak memory 215636 kb
Host smart-85d0657a-5938-451f-aeb2-c2201fa1d6a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990095444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.29900
95444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2552458536
Short name T1227
Test name
Test status
Simulation time 24356734 ps
CPU time 1.67 seconds
Started Jul 15 07:23:15 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 216000 kb
Host smart-2f676627-4f4f-4baf-8b75-3a3f377c6764
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552458536 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2552458536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2666113629
Short name T1148
Test name
Test status
Simulation time 62192633 ps
CPU time 0.89 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 207228 kb
Host smart-8459f9ef-8863-4f01-8e9a-42a427c7e70c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666113629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2666113629 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3537775888
Short name T150
Test name
Test status
Simulation time 23499526 ps
CPU time 0.77 seconds
Started Jul 15 07:23:13 PM PDT 24
Finished Jul 15 07:24:20 PM PDT 24
Peak memory 207080 kb
Host smart-8a4f3bdb-7742-4aa0-b99e-87cc3c11ce36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537775888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3537775888 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2173551789
Short name T1210
Test name
Test status
Simulation time 85571128 ps
CPU time 1.6 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 215900 kb
Host smart-c3f8b735-07ba-403b-aed0-18bacfe152ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173551789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.2173551789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.215785764
Short name T1157
Test name
Test status
Simulation time 203148016 ps
CPU time 2.75 seconds
Started Jul 15 07:23:07 PM PDT 24
Finished Jul 15 07:24:19 PM PDT 24
Peak memory 216004 kb
Host smart-ff683deb-4e0d-42fe-8c9d-8bf627bbb56e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215785764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_
shadow_reg_errors_with_csr_rw.215785764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2719354042
Short name T1195
Test name
Test status
Simulation time 248024603 ps
CPU time 1.84 seconds
Started Jul 15 07:23:10 PM PDT 24
Finished Jul 15 07:24:19 PM PDT 24
Peak memory 215640 kb
Host smart-46c82911-a0ee-4d47-a802-602fad78b10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719354042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2719354042 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3257293706
Short name T114
Test name
Test status
Simulation time 485453266 ps
CPU time 5.4 seconds
Started Jul 15 07:23:18 PM PDT 24
Finished Jul 15 07:24:29 PM PDT 24
Peak memory 215540 kb
Host smart-b0152f42-90ce-4d1d-9e07-39583358a5d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257293706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.32572
93706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3026512640
Short name T1128
Test name
Test status
Simulation time 90166623 ps
CPU time 2.44 seconds
Started Jul 15 07:23:13 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 217648 kb
Host smart-d554fa93-0dcd-4148-ab25-c1555c09d3c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026512640 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3026512640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.720638399
Short name T1134
Test name
Test status
Simulation time 39017613 ps
CPU time 0.88 seconds
Started Jul 15 07:23:15 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 207228 kb
Host smart-0853437b-5615-4e4d-9212-d5759eda1092
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720638399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.720638399 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3966111852
Short name T1151
Test name
Test status
Simulation time 26281243 ps
CPU time 0.77 seconds
Started Jul 15 07:23:12 PM PDT 24
Finished Jul 15 07:24:20 PM PDT 24
Peak memory 207060 kb
Host smart-3b9fd285-6701-4a4e-9cc6-56fce1a1a065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966111852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3966111852 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2588519865
Short name T1116
Test name
Test status
Simulation time 43292911 ps
CPU time 2.11 seconds
Started Jul 15 07:23:15 PM PDT 24
Finished Jul 15 07:24:23 PM PDT 24
Peak memory 215568 kb
Host smart-56599045-91b7-4a6f-b178-41186f6af70f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588519865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2588519865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2045643245
Short name T1140
Test name
Test status
Simulation time 99479479 ps
CPU time 1.2 seconds
Started Jul 15 07:23:15 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 215972 kb
Host smart-417788d0-2446-4b22-ab27-6cfa21c68369
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045643245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.2045643245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1149894892
Short name T1106
Test name
Test status
Simulation time 217908376 ps
CPU time 2.79 seconds
Started Jul 15 07:23:19 PM PDT 24
Finished Jul 15 07:24:27 PM PDT 24
Peak memory 223528 kb
Host smart-eaa93434-882f-4e73-9ac2-a53c2d719a09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149894892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1149894892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2582742202
Short name T124
Test name
Test status
Simulation time 468962355 ps
CPU time 1.62 seconds
Started Jul 15 07:23:14 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 218660 kb
Host smart-07db96db-f4f1-43df-b3b8-2952ba58bce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582742202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2582742202 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/default/0.kmac_alert_test.3829359568
Short name T875
Test name
Test status
Simulation time 16536245 ps
CPU time 0.8 seconds
Started Jul 15 06:32:33 PM PDT 24
Finished Jul 15 06:32:34 PM PDT 24
Peak memory 205232 kb
Host smart-7d5f1ae9-d9c1-4c54-a253-f7078f7fadca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829359568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3829359568 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.2606269711
Short name T24
Test name
Test status
Simulation time 2999387680 ps
CPU time 187.18 seconds
Started Jul 15 06:32:29 PM PDT 24
Finished Jul 15 06:35:37 PM PDT 24
Peak memory 239012 kb
Host smart-6b2723eb-4d7c-49ad-b287-54f92dc2af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606269711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2606269711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.161640729
Short name T1022
Test name
Test status
Simulation time 7666978258 ps
CPU time 102.5 seconds
Started Jul 15 06:32:32 PM PDT 24
Finished Jul 15 06:34:15 PM PDT 24
Peak memory 229208 kb
Host smart-6520beb7-ee3f-4faa-9028-e92f45887944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161640729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.161640729 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2253725804
Short name T920
Test name
Test status
Simulation time 3481129322 ps
CPU time 283.91 seconds
Started Jul 15 06:32:29 PM PDT 24
Finished Jul 15 06:37:13 PM PDT 24
Peak memory 227508 kb
Host smart-dddc7e4f-542e-4517-9b36-e3aaf628094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253725804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2253725804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.1332007058
Short name T364
Test name
Test status
Simulation time 4288948728 ps
CPU time 26.34 seconds
Started Jul 15 06:32:30 PM PDT 24
Finished Jul 15 06:32:57 PM PDT 24
Peak memory 218848 kb
Host smart-0dd328f7-b1e0-456b-9191-c79f354ad196
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332007058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1332007058 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.3844827620
Short name T654
Test name
Test status
Simulation time 274138646 ps
CPU time 18.93 seconds
Started Jul 15 06:32:34 PM PDT 24
Finished Jul 15 06:32:54 PM PDT 24
Peak memory 223516 kb
Host smart-5c59e227-4ae4-4e29-a6c7-221ba5017b17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3844827620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3844827620 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.1950572370
Short name T992
Test name
Test status
Simulation time 219060946 ps
CPU time 2.71 seconds
Started Jul 15 06:32:45 PM PDT 24
Finished Jul 15 06:32:50 PM PDT 24
Peak memory 215432 kb
Host smart-ede06ce1-9490-4cb7-92e8-7dc1928683e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950572370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1950572370 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.779674506
Short name T842
Test name
Test status
Simulation time 4041973639 ps
CPU time 62.81 seconds
Started Jul 15 06:32:34 PM PDT 24
Finished Jul 15 06:33:37 PM PDT 24
Peak memory 225228 kb
Host smart-73f0a964-cfee-46ba-88fe-468e780ca7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779674506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.779674506 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.3146637459
Short name T662
Test name
Test status
Simulation time 27183378069 ps
CPU time 212.43 seconds
Started Jul 15 06:32:33 PM PDT 24
Finished Jul 15 06:36:07 PM PDT 24
Peak memory 249552 kb
Host smart-c5da02a2-9b4b-4475-a93e-c40cd06962db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146637459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3146637459 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.2097893159
Short name T605
Test name
Test status
Simulation time 2064398037 ps
CPU time 3.12 seconds
Started Jul 15 06:32:31 PM PDT 24
Finished Jul 15 06:32:34 PM PDT 24
Peak memory 207316 kb
Host smart-82c5bef5-b149-4832-b57c-a69def162dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097893159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2097893159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.914519782
Short name T440
Test name
Test status
Simulation time 54348598 ps
CPU time 1.35 seconds
Started Jul 15 06:32:32 PM PDT 24
Finished Jul 15 06:32:34 PM PDT 24
Peak memory 215532 kb
Host smart-89f3036b-ec2f-4e90-8d22-ab9f6fdb72b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914519782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.914519782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.4162614344
Short name T1080
Test name
Test status
Simulation time 41541540539 ps
CPU time 1114.32 seconds
Started Jul 15 06:32:29 PM PDT 24
Finished Jul 15 06:51:04 PM PDT 24
Peak memory 328124 kb
Host smart-522cc0c3-ccd8-4cd8-bd20-f73ace334eca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162614344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.4162614344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.3362286620
Short name T950
Test name
Test status
Simulation time 7659811510 ps
CPU time 162.51 seconds
Started Jul 15 06:32:30 PM PDT 24
Finished Jul 15 06:35:13 PM PDT 24
Peak memory 237956 kb
Host smart-38300f63-9d54-4c03-845e-7098d2625300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362286620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3362286620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.2933294786
Short name T11
Test name
Test status
Simulation time 4130230577 ps
CPU time 23.94 seconds
Started Jul 15 06:32:31 PM PDT 24
Finished Jul 15 06:32:56 PM PDT 24
Peak memory 241452 kb
Host smart-ecede99b-fd86-474d-a439-e7008596d906
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933294786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2933294786 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.1391977114
Short name T212
Test name
Test status
Simulation time 39086036980 ps
CPU time 296.54 seconds
Started Jul 15 06:32:25 PM PDT 24
Finished Jul 15 06:37:22 PM PDT 24
Peak memory 241756 kb
Host smart-236e58a7-1abf-44cf-9f4f-c1acbe905826
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391977114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1391977114 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.3246116020
Short name T462
Test name
Test status
Simulation time 9447652062 ps
CPU time 57.28 seconds
Started Jul 15 06:32:26 PM PDT 24
Finished Jul 15 06:33:24 PM PDT 24
Peak memory 218628 kb
Host smart-20948c25-6656-4feb-8325-faff01919c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246116020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3246116020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.924258718
Short name T19
Test name
Test status
Simulation time 3504805958 ps
CPU time 28.67 seconds
Started Jul 15 06:32:34 PM PDT 24
Finished Jul 15 06:33:04 PM PDT 24
Peak memory 223888 kb
Host smart-bf26b78d-e320-4513-8a32-6bb17b466734
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=924258718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.924258718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.4138144904
Short name T1074
Test name
Test status
Simulation time 425651356 ps
CPU time 4.88 seconds
Started Jul 15 06:32:34 PM PDT 24
Finished Jul 15 06:32:40 PM PDT 24
Peak memory 215640 kb
Host smart-87049662-d188-4893-bbed-7e0902123fd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138144904 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.4138144904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.719795879
Short name T223
Test name
Test status
Simulation time 70087004 ps
CPU time 3.74 seconds
Started Jul 15 06:32:34 PM PDT 24
Finished Jul 15 06:32:38 PM PDT 24
Peak memory 215412 kb
Host smart-34970cb6-7edc-4f44-a96f-0baad9c0c37a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719795879 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.kmac_test_vectors_kmac_xof.719795879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.2505530295
Short name T500
Test name
Test status
Simulation time 1607922776869 ps
CPU time 2126.35 seconds
Started Jul 15 06:32:30 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 389280 kb
Host smart-e15a49b8-834a-47ab-9bbb-c72532a057ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2505530295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2505530295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.754053938
Short name T342
Test name
Test status
Simulation time 18803410850 ps
CPU time 1432.99 seconds
Started Jul 15 06:32:29 PM PDT 24
Finished Jul 15 06:56:23 PM PDT 24
Peak memory 387720 kb
Host smart-9cff4178-592e-4916-a004-79eb690c15a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=754053938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.754053938 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.2944382292
Short name T787
Test name
Test status
Simulation time 247991967355 ps
CPU time 1296.35 seconds
Started Jul 15 06:32:31 PM PDT 24
Finished Jul 15 06:54:08 PM PDT 24
Peak memory 336060 kb
Host smart-50df7896-78b9-4ea5-93cd-e710fd2af898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2944382292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2944382292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.188222320
Short name T743
Test name
Test status
Simulation time 196857353170 ps
CPU time 1001.16 seconds
Started Jul 15 06:32:34 PM PDT 24
Finished Jul 15 06:49:16 PM PDT 24
Peak memory 296452 kb
Host smart-64e97d74-645a-45ff-a6cb-8baed4b93e6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=188222320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.188222320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.3534497969
Short name T379
Test name
Test status
Simulation time 491563121842 ps
CPU time 4587.03 seconds
Started Jul 15 06:32:31 PM PDT 24
Finished Jul 15 07:48:59 PM PDT 24
Peak memory 652156 kb
Host smart-44422723-aa67-49a3-bd30-6e429d920f04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3534497969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3534497969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.1703398408
Short name T294
Test name
Test status
Simulation time 212956887287 ps
CPU time 3815.74 seconds
Started Jul 15 06:32:31 PM PDT 24
Finished Jul 15 07:36:08 PM PDT 24
Peak memory 557640 kb
Host smart-4cc464c5-4891-4ecd-8fe7-a3ab6549e8df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1703398408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1703398408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.3801640158
Short name T655
Test name
Test status
Simulation time 230758280 ps
CPU time 0.76 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 06:32:38 PM PDT 24
Peak memory 205252 kb
Host smart-e1841da1-92d3-49af-b2d4-89b0dc134863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801640158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3801640158 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.1997789292
Short name T595
Test name
Test status
Simulation time 5772535356 ps
CPU time 144.92 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 06:35:03 PM PDT 24
Peak memory 233904 kb
Host smart-88a9d8fd-9053-4fda-9f0e-8d35f36c92c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997789292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1997789292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.2217319994
Short name T706
Test name
Test status
Simulation time 4278456849 ps
CPU time 107.07 seconds
Started Jul 15 06:32:35 PM PDT 24
Finished Jul 15 06:34:23 PM PDT 24
Peak memory 231204 kb
Host smart-33b475d5-bb38-44f4-b946-ba0bd49ff55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217319994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2217319994 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.3035331712
Short name T1071
Test name
Test status
Simulation time 52619379641 ps
CPU time 790.4 seconds
Started Jul 15 06:32:38 PM PDT 24
Finished Jul 15 06:45:49 PM PDT 24
Peak memory 231768 kb
Host smart-42179a9a-8b97-41b4-b665-5bce98502aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035331712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3035331712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.469323054
Short name T1001
Test name
Test status
Simulation time 675487007 ps
CPU time 17.83 seconds
Started Jul 15 06:32:40 PM PDT 24
Finished Jul 15 06:33:00 PM PDT 24
Peak memory 223592 kb
Host smart-f42e9f47-7919-47f5-9912-b8cd1298151f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=469323054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.469323054 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.2910553137
Short name T271
Test name
Test status
Simulation time 4313059020 ps
CPU time 31.84 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 06:33:10 PM PDT 24
Peak memory 223788 kb
Host smart-a910b4ae-3e1a-438e-8079-6786b6b71450
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2910553137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2910553137 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.3049876255
Short name T881
Test name
Test status
Simulation time 2464173070 ps
CPU time 6.17 seconds
Started Jul 15 06:32:40 PM PDT 24
Finished Jul 15 06:32:48 PM PDT 24
Peak memory 223080 kb
Host smart-53e9f48d-e5f8-44fe-abb7-bfa4264c2935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049876255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3049876255 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.3876146710
Short name T547
Test name
Test status
Simulation time 8438702629 ps
CPU time 121.94 seconds
Started Jul 15 06:32:36 PM PDT 24
Finished Jul 15 06:34:39 PM PDT 24
Peak memory 232308 kb
Host smart-081135c0-217e-4950-8dda-8aca3b5a2964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876146710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.3876146710 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.1104761573
Short name T397
Test name
Test status
Simulation time 430429061 ps
CPU time 31.59 seconds
Started Jul 15 06:32:36 PM PDT 24
Finished Jul 15 06:33:08 PM PDT 24
Peak memory 232128 kb
Host smart-86a5159c-3b36-4078-a5ab-e21bfc390420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104761573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1104761573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.519281576
Short name T730
Test name
Test status
Simulation time 2644927231 ps
CPU time 3.68 seconds
Started Jul 15 06:32:40 PM PDT 24
Finished Jul 15 06:32:45 PM PDT 24
Peak memory 207400 kb
Host smart-babd683a-b355-4dfe-a6aa-6efa05cb7932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519281576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.519281576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.529931884
Short name T626
Test name
Test status
Simulation time 43702685 ps
CPU time 1.24 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 06:32:39 PM PDT 24
Peak memory 215536 kb
Host smart-6f038cb5-fe6e-442f-a25e-da1501a9b1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529931884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.529931884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.2811064269
Short name T73
Test name
Test status
Simulation time 266687640140 ps
CPU time 2035.95 seconds
Started Jul 15 06:32:33 PM PDT 24
Finished Jul 15 07:06:30 PM PDT 24
Peak memory 415268 kb
Host smart-c264f4da-ab92-4895-af50-a98e4d01fff5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811064269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.2811064269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.3154975727
Short name T301
Test name
Test status
Simulation time 7494702758 ps
CPU time 9.21 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 06:32:47 PM PDT 24
Peak memory 223860 kb
Host smart-2e9773c1-b40a-4e71-a9ce-6589251985e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154975727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3154975727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.2693379443
Short name T76
Test name
Test status
Simulation time 6235089198 ps
CPU time 42.89 seconds
Started Jul 15 06:32:36 PM PDT 24
Finished Jul 15 06:33:20 PM PDT 24
Peak memory 255820 kb
Host smart-67590f38-aabb-4f7b-a708-a5e84eb6af92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693379443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2693379443 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.20800212
Short name T418
Test name
Test status
Simulation time 997977703 ps
CPU time 18.56 seconds
Started Jul 15 06:32:31 PM PDT 24
Finished Jul 15 06:32:50 PM PDT 24
Peak memory 219748 kb
Host smart-3657db6d-c695-404b-a78d-bc81e6d43d62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.20800212 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2441009025
Short name T854
Test name
Test status
Simulation time 48195692630 ps
CPU time 65.26 seconds
Started Jul 15 06:32:31 PM PDT 24
Finished Jul 15 06:33:37 PM PDT 24
Peak memory 221236 kb
Host smart-c66eef75-6408-4bf9-80ae-125ded770895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441009025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2441009025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.3890841907
Short name T26
Test name
Test status
Simulation time 14768949910 ps
CPU time 101.38 seconds
Started Jul 15 06:32:39 PM PDT 24
Finished Jul 15 06:34:22 PM PDT 24
Peak memory 240264 kb
Host smart-732d7025-6a6e-44a4-ab0f-08f5bce710de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3890841907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3890841907 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.3870168442
Short name T426
Test name
Test status
Simulation time 186497970 ps
CPU time 4.97 seconds
Started Jul 15 06:32:36 PM PDT 24
Finished Jul 15 06:32:41 PM PDT 24
Peak memory 215604 kb
Host smart-c7a8c31c-ef7f-4fc0-88ab-f3193a816c72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870168442 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.3870168442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1636237151
Short name T937
Test name
Test status
Simulation time 468530202 ps
CPU time 4.61 seconds
Started Jul 15 06:32:34 PM PDT 24
Finished Jul 15 06:32:39 PM PDT 24
Peak memory 215712 kb
Host smart-db45b085-ce28-4491-9fbc-7fb7f07eff2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636237151 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1636237151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.3401625973
Short name T481
Test name
Test status
Simulation time 201588445193 ps
CPU time 1967.88 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 389556 kb
Host smart-7b20fd07-f3c3-4c93-b898-f97353217e03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3401625973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3401625973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.338570427
Short name T224
Test name
Test status
Simulation time 354858372869 ps
CPU time 2027.43 seconds
Started Jul 15 06:32:39 PM PDT 24
Finished Jul 15 07:06:28 PM PDT 24
Peak memory 376868 kb
Host smart-a4f12869-7140-4c54-8176-1dca713bab19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=338570427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.338570427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.1626884996
Short name T484
Test name
Test status
Simulation time 70818719318 ps
CPU time 1446.66 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 06:56:45 PM PDT 24
Peak memory 334392 kb
Host smart-0fa4d3b8-dd46-4dca-9e5b-4ffcaab321dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1626884996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1626884996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.263387474
Short name T181
Test name
Test status
Simulation time 9721914636 ps
CPU time 778.37 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 06:45:36 PM PDT 24
Peak memory 293016 kb
Host smart-ca2b010f-2d00-4604-920e-a12f26ae732a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=263387474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.263387474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3541079051
Short name T834
Test name
Test status
Simulation time 150520172677 ps
CPU time 3881.96 seconds
Started Jul 15 06:32:36 PM PDT 24
Finished Jul 15 07:37:19 PM PDT 24
Peak memory 556796 kb
Host smart-be72ace3-4a9e-45db-bb12-a46a97f3cb7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3541079051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3541079051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.3994711854
Short name T624
Test name
Test status
Simulation time 40426760 ps
CPU time 0.8 seconds
Started Jul 15 06:33:23 PM PDT 24
Finished Jul 15 06:33:25 PM PDT 24
Peak memory 205280 kb
Host smart-80142390-a7bc-431b-8a35-028c766fb089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994711854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3994711854 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.1696110782
Short name T899
Test name
Test status
Simulation time 11364187884 ps
CPU time 40.35 seconds
Started Jul 15 06:33:18 PM PDT 24
Finished Jul 15 06:33:59 PM PDT 24
Peak memory 223184 kb
Host smart-23cea8a9-eb6a-4142-afb1-50d403b0bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696110782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1696110782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.1662528501
Short name T765
Test name
Test status
Simulation time 18176671446 ps
CPU time 291.55 seconds
Started Jul 15 06:33:17 PM PDT 24
Finished Jul 15 06:38:10 PM PDT 24
Peak memory 226312 kb
Host smart-a22c81c5-3695-4e76-b125-11b8104ba91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662528501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1662528501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.889191585
Short name T832
Test name
Test status
Simulation time 373582006 ps
CPU time 24.58 seconds
Started Jul 15 06:33:14 PM PDT 24
Finished Jul 15 06:33:39 PM PDT 24
Peak memory 236072 kb
Host smart-25c8a10d-6e82-4b0c-9a39-990d2adf0ba1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=889191585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.889191585 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2217262460
Short name T736
Test name
Test status
Simulation time 634918683 ps
CPU time 11.27 seconds
Started Jul 15 06:33:24 PM PDT 24
Finished Jul 15 06:33:36 PM PDT 24
Peak memory 215712 kb
Host smart-237b324d-0c46-44eb-bc71-aecb2b414f91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2217262460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2217262460 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.2297928517
Short name T690
Test name
Test status
Simulation time 9789016049 ps
CPU time 185.49 seconds
Started Jul 15 06:33:21 PM PDT 24
Finished Jul 15 06:36:27 PM PDT 24
Peak memory 238036 kb
Host smart-883feb8e-56a5-4071-b980-8b5e78eb6fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297928517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2297928517 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.1169993524
Short name T297
Test name
Test status
Simulation time 19113719909 ps
CPU time 258.85 seconds
Started Jul 15 06:33:19 PM PDT 24
Finished Jul 15 06:37:38 PM PDT 24
Peak memory 250040 kb
Host smart-0612fcdb-5938-42cc-91e3-c34ad0d9b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169993524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1169993524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.3297395714
Short name T1075
Test name
Test status
Simulation time 3236474743 ps
CPU time 4.47 seconds
Started Jul 15 06:33:16 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 215548 kb
Host smart-cee12e94-685d-40d8-b56b-0c22812ba756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297395714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3297395714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.3662879528
Short name T782
Test name
Test status
Simulation time 7064110198 ps
CPU time 546.79 seconds
Started Jul 15 06:33:16 PM PDT 24
Finished Jul 15 06:42:23 PM PDT 24
Peak memory 280928 kb
Host smart-ace88751-3c76-4853-a8cf-fdf1ba818ed5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662879528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.3662879528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.3358609764
Short name T687
Test name
Test status
Simulation time 9033668216 ps
CPU time 90.54 seconds
Started Jul 15 06:33:20 PM PDT 24
Finished Jul 15 06:34:51 PM PDT 24
Peak memory 227844 kb
Host smart-170f2f3b-ea9b-42ce-b975-56bb58656f95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358609764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3358609764 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.2618909995
Short name T568
Test name
Test status
Simulation time 2272214681 ps
CPU time 37.48 seconds
Started Jul 15 06:33:16 PM PDT 24
Finished Jul 15 06:33:54 PM PDT 24
Peak memory 219272 kb
Host smart-361f01cb-cda1-455b-99a1-70d7f42b2cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618909995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2618909995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.2122459436
Short name T1065
Test name
Test status
Simulation time 14774614078 ps
CPU time 73.11 seconds
Started Jul 15 06:33:24 PM PDT 24
Finished Jul 15 06:34:38 PM PDT 24
Peak memory 226504 kb
Host smart-962aa846-fe1f-4ea0-84ad-2c23efd951d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2122459436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2122459436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.4179332558
Short name T685
Test name
Test status
Simulation time 256011976 ps
CPU time 4.05 seconds
Started Jul 15 06:33:13 PM PDT 24
Finished Jul 15 06:33:18 PM PDT 24
Peak memory 215688 kb
Host smart-29c92fc3-68ea-4657-a4b5-f5e866626de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179332558 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.4179332558 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.1126900412
Short name T1040
Test name
Test status
Simulation time 181280045 ps
CPU time 4.69 seconds
Started Jul 15 06:33:15 PM PDT 24
Finished Jul 15 06:33:20 PM PDT 24
Peak memory 215572 kb
Host smart-575ebb6a-f261-44fc-89c5-4380223db58a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126900412 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.1126900412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.1659505455
Short name T281
Test name
Test status
Simulation time 64980132570 ps
CPU time 1699.5 seconds
Started Jul 15 06:33:15 PM PDT 24
Finished Jul 15 07:01:35 PM PDT 24
Peak memory 392204 kb
Host smart-2f7a25e4-15c5-40bf-bfe1-59fd5dbe2923
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1659505455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.1659505455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.1478179326
Short name T482
Test name
Test status
Simulation time 19281224902 ps
CPU time 1609.59 seconds
Started Jul 15 06:33:18 PM PDT 24
Finished Jul 15 07:00:08 PM PDT 24
Peak memory 374240 kb
Host smart-84434b84-4870-4c89-94f6-d1171f0cf0c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1478179326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.1478179326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.4156597399
Short name T471
Test name
Test status
Simulation time 34866498126 ps
CPU time 1153.26 seconds
Started Jul 15 06:33:16 PM PDT 24
Finished Jul 15 06:52:30 PM PDT 24
Peak memory 334376 kb
Host smart-5fd28a1a-4757-4ee3-9d77-48ff2c806d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4156597399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.4156597399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.4275140261
Short name T977
Test name
Test status
Simulation time 39998793597 ps
CPU time 846.24 seconds
Started Jul 15 06:33:17 PM PDT 24
Finished Jul 15 06:47:24 PM PDT 24
Peak memory 297084 kb
Host smart-95249291-0701-41ad-aeeb-4cf1416f9c89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4275140261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.4275140261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.3439946056
Short name T368
Test name
Test status
Simulation time 50796033815 ps
CPU time 4275.75 seconds
Started Jul 15 06:33:19 PM PDT 24
Finished Jul 15 07:44:36 PM PDT 24
Peak memory 639064 kb
Host smart-e3708f22-6714-4e92-b5e8-aa71b941388b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3439946056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3439946056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.2930184108
Short name T197
Test name
Test status
Simulation time 175873829202 ps
CPU time 3529.1 seconds
Started Jul 15 06:33:17 PM PDT 24
Finished Jul 15 07:32:07 PM PDT 24
Peak memory 575008 kb
Host smart-c8c50722-2a24-40ab-8545-ae388fccfddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2930184108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.2930184108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_app.2659419991
Short name T1044
Test name
Test status
Simulation time 21974127004 ps
CPU time 105.38 seconds
Started Jul 15 06:33:24 PM PDT 24
Finished Jul 15 06:35:10 PM PDT 24
Peak memory 229448 kb
Host smart-061ef038-a82d-4ca0-81e4-4e1ee12c3122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659419991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2659419991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.2242262566
Short name T341
Test name
Test status
Simulation time 12876495162 ps
CPU time 359.19 seconds
Started Jul 15 06:33:23 PM PDT 24
Finished Jul 15 06:39:23 PM PDT 24
Peak memory 228872 kb
Host smart-4d0c2afb-97b4-4ff6-b2f5-0de28eff1021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242262566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2242262566 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.396505871
Short name T348
Test name
Test status
Simulation time 1280901664 ps
CPU time 7.95 seconds
Started Jul 15 06:33:36 PM PDT 24
Finished Jul 15 06:33:44 PM PDT 24
Peak memory 223460 kb
Host smart-9ca45de3-fd10-485f-a75b-a7ce1cb2fcaf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396505871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.396505871 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.1160636021
Short name T501
Test name
Test status
Simulation time 1009066205 ps
CPU time 9.5 seconds
Started Jul 15 06:33:32 PM PDT 24
Finished Jul 15 06:33:42 PM PDT 24
Peak memory 215612 kb
Host smart-b13207b0-55f5-40f4-ba05-43fb697d2f7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1160636021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1160636021 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.1116779677
Short name T267
Test name
Test status
Simulation time 18447566666 ps
CPU time 83.72 seconds
Started Jul 15 06:33:25 PM PDT 24
Finished Jul 15 06:34:49 PM PDT 24
Peak memory 226516 kb
Host smart-ba4be9a4-01cb-4d4d-baaa-6b0816004517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116779677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1116779677 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.2296466113
Short name T669
Test name
Test status
Simulation time 6865293366 ps
CPU time 241.86 seconds
Started Jul 15 06:33:24 PM PDT 24
Finished Jul 15 06:37:27 PM PDT 24
Peak memory 251288 kb
Host smart-63d30b14-b571-4a46-93d8-64655de15d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296466113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2296466113 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.2448699487
Short name T969
Test name
Test status
Simulation time 1465587466 ps
CPU time 7.56 seconds
Started Jul 15 06:33:34 PM PDT 24
Finished Jul 15 06:33:42 PM PDT 24
Peak memory 215360 kb
Host smart-90292ee1-6d23-4ed7-bf60-2209115c8b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448699487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2448699487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.1068208535
Short name T837
Test name
Test status
Simulation time 126950031 ps
CPU time 1.26 seconds
Started Jul 15 06:33:36 PM PDT 24
Finished Jul 15 06:33:38 PM PDT 24
Peak memory 215524 kb
Host smart-d5a8c6d6-e3b0-4eab-b152-821214e9ec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068208535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1068208535 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.2199692808
Short name T420
Test name
Test status
Simulation time 22331119804 ps
CPU time 151.97 seconds
Started Jul 15 06:33:23 PM PDT 24
Finished Jul 15 06:35:56 PM PDT 24
Peak memory 230492 kb
Host smart-20ebd91e-6a76-43d4-91ee-43f1b786defe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199692808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.2199692808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.151426739
Short name T225
Test name
Test status
Simulation time 3324920056 ps
CPU time 68.12 seconds
Started Jul 15 06:33:24 PM PDT 24
Finished Jul 15 06:34:33 PM PDT 24
Peak memory 223828 kb
Host smart-6013662a-6f2c-4671-aa83-c44c10932f7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151426739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.151426739 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.1841935943
Short name T841
Test name
Test status
Simulation time 1826484378 ps
CPU time 37.59 seconds
Started Jul 15 06:33:24 PM PDT 24
Finished Jul 15 06:34:02 PM PDT 24
Peak memory 219368 kb
Host smart-a32a7635-7d5f-441d-a472-cab1f48b715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841935943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1841935943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.462224292
Short name T1063
Test name
Test status
Simulation time 29140228793 ps
CPU time 1044.74 seconds
Started Jul 15 06:33:27 PM PDT 24
Finished Jul 15 06:50:52 PM PDT 24
Peak memory 362088 kb
Host smart-98008128-3831-42c3-a28c-ccbc2c6c7921
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=462224292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.462224292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.2731645670
Short name T305
Test name
Test status
Simulation time 65513876 ps
CPU time 4.14 seconds
Started Jul 15 06:33:22 PM PDT 24
Finished Jul 15 06:33:27 PM PDT 24
Peak memory 215684 kb
Host smart-6496614d-54c9-42ca-ae19-994881df8d68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731645670 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.2731645670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2664563110
Short name T539
Test name
Test status
Simulation time 631349328 ps
CPU time 4.45 seconds
Started Jul 15 06:33:23 PM PDT 24
Finished Jul 15 06:33:28 PM PDT 24
Peak memory 215612 kb
Host smart-ccf03871-cbfe-43c0-88bc-99d1bffe72c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664563110 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2664563110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.2206047396
Short name T725
Test name
Test status
Simulation time 420277601422 ps
CPU time 1946.57 seconds
Started Jul 15 06:33:24 PM PDT 24
Finished Jul 15 07:05:52 PM PDT 24
Peak memory 390560 kb
Host smart-abcc31b6-1b6e-44fa-b2f2-8068e62edf66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2206047396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.2206047396 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.3691592210
Short name T522
Test name
Test status
Simulation time 180206675033 ps
CPU time 1788.4 seconds
Started Jul 15 06:33:25 PM PDT 24
Finished Jul 15 07:03:14 PM PDT 24
Peak memory 368904 kb
Host smart-c99133fb-1477-464c-92cf-16344b71feb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3691592210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3691592210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.1471201691
Short name T713
Test name
Test status
Simulation time 14277374460 ps
CPU time 1031.34 seconds
Started Jul 15 06:33:23 PM PDT 24
Finished Jul 15 06:50:35 PM PDT 24
Peak memory 333596 kb
Host smart-e972c2a5-7b26-4cbf-84a5-d84c617b259a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1471201691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.1471201691 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.3608312533
Short name T823
Test name
Test status
Simulation time 9643721791 ps
CPU time 777.48 seconds
Started Jul 15 06:33:23 PM PDT 24
Finished Jul 15 06:46:21 PM PDT 24
Peak memory 294104 kb
Host smart-0bd8483d-19f1-4ec6-a940-14bbf850f2d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3608312533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3608312533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.291778225
Short name T357
Test name
Test status
Simulation time 52850054886 ps
CPU time 3749.28 seconds
Started Jul 15 06:33:20 PM PDT 24
Finished Jul 15 07:35:51 PM PDT 24
Peak memory 648316 kb
Host smart-c0f6493f-adfc-4a98-b763-980ec5081c44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=291778225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.291778225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.90604712
Short name T918
Test name
Test status
Simulation time 245887551996 ps
CPU time 3925.91 seconds
Started Jul 15 06:33:24 PM PDT 24
Finished Jul 15 07:38:50 PM PDT 24
Peak memory 573164 kb
Host smart-831dc2ba-5d27-42d4-ba71-5db500e2e9b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=90604712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.90604712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.2460507252
Short name T883
Test name
Test status
Simulation time 22706980 ps
CPU time 0.84 seconds
Started Jul 15 06:33:34 PM PDT 24
Finished Jul 15 06:33:36 PM PDT 24
Peak memory 205280 kb
Host smart-7c4287b2-2f2e-45a5-a2db-c4209598972e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460507252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2460507252 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.4037087610
Short name T982
Test name
Test status
Simulation time 3707934269 ps
CPU time 42.6 seconds
Started Jul 15 06:33:36 PM PDT 24
Finished Jul 15 06:34:19 PM PDT 24
Peak memory 223868 kb
Host smart-dd2ee85d-12b1-4dae-9243-a34faeeffdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037087610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.4037087610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.1556158616
Short name T814
Test name
Test status
Simulation time 5403179663 ps
CPU time 32.63 seconds
Started Jul 15 06:33:34 PM PDT 24
Finished Jul 15 06:34:07 PM PDT 24
Peak memory 223720 kb
Host smart-83f80367-eb6c-4bdc-a61b-6cce74f3e9cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1556158616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1556158616 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.2208954352
Short name T1081
Test name
Test status
Simulation time 682133908 ps
CPU time 7.32 seconds
Started Jul 15 06:33:34 PM PDT 24
Finished Jul 15 06:33:42 PM PDT 24
Peak memory 219232 kb
Host smart-72769669-3742-46a8-a556-355f1e07e86c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2208954352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2208954352 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.22562126
Short name T664
Test name
Test status
Simulation time 35416864336 ps
CPU time 271.85 seconds
Started Jul 15 06:33:34 PM PDT 24
Finished Jul 15 06:38:07 PM PDT 24
Peak memory 242444 kb
Host smart-00baa18f-eaca-4785-bfc9-82c395595f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22562126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.22562126 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.2377554781
Short name T739
Test name
Test status
Simulation time 3081545222 ps
CPU time 242.18 seconds
Started Jul 15 06:33:33 PM PDT 24
Finished Jul 15 06:37:36 PM PDT 24
Peak memory 252968 kb
Host smart-29c24c30-d2aa-4f17-b1ad-a88b284d2b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377554781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2377554781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.383954717
Short name T1011
Test name
Test status
Simulation time 1724249530 ps
CPU time 9.61 seconds
Started Jul 15 06:33:34 PM PDT 24
Finished Jul 15 06:33:44 PM PDT 24
Peak memory 207352 kb
Host smart-ef9ecc60-b11b-4b88-a5ad-6a057a5c50da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383954717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.383954717 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.1545834200
Short name T796
Test name
Test status
Simulation time 41037271 ps
CPU time 1.33 seconds
Started Jul 15 06:33:33 PM PDT 24
Finished Jul 15 06:33:35 PM PDT 24
Peak memory 215512 kb
Host smart-78a3cc7c-293f-45e3-9e9c-7477072f3daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545834200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1545834200 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.203682726
Short name T558
Test name
Test status
Simulation time 188057844709 ps
CPU time 1164.3 seconds
Started Jul 15 06:33:28 PM PDT 24
Finished Jul 15 06:52:52 PM PDT 24
Peak memory 326816 kb
Host smart-0839469b-b1d4-48e4-b5b5-fbabc3893b8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203682726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.203682726 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.138077364
Short name T488
Test name
Test status
Simulation time 21707723019 ps
CPU time 427.37 seconds
Started Jul 15 06:33:27 PM PDT 24
Finished Jul 15 06:40:35 PM PDT 24
Peak memory 249140 kb
Host smart-b4accc6e-9cdb-4edb-8bd0-6b63114b6f82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138077364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.138077364 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.1127926130
Short name T746
Test name
Test status
Simulation time 11703012264 ps
CPU time 49.05 seconds
Started Jul 15 06:33:28 PM PDT 24
Finished Jul 15 06:34:17 PM PDT 24
Peak memory 223764 kb
Host smart-caf9e75f-3705-41ec-972a-de3c84132430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127926130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1127926130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.3667369144
Short name T980
Test name
Test status
Simulation time 56825603658 ps
CPU time 666.69 seconds
Started Jul 15 06:33:36 PM PDT 24
Finished Jul 15 06:44:43 PM PDT 24
Peak memory 338808 kb
Host smart-39ec0bd2-4192-4f70-9148-22a657b125dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3667369144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3667369144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.3047557636
Short name T184
Test name
Test status
Simulation time 665420333 ps
CPU time 4.5 seconds
Started Jul 15 06:33:26 PM PDT 24
Finished Jul 15 06:33:31 PM PDT 24
Peak memory 215632 kb
Host smart-02026685-398c-46f5-8d2e-1514eabe78ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047557636 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.3047557636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.712602248
Short name T979
Test name
Test status
Simulation time 1991920120 ps
CPU time 4.78 seconds
Started Jul 15 06:33:32 PM PDT 24
Finished Jul 15 06:33:37 PM PDT 24
Peak memory 215616 kb
Host smart-28313860-085f-4e95-9278-e05b50d4b65d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712602248 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.kmac_test_vectors_kmac_xof.712602248 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.2438158284
Short name T722
Test name
Test status
Simulation time 335793238968 ps
CPU time 1882.2 seconds
Started Jul 15 06:33:28 PM PDT 24
Finished Jul 15 07:04:51 PM PDT 24
Peak memory 390892 kb
Host smart-647672b9-9399-4725-904b-d77580a68f26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2438158284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.2438158284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.3801216138
Short name T723
Test name
Test status
Simulation time 416149037595 ps
CPU time 1897.37 seconds
Started Jul 15 06:33:29 PM PDT 24
Finished Jul 15 07:05:07 PM PDT 24
Peak memory 374436 kb
Host smart-79c947ab-d2c2-4663-ad27-7fa4ed13aaa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3801216138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3801216138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.1553015181
Short name T707
Test name
Test status
Simulation time 13774267424 ps
CPU time 1109.87 seconds
Started Jul 15 06:33:28 PM PDT 24
Finished Jul 15 06:51:59 PM PDT 24
Peak memory 329520 kb
Host smart-d56eade7-d2c1-40dd-9f7e-581923bd217b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1553015181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.1553015181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.3980702902
Short name T303
Test name
Test status
Simulation time 207222402793 ps
CPU time 984.94 seconds
Started Jul 15 06:33:29 PM PDT 24
Finished Jul 15 06:49:55 PM PDT 24
Peak memory 297888 kb
Host smart-0e4a0247-0a81-4b0e-b97d-bb36e7446557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3980702902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.3980702902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.588826447
Short name T572
Test name
Test status
Simulation time 352263230220 ps
CPU time 4649.93 seconds
Started Jul 15 06:33:33 PM PDT 24
Finished Jul 15 07:51:04 PM PDT 24
Peak memory 655164 kb
Host smart-0d5b4280-87bb-4401-94a2-6a9b5d71e72f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=588826447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.588826447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.805353318
Short name T897
Test name
Test status
Simulation time 221754494782 ps
CPU time 4269.58 seconds
Started Jul 15 06:33:34 PM PDT 24
Finished Jul 15 07:44:45 PM PDT 24
Peak memory 571632 kb
Host smart-43c53726-9d4c-469f-a571-23ae5afe38ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=805353318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.805353318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.1770828935
Short name T509
Test name
Test status
Simulation time 41754402 ps
CPU time 0.76 seconds
Started Jul 15 06:33:48 PM PDT 24
Finished Jul 15 06:33:49 PM PDT 24
Peak memory 205292 kb
Host smart-bf6842e3-3b22-457c-bda1-4bce11b0d87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770828935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1770828935 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_burst_write.2519753926
Short name T139
Test name
Test status
Simulation time 4943914382 ps
CPU time 405.42 seconds
Started Jul 15 06:33:35 PM PDT 24
Finished Jul 15 06:40:21 PM PDT 24
Peak memory 229140 kb
Host smart-1645a15e-c15e-4b35-8dc1-362106cb9077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519753926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2519753926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2362458847
Short name T425
Test name
Test status
Simulation time 1897245169 ps
CPU time 11.91 seconds
Started Jul 15 06:33:47 PM PDT 24
Finished Jul 15 06:33:59 PM PDT 24
Peak memory 215524 kb
Host smart-72ff055b-b1f8-4eb7-8cfc-4398a42a5d44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2362458847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2362458847 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.3796458973
Short name T414
Test name
Test status
Simulation time 6984572757 ps
CPU time 25.97 seconds
Started Jul 15 06:33:47 PM PDT 24
Finished Jul 15 06:34:14 PM PDT 24
Peak memory 217832 kb
Host smart-f7e34f56-32dc-49f4-a6d5-0c66d0a04cfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3796458973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3796458973 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_error.118138607
Short name T944
Test name
Test status
Simulation time 59026175067 ps
CPU time 229.98 seconds
Started Jul 15 06:33:48 PM PDT 24
Finished Jul 15 06:37:38 PM PDT 24
Peak memory 248588 kb
Host smart-abcd35ae-5670-4c5f-bfcc-6c1d03074894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118138607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.118138607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.188183295
Short name T768
Test name
Test status
Simulation time 1206337591 ps
CPU time 6.06 seconds
Started Jul 15 06:33:46 PM PDT 24
Finished Jul 15 06:33:52 PM PDT 24
Peak memory 207268 kb
Host smart-dd54b7cb-ba82-427d-af14-be1b21ae5cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188183295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.188183295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.1255967406
Short name T614
Test name
Test status
Simulation time 54823204 ps
CPU time 1.16 seconds
Started Jul 15 06:33:46 PM PDT 24
Finished Jul 15 06:33:48 PM PDT 24
Peak memory 215536 kb
Host smart-4efd2d7d-9728-4029-9b58-4bedfe5b70b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255967406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1255967406 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3035434360
Short name T227
Test name
Test status
Simulation time 367284938449 ps
CPU time 1134.45 seconds
Started Jul 15 06:33:34 PM PDT 24
Finished Jul 15 06:52:29 PM PDT 24
Peak memory 310252 kb
Host smart-7ce048cb-5646-40cc-8c30-10299134d24b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035434360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3035434360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.163084384
Short name T327
Test name
Test status
Simulation time 23906702877 ps
CPU time 339.55 seconds
Started Jul 15 06:33:33 PM PDT 24
Finished Jul 15 06:39:13 PM PDT 24
Peak memory 249376 kb
Host smart-1f7526b6-d141-48a8-b3ba-7de4859fe72f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163084384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.163084384 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.4172279397
Short name T828
Test name
Test status
Simulation time 1544260555 ps
CPU time 37.68 seconds
Started Jul 15 06:33:33 PM PDT 24
Finished Jul 15 06:34:12 PM PDT 24
Peak memory 219544 kb
Host smart-77682426-7b9d-44f2-bf84-fdfbb1fbd3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172279397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.4172279397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.2055125697
Short name T780
Test name
Test status
Simulation time 11204028901 ps
CPU time 441.15 seconds
Started Jul 15 06:33:46 PM PDT 24
Finished Jul 15 06:41:08 PM PDT 24
Peak memory 316888 kb
Host smart-5583aa9a-6ca0-4160-840e-26dc189bceab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2055125697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2055125697 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3116428990
Short name T927
Test name
Test status
Simulation time 180578783 ps
CPU time 4.63 seconds
Started Jul 15 06:33:41 PM PDT 24
Finished Jul 15 06:33:47 PM PDT 24
Peak memory 215520 kb
Host smart-ada2c1c5-5a3e-4e81-b23f-4594b36ecf26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116428990 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3116428990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2374604351
Short name T656
Test name
Test status
Simulation time 81155709 ps
CPU time 4.15 seconds
Started Jul 15 06:33:47 PM PDT 24
Finished Jul 15 06:33:52 PM PDT 24
Peak memory 215612 kb
Host smart-2e63860e-05e9-45d2-baa3-ab7bc7dc5f03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374604351 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2374604351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.1767014339
Short name T930
Test name
Test status
Simulation time 19394026733 ps
CPU time 1489.8 seconds
Started Jul 15 06:33:41 PM PDT 24
Finished Jul 15 06:58:32 PM PDT 24
Peak memory 388016 kb
Host smart-f6617e7c-754e-4799-a4f0-61f53c0664b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1767014339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1767014339 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1148764235
Short name T1009
Test name
Test status
Simulation time 183975996351 ps
CPU time 1806.16 seconds
Started Jul 15 06:33:39 PM PDT 24
Finished Jul 15 07:03:46 PM PDT 24
Peak memory 368620 kb
Host smart-8c745268-683f-4d15-b561-f16d81ca2e30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1148764235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1148764235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.2097765427
Short name T477
Test name
Test status
Simulation time 13468530884 ps
CPU time 1088.01 seconds
Started Jul 15 06:33:39 PM PDT 24
Finished Jul 15 06:51:48 PM PDT 24
Peak memory 330976 kb
Host smart-79c0a516-64c7-4aef-91fa-f5ae2ca0f551
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2097765427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2097765427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.824346430
Short name T648
Test name
Test status
Simulation time 53749873612 ps
CPU time 1030.75 seconds
Started Jul 15 06:33:42 PM PDT 24
Finished Jul 15 06:50:54 PM PDT 24
Peak memory 301572 kb
Host smart-65be128a-ed81-45c2-aca5-c9c1ab83a2e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=824346430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.824346430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.754759381
Short name T926
Test name
Test status
Simulation time 51371235368 ps
CPU time 4038.58 seconds
Started Jul 15 06:33:41 PM PDT 24
Finished Jul 15 07:41:00 PM PDT 24
Peak memory 637656 kb
Host smart-bade1036-e5b6-4044-859f-f6cb7953505f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=754759381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.754759381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.2764561759
Short name T606
Test name
Test status
Simulation time 194171231254 ps
CPU time 3835.01 seconds
Started Jul 15 06:33:40 PM PDT 24
Finished Jul 15 07:37:36 PM PDT 24
Peak memory 562456 kb
Host smart-19076f63-4bfd-4b05-bdad-367758207703
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2764561759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2764561759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.3140560219
Short name T220
Test name
Test status
Simulation time 43131092 ps
CPU time 0.78 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:33:53 PM PDT 24
Peak memory 205248 kb
Host smart-42027376-1a7b-4e22-a9e4-b8b304f1b424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140560219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3140560219 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.3673609291
Short name T877
Test name
Test status
Simulation time 4617368152 ps
CPU time 44.14 seconds
Started Jul 15 06:33:51 PM PDT 24
Finished Jul 15 06:34:35 PM PDT 24
Peak memory 223828 kb
Host smart-ce32ef54-d6cc-450b-910e-97f3d85dee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673609291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3673609291 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.3630151141
Short name T581
Test name
Test status
Simulation time 8211381416 ps
CPU time 174.67 seconds
Started Jul 15 06:33:47 PM PDT 24
Finished Jul 15 06:36:42 PM PDT 24
Peak memory 223972 kb
Host smart-677f72fa-adb8-413f-94e1-5f31217740ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630151141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3630151141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.3613125847
Short name T797
Test name
Test status
Simulation time 1077359156 ps
CPU time 13.85 seconds
Started Jul 15 06:33:51 PM PDT 24
Finished Jul 15 06:34:06 PM PDT 24
Peak memory 223672 kb
Host smart-0fd404ac-83ff-40dc-8f3f-84235c78a274
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3613125847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3613125847 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2383491097
Short name T79
Test name
Test status
Simulation time 517028138 ps
CPU time 10.36 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:34:03 PM PDT 24
Peak memory 222480 kb
Host smart-d86d2085-913c-47a8-b2d5-5fb7a02a795d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383491097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2383491097 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.777559761
Short name T672
Test name
Test status
Simulation time 5665468901 ps
CPU time 300.2 seconds
Started Jul 15 06:33:50 PM PDT 24
Finished Jul 15 06:38:51 PM PDT 24
Peak memory 244952 kb
Host smart-e2feb50b-4040-4fdf-9854-a4793f513cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777559761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.777559761 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.697211397
Short name T718
Test name
Test status
Simulation time 19915328426 ps
CPU time 325.7 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:39:19 PM PDT 24
Peak memory 251932 kb
Host smart-615f2263-b703-4554-b945-3a0c651cd23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697211397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.697211397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.596247046
Short name T401
Test name
Test status
Simulation time 2427666699 ps
CPU time 6.98 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:34:06 PM PDT 24
Peak memory 207440 kb
Host smart-efca5a93-c070-4bef-8518-6a115ff0d167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596247046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.596247046 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.3529510401
Short name T968
Test name
Test status
Simulation time 152395910 ps
CPU time 1.48 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:34:00 PM PDT 24
Peak memory 215524 kb
Host smart-32f8bc1d-3fa4-41fd-8087-67e2310898c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529510401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3529510401 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.2849472407
Short name T461
Test name
Test status
Simulation time 215283400545 ps
CPU time 2230.65 seconds
Started Jul 15 06:33:50 PM PDT 24
Finished Jul 15 07:11:01 PM PDT 24
Peak memory 448504 kb
Host smart-efdf5019-582e-47bf-b3b6-40fa784f1cb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849472407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.2849472407 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.4127005120
Short name T206
Test name
Test status
Simulation time 2474988770 ps
CPU time 64.01 seconds
Started Jul 15 06:33:48 PM PDT 24
Finished Jul 15 06:34:53 PM PDT 24
Peak memory 231984 kb
Host smart-cf37b7d0-7b48-4f47-b46f-3f8b5a678c63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127005120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.4127005120 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.2271658575
Short name T1077
Test name
Test status
Simulation time 1499452526 ps
CPU time 23.34 seconds
Started Jul 15 06:33:47 PM PDT 24
Finished Jul 15 06:34:11 PM PDT 24
Peak memory 215664 kb
Host smart-2171f930-fddc-46a0-8ece-c4c302583254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271658575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2271658575 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.1407463769
Short name T810
Test name
Test status
Simulation time 6035296175 ps
CPU time 80.19 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:35:13 PM PDT 24
Peak memory 240228 kb
Host smart-0baf15b7-9c6b-4e8d-b0e0-32d5c6100320
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1407463769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1407463769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.855116511
Short name T851
Test name
Test status
Simulation time 221816525 ps
CPU time 4.6 seconds
Started Jul 15 06:33:50 PM PDT 24
Finished Jul 15 06:33:56 PM PDT 24
Peak memory 215628 kb
Host smart-5d36745d-e702-4b96-821d-306b6c6062ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855116511 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.kmac_test_vectors_kmac.855116511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.2590523436
Short name T807
Test name
Test status
Simulation time 593073933 ps
CPU time 4.29 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:34:02 PM PDT 24
Peak memory 215596 kb
Host smart-8d8508a1-d965-45b8-97ff-a1e65d352279
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590523436 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.2590523436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.1557678819
Short name T540
Test name
Test status
Simulation time 69156751325 ps
CPU time 1769.91 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 07:03:27 PM PDT 24
Peak memory 397128 kb
Host smart-6d896637-3e0b-467d-ac6f-ef539c39bb03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1557678819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.1557678819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.439730786
Short name T813
Test name
Test status
Simulation time 721727604966 ps
CPU time 1668.91 seconds
Started Jul 15 06:33:51 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 374544 kb
Host smart-e7af37a0-58ed-463c-87da-4a84eec201b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=439730786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.439730786 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.1358521659
Short name T476
Test name
Test status
Simulation time 195765991491 ps
CPU time 1176.06 seconds
Started Jul 15 06:33:50 PM PDT 24
Finished Jul 15 06:53:27 PM PDT 24
Peak memory 336632 kb
Host smart-4281be96-751b-4264-8871-0dbbce0c1ab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1358521659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.1358521659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.1143998576
Short name T912
Test name
Test status
Simulation time 141059628979 ps
CPU time 961.51 seconds
Started Jul 15 06:33:47 PM PDT 24
Finished Jul 15 06:49:50 PM PDT 24
Peak memory 294060 kb
Host smart-bd28bcc0-1f10-4309-ba75-a65d4d62129c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1143998576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.1143998576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.154548789
Short name T705
Test name
Test status
Simulation time 209762156428 ps
CPU time 4027.51 seconds
Started Jul 15 06:33:46 PM PDT 24
Finished Jul 15 07:40:55 PM PDT 24
Peak memory 639500 kb
Host smart-7fc7246f-8479-48b9-9321-327e63fff232
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=154548789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.154548789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.3923355194
Short name T1073
Test name
Test status
Simulation time 387876226264 ps
CPU time 3955.91 seconds
Started Jul 15 06:33:51 PM PDT 24
Finished Jul 15 07:39:49 PM PDT 24
Peak memory 570224 kb
Host smart-b0b5b143-537e-4854-a5d0-d8f5d656b0a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3923355194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.3923355194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.3094885043
Short name T229
Test name
Test status
Simulation time 15275614 ps
CPU time 0.8 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:34:00 PM PDT 24
Peak memory 205324 kb
Host smart-1430ecd3-e95a-420c-8c95-a2646576728c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094885043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3094885043 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.4136806138
Short name T535
Test name
Test status
Simulation time 54466804055 ps
CPU time 319.34 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:39:12 PM PDT 24
Peak memory 249792 kb
Host smart-bd258370-9ca8-4334-b8c4-b0279eae174b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136806138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.4136806138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.1023708621
Short name T610
Test name
Test status
Simulation time 7696054674 ps
CPU time 108.88 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:35:42 PM PDT 24
Peak memory 221628 kb
Host smart-2a4f0e27-8428-45c8-8cd0-81f4b85973fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023708621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1023708621 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.693125718
Short name T826
Test name
Test status
Simulation time 756693229 ps
CPU time 24.68 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:34:24 PM PDT 24
Peak memory 219524 kb
Host smart-21c5d4d7-8979-4020-a9da-4225d0ac5b56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=693125718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.693125718 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.436480231
Short name T751
Test name
Test status
Simulation time 7721383554 ps
CPU time 39.48 seconds
Started Jul 15 06:33:58 PM PDT 24
Finished Jul 15 06:34:39 PM PDT 24
Peak memory 229188 kb
Host smart-d9c05d9c-706d-474f-8a1e-3d6b052eb7b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=436480231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.436480231 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.971686954
Short name T745
Test name
Test status
Simulation time 5639604666 ps
CPU time 80.07 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:35:18 PM PDT 24
Peak memory 227640 kb
Host smart-aa0044b3-490f-48e0-81b5-59ec61f9a4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971686954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.971686954 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.2436980942
Short name T621
Test name
Test status
Simulation time 726079052 ps
CPU time 7.85 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:34:07 PM PDT 24
Peak memory 218396 kb
Host smart-1eeaf04b-049d-4302-9f54-680ed5b0185c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436980942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2436980942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.3695983816
Short name T22
Test name
Test status
Simulation time 530248798 ps
CPU time 3.47 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:34:02 PM PDT 24
Peak memory 215472 kb
Host smart-857b8996-f39a-4b71-b110-c26c8dfef8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695983816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3695983816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.2112004305
Short name T634
Test name
Test status
Simulation time 134761874 ps
CPU time 1.25 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:33:59 PM PDT 24
Peak memory 215664 kb
Host smart-85160cbf-632c-44e7-8edc-f75c4cb1064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112004305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2112004305 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.2384206537
Short name T188
Test name
Test status
Simulation time 110913334938 ps
CPU time 2277.86 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 07:11:51 PM PDT 24
Peak memory 430848 kb
Host smart-1bcbd0a2-96f4-4147-8439-801602aac073
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384206537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.2384206537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.3326287467
Short name T615
Test name
Test status
Simulation time 2198334254 ps
CPU time 87.57 seconds
Started Jul 15 06:33:51 PM PDT 24
Finished Jul 15 06:35:20 PM PDT 24
Peak memory 226184 kb
Host smart-3244c88c-8540-4c5c-9460-f3d0497cc986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326287467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3326287467 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.230761982
Short name T217
Test name
Test status
Simulation time 8177448205 ps
CPU time 14.27 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:34:07 PM PDT 24
Peak memory 215916 kb
Host smart-a6dddbdc-42c8-4f4e-9435-72653cb43551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230761982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.230761982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.488883851
Short name T1035
Test name
Test status
Simulation time 26217764668 ps
CPU time 234.52 seconds
Started Jul 15 06:33:58 PM PDT 24
Finished Jul 15 06:37:54 PM PDT 24
Peak memory 255368 kb
Host smart-ea6192a8-c216-4ea8-8ddc-fe0bfd104697
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=488883851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.488883851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1961613247
Short name T738
Test name
Test status
Simulation time 62239372 ps
CPU time 3.49 seconds
Started Jul 15 06:33:51 PM PDT 24
Finished Jul 15 06:33:55 PM PDT 24
Peak memory 215592 kb
Host smart-39f4122e-7ab4-4d67-bd29-8d43fcfc12e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961613247 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1961613247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3108075864
Short name T201
Test name
Test status
Simulation time 366676091 ps
CPU time 4.9 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:34:04 PM PDT 24
Peak memory 215612 kb
Host smart-e6ecf642-bb61-41d2-bc0f-3aeb5359ba83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108075864 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3108075864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.3733022867
Short name T490
Test name
Test status
Simulation time 18322383505 ps
CPU time 1491.2 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:58:48 PM PDT 24
Peak memory 374704 kb
Host smart-9da20844-3e38-4be1-a4de-096b7c536c9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3733022867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.3733022867 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.91957652
Short name T442
Test name
Test status
Simulation time 64017280759 ps
CPU time 1410.73 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:57:24 PM PDT 24
Peak memory 377832 kb
Host smart-4e5a2501-4796-455b-997b-8c3d5c829293
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=91957652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.91957652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.4146159094
Short name T922
Test name
Test status
Simulation time 292932581578 ps
CPU time 1462.08 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:58:20 PM PDT 24
Peak memory 334568 kb
Host smart-b95823e2-2909-4878-a33d-a8e24de965e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4146159094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.4146159094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.648168049
Short name T351
Test name
Test status
Simulation time 48554714628 ps
CPU time 1039.74 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 06:51:13 PM PDT 24
Peak memory 293796 kb
Host smart-fb07b23b-a031-4a2c-b904-0c5f391bb26e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=648168049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.648168049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.1848486261
Short name T633
Test name
Test status
Simulation time 316841000479 ps
CPU time 3944.21 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 07:39:43 PM PDT 24
Peak memory 648264 kb
Host smart-76db9e16-76eb-44b9-a043-f59cf8a7ae85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1848486261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1848486261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.2905596201
Short name T620
Test name
Test status
Simulation time 2423573585401 ps
CPU time 4686.04 seconds
Started Jul 15 06:33:52 PM PDT 24
Finished Jul 15 07:52:00 PM PDT 24
Peak memory 561480 kb
Host smart-342bb020-6ede-4d33-aa0f-88e5cdc9c218
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2905596201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2905596201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.3944863971
Short name T433
Test name
Test status
Simulation time 274136188 ps
CPU time 0.91 seconds
Started Jul 15 06:34:04 PM PDT 24
Finished Jul 15 06:34:06 PM PDT 24
Peak memory 205308 kb
Host smart-14857a96-798f-429b-b017-1789500abb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944863971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3944863971 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.2744500034
Short name T435
Test name
Test status
Simulation time 26099463268 ps
CPU time 238.84 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:37:58 PM PDT 24
Peak memory 242048 kb
Host smart-9d6f76b2-3404-4540-85b7-e5432749b516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744500034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2744500034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.3693115896
Short name T848
Test name
Test status
Simulation time 10880495396 ps
CPU time 267.93 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:38:27 PM PDT 24
Peak memory 225408 kb
Host smart-0f22ce16-55a1-44e9-b5a2-ba697c08d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693115896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3693115896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.3615728963
Short name T360
Test name
Test status
Simulation time 361011619 ps
CPU time 17.94 seconds
Started Jul 15 06:34:02 PM PDT 24
Finished Jul 15 06:34:21 PM PDT 24
Peak memory 223668 kb
Host smart-ec64ae64-0121-4ad3-91e0-cc46accc8afe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3615728963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3615728963 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.2888922477
Short name T286
Test name
Test status
Simulation time 1593409178 ps
CPU time 21.04 seconds
Started Jul 15 06:34:02 PM PDT 24
Finished Jul 15 06:34:23 PM PDT 24
Peak memory 216932 kb
Host smart-fb57561c-f4d4-4b53-8e89-685f188d42a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2888922477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2888922477 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.3045353529
Short name T381
Test name
Test status
Simulation time 8421310742 ps
CPU time 80.21 seconds
Started Jul 15 06:34:03 PM PDT 24
Finished Jul 15 06:35:24 PM PDT 24
Peak memory 226104 kb
Host smart-13585521-0755-4dca-a16d-083ecfe256e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045353529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3045353529 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.3868884950
Short name T78
Test name
Test status
Simulation time 4768278702 ps
CPU time 320 seconds
Started Jul 15 06:34:04 PM PDT 24
Finished Jul 15 06:39:25 PM PDT 24
Peak memory 252508 kb
Host smart-c085cc71-7774-48d7-85f6-1d0ace07a11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868884950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3868884950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.1488030560
Short name T762
Test name
Test status
Simulation time 1671850315 ps
CPU time 2.84 seconds
Started Jul 15 06:34:02 PM PDT 24
Finished Jul 15 06:34:06 PM PDT 24
Peak memory 207232 kb
Host smart-56d24f75-4025-4796-a669-b854780e8498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488030560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1488030560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.2094308866
Short name T781
Test name
Test status
Simulation time 962241956 ps
CPU time 65.08 seconds
Started Jul 15 06:34:03 PM PDT 24
Finished Jul 15 06:35:08 PM PDT 24
Peak memory 233616 kb
Host smart-1cd0a737-6d10-43a0-98c0-35b052622ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094308866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2094308866 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.550190002
Short name T534
Test name
Test status
Simulation time 108835089401 ps
CPU time 153.77 seconds
Started Jul 15 06:33:58 PM PDT 24
Finished Jul 15 06:36:34 PM PDT 24
Peak memory 229028 kb
Host smart-2a0cea77-68a2-479b-8a46-959fe48ad5f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550190002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_an
d_output.550190002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.2291810296
Short name T550
Test name
Test status
Simulation time 33671631040 ps
CPU time 150.26 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:36:28 PM PDT 24
Peak memory 233604 kb
Host smart-b103c6c7-cd7c-4fc3-9421-3a46ac04f62d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291810296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2291810296 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.2983505518
Short name T602
Test name
Test status
Simulation time 7763380387 ps
CPU time 42.89 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:34:40 PM PDT 24
Peak memory 218696 kb
Host smart-12e3a4e0-9508-4aaa-85a6-fd2c1368f7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983505518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2983505518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.4112190367
Short name T88
Test name
Test status
Simulation time 10664832922 ps
CPU time 697.8 seconds
Started Jul 15 06:34:01 PM PDT 24
Finished Jul 15 06:45:40 PM PDT 24
Peak memory 338532 kb
Host smart-2795459f-85a5-48ff-be39-5ec013474514
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4112190367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.4112190367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.4062782915
Short name T236
Test name
Test status
Simulation time 63046394 ps
CPU time 3.75 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:34:03 PM PDT 24
Peak memory 215584 kb
Host smart-dcfe2186-c626-4dbe-a8bd-cf3c4e81e85c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062782915 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.4062782915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.3389434670
Short name T760
Test name
Test status
Simulation time 260822183 ps
CPU time 5.39 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 06:34:04 PM PDT 24
Peak memory 215680 kb
Host smart-5d641e8f-4e12-42da-8136-427fc0999b7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389434670 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.3389434670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.2010850766
Short name T385
Test name
Test status
Simulation time 140029300800 ps
CPU time 1905.5 seconds
Started Jul 15 06:33:59 PM PDT 24
Finished Jul 15 07:05:46 PM PDT 24
Peak memory 396596 kb
Host smart-1226ce32-d12d-4720-aebe-6cff819b1dd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2010850766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.2010850766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.124964656
Short name T221
Test name
Test status
Simulation time 18430975691 ps
CPU time 1489.55 seconds
Started Jul 15 06:33:58 PM PDT 24
Finished Jul 15 06:58:49 PM PDT 24
Peak memory 387872 kb
Host smart-6d8728b1-dfb2-462e-8404-8d2bc4d797f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=124964656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.124964656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.39812173
Short name T935
Test name
Test status
Simulation time 236345223906 ps
CPU time 1518.85 seconds
Started Jul 15 06:33:58 PM PDT 24
Finished Jul 15 06:59:19 PM PDT 24
Peak memory 328796 kb
Host smart-15952631-c24d-4011-a070-2beb72cb9a6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=39812173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.39812173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.2133764070
Short name T717
Test name
Test status
Simulation time 65921394309 ps
CPU time 862.65 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 06:48:21 PM PDT 24
Peak memory 292560 kb
Host smart-b0f297be-0393-4ce9-9563-4769bc3b6892
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2133764070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.2133764070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.4173381753
Short name T1020
Test name
Test status
Simulation time 52846340745 ps
CPU time 4082.17 seconds
Started Jul 15 06:33:57 PM PDT 24
Finished Jul 15 07:42:02 PM PDT 24
Peak memory 647716 kb
Host smart-6624b8db-5471-4046-98ec-971557814f40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4173381753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.4173381753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.170333852
Short name T431
Test name
Test status
Simulation time 190571031727 ps
CPU time 3726.69 seconds
Started Jul 15 06:33:56 PM PDT 24
Finished Jul 15 07:36:05 PM PDT 24
Peak memory 557868 kb
Host smart-ce1e8f10-5a05-4667-80e6-b1085d866779
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=170333852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.170333852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.1933157421
Short name T234
Test name
Test status
Simulation time 29235612 ps
CPU time 0.78 seconds
Started Jul 15 06:34:12 PM PDT 24
Finished Jul 15 06:34:13 PM PDT 24
Peak memory 205312 kb
Host smart-3599144c-9716-49b8-a72a-9e7fc81cace5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933157421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1933157421 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.4207471532
Short name T417
Test name
Test status
Simulation time 12020843396 ps
CPU time 262.71 seconds
Started Jul 15 06:34:12 PM PDT 24
Finished Jul 15 06:38:35 PM PDT 24
Peak memory 245220 kb
Host smart-49985da5-4e8c-4bd3-9f72-c529ce907b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207471532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.4207471532 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.3419771165
Short name T1039
Test name
Test status
Simulation time 32784699178 ps
CPU time 283.22 seconds
Started Jul 15 06:34:05 PM PDT 24
Finished Jul 15 06:38:49 PM PDT 24
Peak memory 227240 kb
Host smart-f36461c7-23f9-45ef-9ef5-d60592d913ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419771165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3419771165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.3514960410
Short name T398
Test name
Test status
Simulation time 364403134 ps
CPU time 22.87 seconds
Started Jul 15 06:34:13 PM PDT 24
Finished Jul 15 06:34:37 PM PDT 24
Peak memory 223820 kb
Host smart-f3c04af9-6d0d-451a-8a90-3e4e2f48d6f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3514960410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3514960410 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.2670024315
Short name T31
Test name
Test status
Simulation time 706554191 ps
CPU time 16.82 seconds
Started Jul 15 06:34:12 PM PDT 24
Finished Jul 15 06:34:30 PM PDT 24
Peak memory 218208 kb
Host smart-210a86b9-8eae-4968-af97-436d6467a799
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2670024315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2670024315 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.889650720
Short name T625
Test name
Test status
Simulation time 48442026897 ps
CPU time 224.88 seconds
Started Jul 15 06:34:13 PM PDT 24
Finished Jul 15 06:37:59 PM PDT 24
Peak memory 239292 kb
Host smart-bcb12ec2-16dc-44a2-897b-483b6ad354f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889650720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.889650720 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.731339949
Short name T791
Test name
Test status
Simulation time 26462324978 ps
CPU time 370.46 seconds
Started Jul 15 06:34:13 PM PDT 24
Finished Jul 15 06:40:24 PM PDT 24
Peak memory 256632 kb
Host smart-04239f59-bdc6-45d4-a89c-fa5848103c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731339949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.731339949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.3385437682
Short name T69
Test name
Test status
Simulation time 2538098433 ps
CPU time 3.53 seconds
Started Jul 15 06:34:13 PM PDT 24
Finished Jul 15 06:34:18 PM PDT 24
Peak memory 207332 kb
Host smart-39612907-35dc-44c3-9cc9-cef03113f167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385437682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3385437682 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.354651242
Short name T643
Test name
Test status
Simulation time 796883554 ps
CPU time 14.59 seconds
Started Jul 15 06:34:14 PM PDT 24
Finished Jul 15 06:34:29 PM PDT 24
Peak memory 223804 kb
Host smart-1ea30522-e38c-44f8-849c-79b278682bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354651242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.354651242 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.3796391873
Short name T512
Test name
Test status
Simulation time 460886688338 ps
CPU time 2523.51 seconds
Started Jul 15 06:34:03 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 441056 kb
Host smart-46056b91-528a-4745-b4ed-255f2e07f598
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796391873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.3796391873 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.3851658367
Short name T871
Test name
Test status
Simulation time 9401211029 ps
CPU time 239.05 seconds
Started Jul 15 06:34:04 PM PDT 24
Finished Jul 15 06:38:03 PM PDT 24
Peak memory 240328 kb
Host smart-9e2260b4-c546-47dd-8fba-e99e53af6558
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851658367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3851658367 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.3846497715
Short name T187
Test name
Test status
Simulation time 228789309 ps
CPU time 5.19 seconds
Started Jul 15 06:34:04 PM PDT 24
Finished Jul 15 06:34:10 PM PDT 24
Peak memory 216596 kb
Host smart-197e6786-f067-49d7-9cfa-1f6d001710b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846497715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3846497715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.463248635
Short name T702
Test name
Test status
Simulation time 182828006158 ps
CPU time 1125.08 seconds
Started Jul 15 06:34:14 PM PDT 24
Finished Jul 15 06:53:01 PM PDT 24
Peak memory 346984 kb
Host smart-0d7d1542-e3f4-41a7-8169-976d8616a73a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=463248635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.463248635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.842901841
Short name T959
Test name
Test status
Simulation time 727009295 ps
CPU time 4.78 seconds
Started Jul 15 06:34:13 PM PDT 24
Finished Jul 15 06:34:19 PM PDT 24
Peak memory 215636 kb
Host smart-73a7cce5-ee51-4138-a99f-7cbf12261310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842901841 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.kmac_test_vectors_kmac.842901841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.1877613671
Short name T304
Test name
Test status
Simulation time 215385043 ps
CPU time 4.44 seconds
Started Jul 15 06:34:14 PM PDT 24
Finished Jul 15 06:34:19 PM PDT 24
Peak memory 215604 kb
Host smart-0ea1cdf7-e833-470f-b941-1da519529ee3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877613671 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.1877613671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.303905522
Short name T653
Test name
Test status
Simulation time 336602520593 ps
CPU time 1799.48 seconds
Started Jul 15 06:34:02 PM PDT 24
Finished Jul 15 07:04:02 PM PDT 24
Peak memory 391116 kb
Host smart-5133f122-8035-462d-9eef-bf4b9f2a366e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=303905522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.303905522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.2969900484
Short name T389
Test name
Test status
Simulation time 94672687618 ps
CPU time 1941.94 seconds
Started Jul 15 06:34:08 PM PDT 24
Finished Jul 15 07:06:31 PM PDT 24
Peak memory 371968 kb
Host smart-3b072387-6a89-444c-9182-ce6d4fe7d1c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2969900484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.2969900484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.2746918866
Short name T299
Test name
Test status
Simulation time 190897190254 ps
CPU time 1269.77 seconds
Started Jul 15 06:34:06 PM PDT 24
Finished Jul 15 06:55:17 PM PDT 24
Peak memory 328092 kb
Host smart-d15d1a91-e3d4-42c4-a13f-b0961109e34c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2746918866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.2746918866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.3137159872
Short name T375
Test name
Test status
Simulation time 129116998088 ps
CPU time 927.36 seconds
Started Jul 15 06:34:07 PM PDT 24
Finished Jul 15 06:49:35 PM PDT 24
Peak memory 293228 kb
Host smart-ffd374e6-4741-4e59-8b4c-915f6aa6d912
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3137159872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.3137159872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.3972396278
Short name T729
Test name
Test status
Simulation time 899721601660 ps
CPU time 4815.97 seconds
Started Jul 15 06:34:07 PM PDT 24
Finished Jul 15 07:54:24 PM PDT 24
Peak memory 644472 kb
Host smart-444caca3-d1ba-4f73-96b2-80b4104c7530
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3972396278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3972396278 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.3735257535
Short name T202
Test name
Test status
Simulation time 287505719739 ps
CPU time 4097.56 seconds
Started Jul 15 06:34:12 PM PDT 24
Finished Jul 15 07:42:31 PM PDT 24
Peak memory 568856 kb
Host smart-2d1cc892-c57f-433d-85ae-c8a373e4db4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3735257535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3735257535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.1922156281
Short name T382
Test name
Test status
Simulation time 26674265 ps
CPU time 0.8 seconds
Started Jul 15 06:34:23 PM PDT 24
Finished Jul 15 06:34:24 PM PDT 24
Peak memory 205260 kb
Host smart-09444e7e-b214-4ec2-81dd-bcbaaae45620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922156281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1922156281 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.2020029715
Short name T748
Test name
Test status
Simulation time 21341523582 ps
CPU time 206.25 seconds
Started Jul 15 06:34:26 PM PDT 24
Finished Jul 15 06:37:53 PM PDT 24
Peak memory 236272 kb
Host smart-73b4f842-1f7a-4491-99d6-f13fd2eaa057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020029715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2020029715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.1326884818
Short name T865
Test name
Test status
Simulation time 25707301398 ps
CPU time 828.18 seconds
Started Jul 15 06:34:20 PM PDT 24
Finished Jul 15 06:48:09 PM PDT 24
Peak memory 232800 kb
Host smart-66cb2ab7-c3a0-4081-9a5a-c5fdd853d79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326884818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1326884818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.251407994
Short name T276
Test name
Test status
Simulation time 1033549365 ps
CPU time 6.31 seconds
Started Jul 15 06:34:24 PM PDT 24
Finished Jul 15 06:34:31 PM PDT 24
Peak memory 216548 kb
Host smart-5394b6a9-63fe-45dd-8776-ffe55d2c0406
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=251407994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.251407994 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.1828797884
Short name T399
Test name
Test status
Simulation time 2279279218 ps
CPU time 45.09 seconds
Started Jul 15 06:34:25 PM PDT 24
Finished Jul 15 06:35:10 PM PDT 24
Peak memory 220876 kb
Host smart-23cd15d3-17f1-42d0-83da-7795bd1fa9cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828797884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1828797884 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.2326822490
Short name T243
Test name
Test status
Simulation time 3866402573 ps
CPU time 16.16 seconds
Started Jul 15 06:34:25 PM PDT 24
Finished Jul 15 06:34:42 PM PDT 24
Peak memory 223812 kb
Host smart-381f9328-1a53-4a3a-ac92-807c1e56c2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326822490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2326822490 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.4076887582
Short name T955
Test name
Test status
Simulation time 6060652204 ps
CPU time 111.54 seconds
Started Jul 15 06:34:23 PM PDT 24
Finished Jul 15 06:36:15 PM PDT 24
Peak memory 240192 kb
Host smart-75903fb0-b9b3-4bc7-84af-2e34ad3a94ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076887582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.4076887582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.1293522219
Short name T370
Test name
Test status
Simulation time 2187833102 ps
CPU time 3.82 seconds
Started Jul 15 06:34:25 PM PDT 24
Finished Jul 15 06:34:29 PM PDT 24
Peak memory 207264 kb
Host smart-39e5d53c-c9bc-4c40-b5a3-17b9ac29f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293522219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1293522219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1510513834
Short name T403
Test name
Test status
Simulation time 45751018 ps
CPU time 1.46 seconds
Started Jul 15 06:34:24 PM PDT 24
Finished Jul 15 06:34:26 PM PDT 24
Peak memory 216876 kb
Host smart-a21bc943-2d35-4580-a454-8f093ad31d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510513834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1510513834 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.761698458
Short name T232
Test name
Test status
Simulation time 14296003553 ps
CPU time 316.25 seconds
Started Jul 15 06:34:12 PM PDT 24
Finished Jul 15 06:39:29 PM PDT 24
Peak memory 244332 kb
Host smart-3b838031-15c3-4f26-bcbf-e8b7542a11ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761698458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_an
d_output.761698458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.1209320458
Short name T784
Test name
Test status
Simulation time 8379890116 ps
CPU time 152.1 seconds
Started Jul 15 06:34:13 PM PDT 24
Finished Jul 15 06:36:45 PM PDT 24
Peak memory 233548 kb
Host smart-1649894a-efff-4330-9468-857cb8849d8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209320458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1209320458 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.3199330746
Short name T719
Test name
Test status
Simulation time 859581750 ps
CPU time 10.9 seconds
Started Jul 15 06:34:14 PM PDT 24
Finished Jul 15 06:34:25 PM PDT 24
Peak memory 221600 kb
Host smart-e99e3f73-840d-49f5-9cc3-b0449ee40f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199330746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3199330746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.62523219
Short name T42
Test name
Test status
Simulation time 27143179338 ps
CPU time 534.38 seconds
Started Jul 15 06:34:24 PM PDT 24
Finished Jul 15 06:43:19 PM PDT 24
Peak memory 271400 kb
Host smart-3e3c582e-4efe-4e90-87ac-b84484f3bd08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=62523219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.62523219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.3246241078
Short name T521
Test name
Test status
Simulation time 2171351371 ps
CPU time 5.58 seconds
Started Jul 15 06:34:20 PM PDT 24
Finished Jul 15 06:34:26 PM PDT 24
Peak memory 215656 kb
Host smart-d559dcf5-68b5-4617-8794-46052b2fd260
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246241078 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.3246241078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.338686640
Short name T1041
Test name
Test status
Simulation time 107466414 ps
CPU time 3.81 seconds
Started Jul 15 06:34:20 PM PDT 24
Finished Jul 15 06:34:25 PM PDT 24
Peak memory 215604 kb
Host smart-ef7a81c4-28ef-40ce-b98e-c5e73bed0a03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338686640 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.kmac_test_vectors_kmac_xof.338686640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.1932785869
Short name T334
Test name
Test status
Simulation time 19768237869 ps
CPU time 1539.84 seconds
Started Jul 15 06:34:20 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 386900 kb
Host smart-d8d7e6c7-f5da-42ed-b249-db0a5531a1b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1932785869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.1932785869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.2454533173
Short name T786
Test name
Test status
Simulation time 215167967938 ps
CPU time 1676.24 seconds
Started Jul 15 06:34:19 PM PDT 24
Finished Jul 15 07:02:16 PM PDT 24
Peak memory 374636 kb
Host smart-c7580cfc-fccc-46ce-8341-6ac5908dd1a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2454533173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.2454533173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.1761359685
Short name T770
Test name
Test status
Simulation time 49067291648 ps
CPU time 1317.87 seconds
Started Jul 15 06:34:21 PM PDT 24
Finished Jul 15 06:56:19 PM PDT 24
Peak memory 335772 kb
Host smart-607389b2-fa0d-4bd5-a2c6-880c2215d8d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1761359685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.1761359685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.1735779253
Short name T617
Test name
Test status
Simulation time 34218135387 ps
CPU time 914.66 seconds
Started Jul 15 06:34:19 PM PDT 24
Finished Jul 15 06:49:34 PM PDT 24
Peak memory 296192 kb
Host smart-395fcc01-e486-4402-921b-c57360b4bc06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1735779253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1735779253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.2472321555
Short name T185
Test name
Test status
Simulation time 272790489934 ps
CPU time 3909.12 seconds
Started Jul 15 06:34:20 PM PDT 24
Finished Jul 15 07:39:30 PM PDT 24
Peak memory 669532 kb
Host smart-efe718fa-ed56-4048-8e68-f868171be1aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2472321555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.2472321555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.4077072079
Short name T515
Test name
Test status
Simulation time 223137489117 ps
CPU time 4444.66 seconds
Started Jul 15 06:34:22 PM PDT 24
Finished Jul 15 07:48:27 PM PDT 24
Peak memory 567932 kb
Host smart-d755668b-22a6-4b74-8b25-88d55e9d5379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4077072079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.4077072079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2436189044
Short name T821
Test name
Test status
Simulation time 18030598 ps
CPU time 0.82 seconds
Started Jul 15 06:34:35 PM PDT 24
Finished Jul 15 06:34:36 PM PDT 24
Peak memory 205196 kb
Host smart-3a6c5688-2b69-4c4d-a055-4c44818d5bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436189044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2436189044 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3117886591
Short name T778
Test name
Test status
Simulation time 8292932800 ps
CPU time 225.91 seconds
Started Jul 15 06:34:34 PM PDT 24
Finished Jul 15 06:38:20 PM PDT 24
Peak memory 241480 kb
Host smart-d01df401-4740-43c6-a48b-32381821e4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117886591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3117886591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.195306580
Short name T720
Test name
Test status
Simulation time 118634933396 ps
CPU time 649.97 seconds
Started Jul 15 06:34:29 PM PDT 24
Finished Jul 15 06:45:20 PM PDT 24
Peak memory 239544 kb
Host smart-837b19a9-1fa3-4514-8b0c-0a8f1cdd53e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195306580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.195306580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.1575036125
Short name T1046
Test name
Test status
Simulation time 515976135 ps
CPU time 12.69 seconds
Started Jul 15 06:34:35 PM PDT 24
Finished Jul 15 06:34:48 PM PDT 24
Peak memory 218736 kb
Host smart-7bd3d94c-69a8-4f06-af98-eade0ad9312d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1575036125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1575036125 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.3402884648
Short name T523
Test name
Test status
Simulation time 3000129457 ps
CPU time 31.53 seconds
Started Jul 15 06:34:35 PM PDT 24
Finished Jul 15 06:35:07 PM PDT 24
Peak memory 223716 kb
Host smart-15d694c6-2911-4a4a-a6ee-3b530e0c81e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3402884648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3402884648 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.3740066616
Short name T963
Test name
Test status
Simulation time 35594938194 ps
CPU time 154.24 seconds
Started Jul 15 06:34:36 PM PDT 24
Finished Jul 15 06:37:11 PM PDT 24
Peak memory 233964 kb
Host smart-e3395a08-641b-474c-80a3-f34ac9ba9a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740066616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3740066616 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.1773121077
Short name T887
Test name
Test status
Simulation time 8197227081 ps
CPU time 368.77 seconds
Started Jul 15 06:34:34 PM PDT 24
Finished Jul 15 06:40:43 PM PDT 24
Peak memory 264808 kb
Host smart-9b6f886a-05bd-40e7-b387-2796abdc66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773121077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1773121077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.2879597875
Short name T650
Test name
Test status
Simulation time 563033272 ps
CPU time 3.34 seconds
Started Jul 15 06:34:36 PM PDT 24
Finished Jul 15 06:34:39 PM PDT 24
Peak memory 207252 kb
Host smart-10ee0c12-e3c1-40f0-8264-370cc7727728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879597875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2879597875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.2759510421
Short name T447
Test name
Test status
Simulation time 517721683 ps
CPU time 4.11 seconds
Started Jul 15 06:34:36 PM PDT 24
Finished Jul 15 06:34:41 PM PDT 24
Peak memory 223836 kb
Host smart-50e51d3f-377f-46ab-85e0-e0bf371783ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759510421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2759510421 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.2689739284
Short name T298
Test name
Test status
Simulation time 38247019149 ps
CPU time 814.06 seconds
Started Jul 15 06:34:28 PM PDT 24
Finished Jul 15 06:48:03 PM PDT 24
Peak memory 292140 kb
Host smart-e850e3ab-797e-4b76-b6a4-f1a296dd1f40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689739284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.2689739284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2914019270
Short name T487
Test name
Test status
Simulation time 4491334168 ps
CPU time 359.8 seconds
Started Jul 15 06:34:29 PM PDT 24
Finished Jul 15 06:40:29 PM PDT 24
Peak memory 249252 kb
Host smart-33d1385f-4e17-4e5a-baaf-dc2e51b164a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914019270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2914019270 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.2916249073
Short name T811
Test name
Test status
Simulation time 1083868228 ps
CPU time 6.42 seconds
Started Jul 15 06:34:30 PM PDT 24
Finished Jul 15 06:34:37 PM PDT 24
Peak memory 218664 kb
Host smart-58b67ecf-9715-43e3-89c4-4d686d20d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916249073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2916249073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.927003629
Short name T693
Test name
Test status
Simulation time 65464442 ps
CPU time 3.69 seconds
Started Jul 15 06:34:36 PM PDT 24
Finished Jul 15 06:34:40 PM PDT 24
Peak memory 215844 kb
Host smart-6408be07-a35e-4761-93c5-64e9545e9806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927003629 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_test_vectors_kmac.927003629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.2670640124
Short name T257
Test name
Test status
Simulation time 553024505 ps
CPU time 5.25 seconds
Started Jul 15 06:34:35 PM PDT 24
Finished Jul 15 06:34:41 PM PDT 24
Peak memory 215620 kb
Host smart-dda27913-ca40-40fb-a5c4-63380d2aefc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670640124 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.2670640124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.3705044710
Short name T682
Test name
Test status
Simulation time 52259475394 ps
CPU time 1527.39 seconds
Started Jul 15 06:34:29 PM PDT 24
Finished Jul 15 06:59:58 PM PDT 24
Peak memory 391884 kb
Host smart-b20ae701-4507-4e71-adf0-2d8f2aaf54c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3705044710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3705044710 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.3193040595
Short name T406
Test name
Test status
Simulation time 190203748163 ps
CPU time 1925.87 seconds
Started Jul 15 06:34:29 PM PDT 24
Finished Jul 15 07:06:36 PM PDT 24
Peak memory 387780 kb
Host smart-51d710ea-532c-4ad1-8079-1ea77ef375bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3193040595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.3193040595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.2473830732
Short name T35
Test name
Test status
Simulation time 204367914142 ps
CPU time 1308.27 seconds
Started Jul 15 06:34:29 PM PDT 24
Finished Jul 15 06:56:18 PM PDT 24
Peak memory 335864 kb
Host smart-c8266b96-79fa-43b3-89b3-4e661bb7059f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2473830732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.2473830732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.121198789
Short name T737
Test name
Test status
Simulation time 9603384219 ps
CPU time 753.69 seconds
Started Jul 15 06:34:29 PM PDT 24
Finished Jul 15 06:47:04 PM PDT 24
Peak memory 296088 kb
Host smart-11e175f5-d7b1-4771-b77c-207a56a2cb50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=121198789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.121198789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.3994536117
Short name T164
Test name
Test status
Simulation time 678568143746 ps
CPU time 4806.24 seconds
Started Jul 15 06:34:27 PM PDT 24
Finished Jul 15 07:54:34 PM PDT 24
Peak memory 635872 kb
Host smart-634a17b2-7168-4fb7-bd1a-ff92268ea3f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3994536117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3994536117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.1447177721
Short name T891
Test name
Test status
Simulation time 48412431632 ps
CPU time 3373.91 seconds
Started Jul 15 06:34:30 PM PDT 24
Finished Jul 15 07:30:45 PM PDT 24
Peak memory 558812 kb
Host smart-3e897e45-f8bc-4b31-b144-32f7e70d762b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1447177721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1447177721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.1045023728
Short name T947
Test name
Test status
Simulation time 45356485 ps
CPU time 0.77 seconds
Started Jul 15 06:32:44 PM PDT 24
Finished Jul 15 06:32:48 PM PDT 24
Peak memory 205260 kb
Host smart-c58875fe-12e0-465f-b8f5-a480582a641c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045023728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1045023728 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.1595093463
Short name T363
Test name
Test status
Simulation time 15872959855 ps
CPU time 169.37 seconds
Started Jul 15 06:32:38 PM PDT 24
Finished Jul 15 06:35:28 PM PDT 24
Peak memory 238080 kb
Host smart-82c90114-b062-4e17-9d28-81178b9441d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595093463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1595093463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.3094550407
Short name T857
Test name
Test status
Simulation time 8863962828 ps
CPU time 64.26 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 06:33:48 PM PDT 24
Peak memory 224728 kb
Host smart-1804a4cc-e3f3-4cd6-b7e6-a29812416e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094550407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3094550407 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2831633639
Short name T320
Test name
Test status
Simulation time 4882940070 ps
CPU time 365.07 seconds
Started Jul 15 06:32:38 PM PDT 24
Finished Jul 15 06:38:44 PM PDT 24
Peak memory 229824 kb
Host smart-6a343ff3-aa8e-4fd8-a977-3ea79639125f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831633639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2831633639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.3518350207
Short name T527
Test name
Test status
Simulation time 7483174784 ps
CPU time 38.57 seconds
Started Jul 15 06:32:41 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 220848 kb
Host smart-d03e0920-b1b4-4053-ad2e-f1cd1af2e6aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3518350207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3518350207 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.3808030108
Short name T313
Test name
Test status
Simulation time 7733040682 ps
CPU time 29.41 seconds
Started Jul 15 06:32:43 PM PDT 24
Finished Jul 15 06:33:14 PM PDT 24
Peak memory 223748 kb
Host smart-48b8f762-20be-4657-a3b6-571afb769abe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3808030108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3808030108 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.4006737741
Short name T777
Test name
Test status
Simulation time 15561128500 ps
CPU time 42.12 seconds
Started Jul 15 06:32:41 PM PDT 24
Finished Jul 15 06:33:25 PM PDT 24
Peak memory 215692 kb
Host smart-93a871e5-72af-4f58-a744-8c7bed2fdc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006737741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.4006737741 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3121286182
Short name T732
Test name
Test status
Simulation time 7438289142 ps
CPU time 81.16 seconds
Started Jul 15 06:32:45 PM PDT 24
Finished Jul 15 06:34:08 PM PDT 24
Peak memory 226880 kb
Host smart-9b1918b3-e785-482a-877e-b33bc1b29605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121286182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3121286182 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.228665326
Short name T32
Test name
Test status
Simulation time 7912551048 ps
CPU time 218.31 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 06:36:23 PM PDT 24
Peak memory 241352 kb
Host smart-be85300c-236c-484a-98da-25fbae345bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228665326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.228665326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.2037398414
Short name T68
Test name
Test status
Simulation time 518923864 ps
CPU time 3.52 seconds
Started Jul 15 06:32:43 PM PDT 24
Finished Jul 15 06:32:49 PM PDT 24
Peak memory 207284 kb
Host smart-a291c093-74a4-4d19-9e9c-ced875d5c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037398414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2037398414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.1173185591
Short name T278
Test name
Test status
Simulation time 169284431 ps
CPU time 1.37 seconds
Started Jul 15 06:32:46 PM PDT 24
Finished Jul 15 06:32:50 PM PDT 24
Peak memory 219568 kb
Host smart-35e151a3-0952-446a-9fdc-14b9e8bdad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173185591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1173185591 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.2970514956
Short name T818
Test name
Test status
Simulation time 108519890279 ps
CPU time 600.77 seconds
Started Jul 15 06:32:40 PM PDT 24
Finished Jul 15 06:42:43 PM PDT 24
Peak memory 269028 kb
Host smart-f6133c28-e1b2-47f7-b7af-85a81b6f7aca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970514956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.2970514956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.2395448817
Short name T331
Test name
Test status
Simulation time 4815434610 ps
CPU time 240.39 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 06:36:44 PM PDT 24
Peak memory 244076 kb
Host smart-4b67093c-2d02-476c-8b2f-4e4526827ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395448817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2395448817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.1983292529
Short name T12
Test name
Test status
Simulation time 6525750023 ps
CPU time 28.93 seconds
Started Jul 15 06:32:40 PM PDT 24
Finished Jul 15 06:33:11 PM PDT 24
Peak memory 251956 kb
Host smart-dec9828d-60f4-4a12-8a54-a58d70622ba3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983292529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1983292529 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.1528467414
Short name T1008
Test name
Test status
Simulation time 40769000465 ps
CPU time 407.17 seconds
Started Jul 15 06:32:35 PM PDT 24
Finished Jul 15 06:39:23 PM PDT 24
Peak memory 250652 kb
Host smart-eee2c0fa-b533-4521-93ea-591094ddd97f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528467414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1528467414 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.1039951851
Short name T754
Test name
Test status
Simulation time 2778572909 ps
CPU time 56.66 seconds
Started Jul 15 06:32:40 PM PDT 24
Finished Jul 15 06:33:37 PM PDT 24
Peak memory 218952 kb
Host smart-f419b82a-7a3b-412d-84f8-517e995dc2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039951851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.1039951851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.1724033611
Short name T1002
Test name
Test status
Simulation time 205062123386 ps
CPU time 1144.72 seconds
Started Jul 15 06:32:44 PM PDT 24
Finished Jul 15 06:51:51 PM PDT 24
Peak memory 352432 kb
Host smart-88d02ca3-8132-465c-9bfd-87ca39602e1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1724033611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1724033611 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.2682700508
Short name T1045
Test name
Test status
Simulation time 1132817442 ps
CPU time 5.43 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 06:32:44 PM PDT 24
Peak memory 215716 kb
Host smart-1f84e551-6f02-42b4-8278-95e4ee38d997
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682700508 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.2682700508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3252707352
Short name T612
Test name
Test status
Simulation time 251002407 ps
CPU time 4.73 seconds
Started Jul 15 06:32:40 PM PDT 24
Finished Jul 15 06:32:46 PM PDT 24
Peak memory 215756 kb
Host smart-1c08a8fd-2295-4d76-b724-82c8f0009352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252707352 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3252707352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.3598404349
Short name T972
Test name
Test status
Simulation time 112260941311 ps
CPU time 1889.24 seconds
Started Jul 15 06:32:37 PM PDT 24
Finished Jul 15 07:04:08 PM PDT 24
Peak memory 373408 kb
Host smart-deee2254-21dc-4845-9913-df5342b77833
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3598404349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3598404349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.967244176
Short name T239
Test name
Test status
Simulation time 315659620571 ps
CPU time 1710.73 seconds
Started Jul 15 06:32:36 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 372160 kb
Host smart-cd765b78-67e1-4caf-9b35-e3d19456039c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=967244176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.967244176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.1708530358
Short name T908
Test name
Test status
Simulation time 13485826535 ps
CPU time 1226.4 seconds
Started Jul 15 06:32:38 PM PDT 24
Finished Jul 15 06:53:05 PM PDT 24
Peak memory 332332 kb
Host smart-126fae26-5fbb-41c6-b712-1c6a98410e4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1708530358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1708530358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.3532065143
Short name T611
Test name
Test status
Simulation time 32725843360 ps
CPU time 824.6 seconds
Started Jul 15 06:32:39 PM PDT 24
Finished Jul 15 06:46:25 PM PDT 24
Peak memory 295728 kb
Host smart-28120207-275c-4765-ac2e-faacc35256c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3532065143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3532065143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.656005617
Short name T250
Test name
Test status
Simulation time 154061604376 ps
CPU time 4076.2 seconds
Started Jul 15 06:32:39 PM PDT 24
Finished Jul 15 07:40:37 PM PDT 24
Peak memory 649728 kb
Host smart-10fbaa22-b516-4d2f-99eb-917bf53ef31e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=656005617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.656005617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.407451111
Short name T1069
Test name
Test status
Simulation time 314534650262 ps
CPU time 4276.32 seconds
Started Jul 15 06:32:39 PM PDT 24
Finished Jul 15 07:43:57 PM PDT 24
Peak memory 550496 kb
Host smart-6b22539d-6dca-4ad5-808e-b508b7316130
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=407451111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.407451111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3172182480
Short name T902
Test name
Test status
Simulation time 44499351 ps
CPU time 0.76 seconds
Started Jul 15 06:34:44 PM PDT 24
Finished Jul 15 06:34:45 PM PDT 24
Peak memory 205328 kb
Host smart-31fd9f48-68be-4041-bc9b-bd64a249a6f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172182480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3172182480 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.2885809079
Short name T856
Test name
Test status
Simulation time 9199307404 ps
CPU time 62.95 seconds
Started Jul 15 06:34:39 PM PDT 24
Finished Jul 15 06:35:43 PM PDT 24
Peak memory 225928 kb
Host smart-c19d9d98-f86a-4db9-bf6b-50446c7b0283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885809079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2885809079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.3945599307
Short name T40
Test name
Test status
Simulation time 4367580420 ps
CPU time 176.93 seconds
Started Jul 15 06:34:41 PM PDT 24
Finished Jul 15 06:37:38 PM PDT 24
Peak memory 224588 kb
Host smart-31607912-f2eb-4eb2-b419-836be7ef9f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945599307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3945599307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.1054109097
Short name T809
Test name
Test status
Simulation time 148020170 ps
CPU time 8.7 seconds
Started Jul 15 06:34:39 PM PDT 24
Finished Jul 15 06:34:48 PM PDT 24
Peak memory 223768 kb
Host smart-1a975a85-00c3-4432-9fa5-2bd1bdae02a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054109097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1054109097 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.2611084423
Short name T1017
Test name
Test status
Simulation time 6957455328 ps
CPU time 118.06 seconds
Started Jul 15 06:34:39 PM PDT 24
Finished Jul 15 06:36:38 PM PDT 24
Peak memory 248592 kb
Host smart-a73b79c4-7cb6-453c-9e3d-8fa7034e449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611084423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.2611084423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.3176487681
Short name T66
Test name
Test status
Simulation time 4973462743 ps
CPU time 7.86 seconds
Started Jul 15 06:34:40 PM PDT 24
Finished Jul 15 06:34:48 PM PDT 24
Peak memory 207448 kb
Host smart-3423e228-939d-4e3b-9773-034db78ddd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176487681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3176487681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.1139949398
Short name T439
Test name
Test status
Simulation time 80269306 ps
CPU time 1.33 seconds
Started Jul 15 06:34:50 PM PDT 24
Finished Jul 15 06:34:52 PM PDT 24
Peak memory 215664 kb
Host smart-7fd740f2-966f-4c6f-84fa-5f64978e2790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139949398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1139949398 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.3901534011
Short name T464
Test name
Test status
Simulation time 56843745621 ps
CPU time 814.39 seconds
Started Jul 15 06:34:35 PM PDT 24
Finished Jul 15 06:48:10 PM PDT 24
Peak memory 294372 kb
Host smart-ff325346-d7a4-4f29-9758-a5e501ec0e97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901534011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.3901534011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.3086681323
Short name T940
Test name
Test status
Simulation time 12803574115 ps
CPU time 319.52 seconds
Started Jul 15 06:34:35 PM PDT 24
Finished Jul 15 06:39:55 PM PDT 24
Peak memory 247160 kb
Host smart-1d01c018-47ae-485e-89e5-0a77dcc62b7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086681323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3086681323 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.1071059503
Short name T1030
Test name
Test status
Simulation time 2145940730 ps
CPU time 14.21 seconds
Started Jul 15 06:34:35 PM PDT 24
Finished Jul 15 06:34:50 PM PDT 24
Peak memory 223812 kb
Host smart-293a2853-abaf-4a11-9a40-ac5b26ac8d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071059503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1071059503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.1291914029
Short name T892
Test name
Test status
Simulation time 69303928 ps
CPU time 3.95 seconds
Started Jul 15 06:34:40 PM PDT 24
Finished Jul 15 06:34:44 PM PDT 24
Peak memory 215652 kb
Host smart-3da07f58-17de-4491-b57b-9f69a691d6de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291914029 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.1291914029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.4190462009
Short name T1068
Test name
Test status
Simulation time 1230506006 ps
CPU time 5 seconds
Started Jul 15 06:34:39 PM PDT 24
Finished Jul 15 06:34:45 PM PDT 24
Peak memory 215596 kb
Host smart-c9ef6c8f-95f8-433c-ae09-f43498bb8228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190462009 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.4190462009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.1467051427
Short name T704
Test name
Test status
Simulation time 344127405362 ps
CPU time 1740.6 seconds
Started Jul 15 06:34:39 PM PDT 24
Finished Jul 15 07:03:40 PM PDT 24
Peak memory 377236 kb
Host smart-b174b1d9-659d-4927-aac4-0c6889df8ad5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1467051427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.1467051427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.1710856909
Short name T492
Test name
Test status
Simulation time 407753501298 ps
CPU time 1755.79 seconds
Started Jul 15 06:34:40 PM PDT 24
Finished Jul 15 07:03:56 PM PDT 24
Peak memory 373944 kb
Host smart-21fe13f2-d238-446c-848a-11b1ecb5e004
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1710856909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.1710856909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.4153334540
Short name T825
Test name
Test status
Simulation time 1017499487117 ps
CPU time 1835.43 seconds
Started Jul 15 06:34:39 PM PDT 24
Finished Jul 15 07:05:15 PM PDT 24
Peak memory 339012 kb
Host smart-fd7f0ca2-b8b5-4e08-8e55-3f9d0d4ed4fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4153334540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.4153334540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.2873365694
Short name T941
Test name
Test status
Simulation time 123400401404 ps
CPU time 952.34 seconds
Started Jul 15 06:34:40 PM PDT 24
Finished Jul 15 06:50:33 PM PDT 24
Peak memory 291532 kb
Host smart-093cf7ab-2915-490b-8c5f-967311851e52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2873365694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.2873365694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.614002074
Short name T840
Test name
Test status
Simulation time 1273694573865 ps
CPU time 5380.97 seconds
Started Jul 15 06:34:40 PM PDT 24
Finished Jul 15 08:04:22 PM PDT 24
Peak memory 642844 kb
Host smart-f0f64250-fe2e-489b-890d-38602261400f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=614002074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.614002074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.1179074022
Short name T489
Test name
Test status
Simulation time 628069030363 ps
CPU time 4003.45 seconds
Started Jul 15 06:34:39 PM PDT 24
Finished Jul 15 07:41:24 PM PDT 24
Peak memory 555344 kb
Host smart-79f3e78e-7f15-416b-9f97-ae0c1f16f858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1179074022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.1179074022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1808239153
Short name T803
Test name
Test status
Simulation time 41089443 ps
CPU time 0.83 seconds
Started Jul 15 06:34:56 PM PDT 24
Finished Jul 15 06:34:58 PM PDT 24
Peak memory 205308 kb
Host smart-5502f0a7-7206-4973-9da0-eb36b8521479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808239153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1808239153 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_burst_write.3082241280
Short name T584
Test name
Test status
Simulation time 18240344238 ps
CPU time 544.29 seconds
Started Jul 15 06:34:49 PM PDT 24
Finished Jul 15 06:43:53 PM PDT 24
Peak memory 230844 kb
Host smart-378acc8e-b3eb-41d5-b3b0-4f7906d8080c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082241280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3082241280 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_error.273194442
Short name T827
Test name
Test status
Simulation time 2653091699 ps
CPU time 94.72 seconds
Started Jul 15 06:34:56 PM PDT 24
Finished Jul 15 06:36:32 PM PDT 24
Peak memory 240584 kb
Host smart-ee3ee56d-7b82-4968-9a3e-581ea7c1e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273194442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.273194442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.3703280610
Short name T763
Test name
Test status
Simulation time 7586893384 ps
CPU time 8.4 seconds
Started Jul 15 06:34:57 PM PDT 24
Finished Jul 15 06:35:06 PM PDT 24
Peak memory 207344 kb
Host smart-daf2ebeb-431e-482f-b2a4-a7d94281b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703280610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3703280610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.27374886
Short name T496
Test name
Test status
Simulation time 172613935 ps
CPU time 1.25 seconds
Started Jul 15 06:34:57 PM PDT 24
Finished Jul 15 06:34:59 PM PDT 24
Peak memory 215504 kb
Host smart-7be96247-d345-475f-b248-ce14920c68c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27374886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.27374886 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.24250539
Short name T793
Test name
Test status
Simulation time 49821182009 ps
CPU time 2207.88 seconds
Started Jul 15 06:34:44 PM PDT 24
Finished Jul 15 07:11:33 PM PDT 24
Peak memory 464812 kb
Host smart-54402348-a2e8-4e76-9e7e-72d6ae61e18e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24250539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and
_output.24250539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.3499828503
Short name T396
Test name
Test status
Simulation time 128400299116 ps
CPU time 480.17 seconds
Started Jul 15 06:34:51 PM PDT 24
Finished Jul 15 06:42:51 PM PDT 24
Peak memory 251712 kb
Host smart-49274bb7-2564-4f2d-8a24-9a2ebd45544e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499828503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3499828503 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.828670028
Short name T235
Test name
Test status
Simulation time 525149464 ps
CPU time 7.03 seconds
Started Jul 15 06:34:44 PM PDT 24
Finished Jul 15 06:34:52 PM PDT 24
Peak memory 216904 kb
Host smart-5abde348-94ff-4170-a48c-13cac86a7a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828670028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.828670028 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.2647411751
Short name T987
Test name
Test status
Simulation time 170769717846 ps
CPU time 1153.71 seconds
Started Jul 15 06:34:56 PM PDT 24
Finished Jul 15 06:54:11 PM PDT 24
Peak memory 338636 kb
Host smart-2910152b-c4c2-4d5a-90d8-004cb4744ee9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2647411751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2647411751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.959520582
Short name T1034
Test name
Test status
Simulation time 223483757 ps
CPU time 4.41 seconds
Started Jul 15 06:34:53 PM PDT 24
Finished Jul 15 06:34:58 PM PDT 24
Peak memory 215668 kb
Host smart-c34dc8bc-a5ee-46ec-aa4c-8a5294d93e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959520582 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.kmac_test_vectors_kmac.959520582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.824655732
Short name T855
Test name
Test status
Simulation time 276923819 ps
CPU time 5.08 seconds
Started Jul 15 06:34:50 PM PDT 24
Finished Jul 15 06:34:56 PM PDT 24
Peak memory 215640 kb
Host smart-d1f8a6b5-7a3e-483b-aa28-84ea7c9b310d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824655732 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.kmac_test_vectors_kmac_xof.824655732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.2697800800
Short name T1051
Test name
Test status
Simulation time 19459577482 ps
CPU time 1620.19 seconds
Started Jul 15 06:34:45 PM PDT 24
Finished Jul 15 07:01:46 PM PDT 24
Peak memory 392848 kb
Host smart-9cf5bf91-d909-48e3-9d38-9dc5b9c7af9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2697800800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.2697800800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3168097329
Short name T436
Test name
Test status
Simulation time 68923603540 ps
CPU time 1406.43 seconds
Started Jul 15 06:34:44 PM PDT 24
Finished Jul 15 06:58:11 PM PDT 24
Peak memory 363720 kb
Host smart-577cd99d-9c8c-4701-96cd-b8cf9f34b249
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3168097329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3168097329 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.3341875246
Short name T158
Test name
Test status
Simulation time 47163284313 ps
CPU time 1221.89 seconds
Started Jul 15 06:34:44 PM PDT 24
Finished Jul 15 06:55:07 PM PDT 24
Peak memory 336440 kb
Host smart-939ae627-bf78-4d3f-a027-1d924a44c469
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3341875246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3341875246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.872982712
Short name T618
Test name
Test status
Simulation time 9463927693 ps
CPU time 883.14 seconds
Started Jul 15 06:34:45 PM PDT 24
Finished Jul 15 06:49:29 PM PDT 24
Peak memory 294404 kb
Host smart-6aefd949-838a-4f43-9e10-7b74c9bf6c89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=872982712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.872982712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.59237462
Short name T800
Test name
Test status
Simulation time 522422249241 ps
CPU time 5005.26 seconds
Started Jul 15 06:34:51 PM PDT 24
Finished Jul 15 07:58:17 PM PDT 24
Peak memory 646676 kb
Host smart-d9fb6bd4-d7d8-4ff1-950e-4d76707a1a2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=59237462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.59237462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.1920552579
Short name T936
Test name
Test status
Simulation time 86253984560 ps
CPU time 3436.33 seconds
Started Jul 15 06:34:51 PM PDT 24
Finished Jul 15 07:32:08 PM PDT 24
Peak memory 558488 kb
Host smart-57508a03-19e3-443d-9be6-86e543872232
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1920552579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.1920552579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2047194702
Short name T1082
Test name
Test status
Simulation time 14737351 ps
CPU time 0.78 seconds
Started Jul 15 06:35:03 PM PDT 24
Finished Jul 15 06:35:05 PM PDT 24
Peak memory 205296 kb
Host smart-0ce94ab3-78b0-46b9-8aba-3d1bd1c60e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047194702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2047194702 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.2625344440
Short name T882
Test name
Test status
Simulation time 1758427486 ps
CPU time 40.57 seconds
Started Jul 15 06:35:01 PM PDT 24
Finished Jul 15 06:35:42 PM PDT 24
Peak memory 223780 kb
Host smart-3ad1a0e1-3c31-4682-b9ba-4bdd0831200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625344440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2625344440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.2585556207
Short name T622
Test name
Test status
Simulation time 20343587132 ps
CPU time 162.45 seconds
Started Jul 15 06:35:00 PM PDT 24
Finished Jul 15 06:37:43 PM PDT 24
Peak memory 223192 kb
Host smart-8d92c03e-032f-4b88-bf7a-322d8d9a8c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585556207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2585556207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.2172399074
Short name T644
Test name
Test status
Simulation time 99300860 ps
CPU time 1.65 seconds
Started Jul 15 06:35:03 PM PDT 24
Finished Jul 15 06:35:05 PM PDT 24
Peak memory 217028 kb
Host smart-4dc5b3a1-495a-4306-b82a-36410692e655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172399074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2172399074 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2275043152
Short name T441
Test name
Test status
Simulation time 60154018045 ps
CPU time 335.58 seconds
Started Jul 15 06:35:03 PM PDT 24
Finished Jul 15 06:40:39 PM PDT 24
Peak memory 255928 kb
Host smart-d6b15216-714e-4608-9b88-d1f5d0383e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275043152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2275043152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.3191389825
Short name T64
Test name
Test status
Simulation time 1260928928 ps
CPU time 2.24 seconds
Started Jul 15 06:35:03 PM PDT 24
Finished Jul 15 06:35:06 PM PDT 24
Peak memory 207228 kb
Host smart-6e1c72d7-7855-4fa1-a0aa-53f81c3866f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191389825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3191389825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.2593840025
Short name T600
Test name
Test status
Simulation time 92217910274 ps
CPU time 1646.57 seconds
Started Jul 15 06:34:56 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 400600 kb
Host smart-d60da5f1-f3cf-4144-9b2f-e5a6918b4fa8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593840025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.2593840025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3232214831
Short name T452
Test name
Test status
Simulation time 9160686582 ps
CPU time 363.99 seconds
Started Jul 15 06:34:56 PM PDT 24
Finished Jul 15 06:41:00 PM PDT 24
Peak memory 250816 kb
Host smart-08cb004a-c6d4-4fa0-ba7a-3c4cd6a98516
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232214831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3232214831 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.3765050159
Short name T817
Test name
Test status
Simulation time 1155275623 ps
CPU time 29.33 seconds
Started Jul 15 06:34:58 PM PDT 24
Finished Jul 15 06:35:27 PM PDT 24
Peak memory 219360 kb
Host smart-33cc2dee-2753-42bc-a2eb-e4ee2d6ac29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765050159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3765050159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.1624164897
Short name T91
Test name
Test status
Simulation time 16087073512 ps
CPU time 336.17 seconds
Started Jul 15 06:35:04 PM PDT 24
Finished Jul 15 06:40:41 PM PDT 24
Peak memory 300660 kb
Host smart-bdb9c163-7027-4e8b-a635-c26ad5d5e49b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1624164897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1624164897 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1966620021
Short name T180
Test name
Test status
Simulation time 252081595 ps
CPU time 4.14 seconds
Started Jul 15 06:35:02 PM PDT 24
Finished Jul 15 06:35:07 PM PDT 24
Peak memory 215744 kb
Host smart-6f97c859-85cd-469b-8891-426f1e349cf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966620021 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1966620021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3181972939
Short name T311
Test name
Test status
Simulation time 196065164 ps
CPU time 4.17 seconds
Started Jul 15 06:35:01 PM PDT 24
Finished Jul 15 06:35:06 PM PDT 24
Peak memory 215644 kb
Host smart-f1b2c97a-9579-41d9-8381-0d5e99d82f88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181972939 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3181972939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.1201190736
Short name T252
Test name
Test status
Simulation time 99649018886 ps
CPU time 1895.28 seconds
Started Jul 15 06:34:56 PM PDT 24
Finished Jul 15 07:06:32 PM PDT 24
Peak memory 378748 kb
Host smart-40bb18b6-82b0-4ce9-a545-fa50631859c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1201190736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.1201190736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.401894255
Short name T683
Test name
Test status
Simulation time 18499940264 ps
CPU time 1431.84 seconds
Started Jul 15 06:34:56 PM PDT 24
Finished Jul 15 06:58:48 PM PDT 24
Peak memory 374788 kb
Host smart-9ef3b7e4-8076-47d9-9693-c987595ace8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=401894255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.401894255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.581130041
Short name T998
Test name
Test status
Simulation time 589545938129 ps
CPU time 1619.91 seconds
Started Jul 15 06:34:58 PM PDT 24
Finished Jul 15 07:01:58 PM PDT 24
Peak memory 336228 kb
Host smart-3b197f25-4035-47ca-ba87-72465c6c1be4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=581130041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.581130041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.4135200318
Short name T861
Test name
Test status
Simulation time 58969467055 ps
CPU time 908.33 seconds
Started Jul 15 06:34:57 PM PDT 24
Finished Jul 15 06:50:06 PM PDT 24
Peak memory 290424 kb
Host smart-e1614b39-fdfe-4754-ba7c-12435e0fefb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4135200318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.4135200318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.2464309001
Short name T1004
Test name
Test status
Simulation time 300913946648 ps
CPU time 4233.67 seconds
Started Jul 15 06:35:00 PM PDT 24
Finished Jul 15 07:45:34 PM PDT 24
Peak memory 656380 kb
Host smart-43ab17aa-7674-4d1c-8086-a8b1eff6b2a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2464309001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.2464309001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.156202186
Short name T756
Test name
Test status
Simulation time 87805707297 ps
CPU time 3595.81 seconds
Started Jul 15 06:34:57 PM PDT 24
Finished Jul 15 07:34:54 PM PDT 24
Peak memory 574828 kb
Host smart-0e91ef48-7291-4d45-a41c-d53a264096cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=156202186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.156202186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.1014471084
Short name T309
Test name
Test status
Simulation time 62720396 ps
CPU time 0.77 seconds
Started Jul 15 06:35:16 PM PDT 24
Finished Jul 15 06:35:17 PM PDT 24
Peak memory 205260 kb
Host smart-ec2ff91d-2560-47a8-b80f-aac17b6fe101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014471084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1014471084 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.4274297251
Short name T999
Test name
Test status
Simulation time 9503671800 ps
CPU time 101.15 seconds
Started Jul 15 06:35:15 PM PDT 24
Finished Jul 15 06:36:57 PM PDT 24
Peak memory 229900 kb
Host smart-9d139667-6530-4b81-ab88-00ab9b23183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274297251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.4274297251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.4210916617
Short name T465
Test name
Test status
Simulation time 139762339640 ps
CPU time 781.27 seconds
Started Jul 15 06:35:09 PM PDT 24
Finished Jul 15 06:48:11 PM PDT 24
Peak memory 232352 kb
Host smart-2f48262a-3185-42d3-b790-b9faa69b53fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210916617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.4210916617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.633079598
Short name T109
Test name
Test status
Simulation time 4915500156 ps
CPU time 183.14 seconds
Started Jul 15 06:35:17 PM PDT 24
Finished Jul 15 06:38:21 PM PDT 24
Peak memory 238912 kb
Host smart-af62dab6-1a34-4dab-9a5a-2a9935e38b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633079598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.633079598 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.3835361138
Short name T28
Test name
Test status
Simulation time 12268784586 ps
CPU time 342.37 seconds
Started Jul 15 06:35:17 PM PDT 24
Finished Jul 15 06:41:00 PM PDT 24
Peak memory 256560 kb
Host smart-2735a130-2e9b-4772-9ae9-5f0b7abcd80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835361138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3835361138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.2409664830
Short name T358
Test name
Test status
Simulation time 600878966 ps
CPU time 3.31 seconds
Started Jul 15 06:35:15 PM PDT 24
Finished Jul 15 06:35:19 PM PDT 24
Peak memory 207268 kb
Host smart-23f130d8-5a6c-418a-884f-4f36612ea710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409664830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2409664830 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.347440590
Short name T354
Test name
Test status
Simulation time 160737296 ps
CPU time 1.26 seconds
Started Jul 15 06:35:16 PM PDT 24
Finished Jul 15 06:35:18 PM PDT 24
Peak memory 215544 kb
Host smart-a18b01ec-2951-4229-961b-73d6d4b34c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347440590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.347440590 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.2870813992
Short name T189
Test name
Test status
Simulation time 266241159392 ps
CPU time 1733.53 seconds
Started Jul 15 06:35:09 PM PDT 24
Finished Jul 15 07:04:03 PM PDT 24
Peak memory 377188 kb
Host smart-287b3fb4-2196-42d7-b33e-3b95f8cb062a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870813992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.2870813992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.3357442674
Short name T275
Test name
Test status
Simulation time 38554970749 ps
CPU time 195.8 seconds
Started Jul 15 06:35:09 PM PDT 24
Finished Jul 15 06:38:25 PM PDT 24
Peak memory 235252 kb
Host smart-3ace284e-8e7e-448c-bf88-42ea8b7ac4c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357442674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3357442674 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1390243647
Short name T802
Test name
Test status
Simulation time 4544573284 ps
CPU time 22.54 seconds
Started Jul 15 06:35:04 PM PDT 24
Finished Jul 15 06:35:27 PM PDT 24
Peak memory 223928 kb
Host smart-74692440-f133-44ff-8083-4d363b6e443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390243647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1390243647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3960321966
Short name T349
Test name
Test status
Simulation time 233999491 ps
CPU time 3.37 seconds
Started Jul 15 06:35:15 PM PDT 24
Finished Jul 15 06:35:19 PM PDT 24
Peak memory 215632 kb
Host smart-66726052-af2e-4b62-bba9-5bb3a23ae3e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3960321966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3960321966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.1354315611
Short name T591
Test name
Test status
Simulation time 341979608 ps
CPU time 4.8 seconds
Started Jul 15 06:35:16 PM PDT 24
Finished Jul 15 06:35:21 PM PDT 24
Peak memory 209228 kb
Host smart-fa5c0736-fe5f-46c6-9513-784531a399cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354315611 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.1354315611 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1857053305
Short name T36
Test name
Test status
Simulation time 915358695 ps
CPU time 5.58 seconds
Started Jul 15 06:35:14 PM PDT 24
Finished Jul 15 06:35:20 PM PDT 24
Peak memory 215628 kb
Host smart-22886765-a168-4670-847e-8d76e91b4408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857053305 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1857053305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.733315974
Short name T182
Test name
Test status
Simulation time 78311219109 ps
CPU time 1677.39 seconds
Started Jul 15 06:35:12 PM PDT 24
Finished Jul 15 07:03:10 PM PDT 24
Peak memory 391280 kb
Host smart-9b2a6056-de30-4622-b583-9d32557709b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=733315974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.733315974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.2244649413
Short name T356
Test name
Test status
Simulation time 74910916620 ps
CPU time 1459.22 seconds
Started Jul 15 06:35:10 PM PDT 24
Finished Jul 15 06:59:30 PM PDT 24
Peak memory 364372 kb
Host smart-170ce8eb-e3b0-47ac-bbcd-3ba8cfc45ff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2244649413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.2244649413 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.1256447873
Short name T312
Test name
Test status
Simulation time 46906448024 ps
CPU time 1246.87 seconds
Started Jul 15 06:35:10 PM PDT 24
Finished Jul 15 06:55:57 PM PDT 24
Peak memory 334928 kb
Host smart-1245a985-3bdd-4dff-bda8-035f1f39030d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1256447873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.1256447873 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.3717001024
Short name T248
Test name
Test status
Simulation time 64008902920 ps
CPU time 927.25 seconds
Started Jul 15 06:35:08 PM PDT 24
Finished Jul 15 06:50:36 PM PDT 24
Peak memory 298948 kb
Host smart-65a95511-b431-41ec-a29e-f9a905dbfb45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3717001024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.3717001024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.2215063222
Short name T530
Test name
Test status
Simulation time 212276018224 ps
CPU time 4033.96 seconds
Started Jul 15 06:35:11 PM PDT 24
Finished Jul 15 07:42:26 PM PDT 24
Peak memory 652156 kb
Host smart-e47ec421-059f-495f-8406-22ef4184e2fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2215063222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.2215063222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.3697353564
Short name T769
Test name
Test status
Simulation time 296805269976 ps
CPU time 3978.97 seconds
Started Jul 15 06:35:09 PM PDT 24
Finished Jul 15 07:41:29 PM PDT 24
Peak memory 579280 kb
Host smart-fd0e0063-26f1-4710-b604-63a583de9176
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3697353564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3697353564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.2124926610
Short name T721
Test name
Test status
Simulation time 118459158 ps
CPU time 0.81 seconds
Started Jul 15 06:35:29 PM PDT 24
Finished Jul 15 06:35:30 PM PDT 24
Peak memory 205252 kb
Host smart-ce0e00bf-997b-49be-a77f-cffb64379848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124926610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2124926610 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3145631474
Short name T806
Test name
Test status
Simulation time 3436883313 ps
CPU time 62.21 seconds
Started Jul 15 06:35:22 PM PDT 24
Finished Jul 15 06:36:24 PM PDT 24
Peak memory 224428 kb
Host smart-f14b3fd7-1327-482a-9fa6-5906f0417f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145631474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3145631474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.1207458008
Short name T283
Test name
Test status
Simulation time 7047502329 ps
CPU time 102.9 seconds
Started Jul 15 06:35:16 PM PDT 24
Finished Jul 15 06:36:59 PM PDT 24
Peak memory 223820 kb
Host smart-a2623e70-95a3-48cc-bbb1-9c70bfd4bfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207458008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1207458008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.658195968
Short name T724
Test name
Test status
Simulation time 3079508665 ps
CPU time 177.28 seconds
Started Jul 15 06:35:21 PM PDT 24
Finished Jul 15 06:38:19 PM PDT 24
Peak memory 238128 kb
Host smart-c31c4dff-e5f6-468c-86ed-1312e6817aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658195968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.658195968 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.1602277036
Short name T619
Test name
Test status
Simulation time 9091755992 ps
CPU time 177.65 seconds
Started Jul 15 06:35:22 PM PDT 24
Finished Jul 15 06:38:20 PM PDT 24
Peak memory 249284 kb
Host smart-b028141e-91aa-4de0-aafc-f395f1c2f368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602277036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1602277036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.4128724421
Short name T949
Test name
Test status
Simulation time 144399052 ps
CPU time 1.4 seconds
Started Jul 15 06:35:28 PM PDT 24
Finished Jul 15 06:35:30 PM PDT 24
Peak memory 207276 kb
Host smart-d40f4e7b-a3d0-4a93-8c84-a3c638c17908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128724421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.4128724421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.80904436
Short name T592
Test name
Test status
Simulation time 329405478 ps
CPU time 1.23 seconds
Started Jul 15 06:35:27 PM PDT 24
Finished Jul 15 06:35:29 PM PDT 24
Peak memory 215536 kb
Host smart-021f5921-fa50-4aad-a5cd-4efa0eba9ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80904436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.80904436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.3356890149
Short name T262
Test name
Test status
Simulation time 81989469304 ps
CPU time 2284.69 seconds
Started Jul 15 06:35:15 PM PDT 24
Finished Jul 15 07:13:20 PM PDT 24
Peak memory 449676 kb
Host smart-98adb8c5-3c41-422d-bf84-68f5fa4e2509
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356890149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.3356890149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.3126690915
Short name T332
Test name
Test status
Simulation time 53252748450 ps
CPU time 198.56 seconds
Started Jul 15 06:35:15 PM PDT 24
Finished Jul 15 06:38:34 PM PDT 24
Peak memory 234284 kb
Host smart-6454da85-cef1-4662-a40a-d9995920672c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126690915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3126690915 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.1914627073
Short name T424
Test name
Test status
Simulation time 694660148 ps
CPU time 8.42 seconds
Started Jul 15 06:35:16 PM PDT 24
Finished Jul 15 06:35:25 PM PDT 24
Peak memory 223772 kb
Host smart-08778b9b-4a5d-46fe-b993-53658ade69a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914627073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1914627073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.612472492
Short name T438
Test name
Test status
Simulation time 51057745284 ps
CPU time 807.31 seconds
Started Jul 15 06:35:29 PM PDT 24
Finished Jul 15 06:48:57 PM PDT 24
Peak memory 326976 kb
Host smart-9438a676-0258-42cc-a396-3cd33dffd033
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=612472492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.612472492 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.3520531832
Short name T903
Test name
Test status
Simulation time 137131084 ps
CPU time 4.09 seconds
Started Jul 15 06:35:23 PM PDT 24
Finished Jul 15 06:35:27 PM PDT 24
Peak memory 215628 kb
Host smart-b6d96f4b-0407-4f4f-b51c-9a28bab511a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520531832 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.3520531832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.362938115
Short name T873
Test name
Test status
Simulation time 128024419 ps
CPU time 3.85 seconds
Started Jul 15 06:35:23 PM PDT 24
Finished Jul 15 06:35:27 PM PDT 24
Peak memory 215672 kb
Host smart-8616cd88-ab21-4d34-afb4-b6e96319e24e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362938115 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.362938115 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.1893349499
Short name T279
Test name
Test status
Simulation time 103080045405 ps
CPU time 2103.27 seconds
Started Jul 15 06:35:17 PM PDT 24
Finished Jul 15 07:10:21 PM PDT 24
Peak memory 399108 kb
Host smart-531458bd-512b-4daa-917d-5d0b64e6fbef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1893349499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.1893349499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.2305320408
Short name T1031
Test name
Test status
Simulation time 79803618724 ps
CPU time 1538.58 seconds
Started Jul 15 06:35:24 PM PDT 24
Finished Jul 15 07:01:03 PM PDT 24
Peak memory 369604 kb
Host smart-1c974367-5bfb-4d77-a2bb-2f2e62408808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2305320408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.2305320408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.2753338676
Short name T574
Test name
Test status
Simulation time 46906746002 ps
CPU time 1212.23 seconds
Started Jul 15 06:35:21 PM PDT 24
Finished Jul 15 06:55:34 PM PDT 24
Peak memory 334992 kb
Host smart-bed9aa10-3b0a-454f-8cbb-e87fc54930d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2753338676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.2753338676 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.2190906201
Short name T528
Test name
Test status
Simulation time 32715398941 ps
CPU time 790.58 seconds
Started Jul 15 06:35:22 PM PDT 24
Finished Jul 15 06:48:33 PM PDT 24
Peak memory 294000 kb
Host smart-32c6b9f9-75d8-4d26-97f3-bd33a31f77ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2190906201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2190906201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.1242646628
Short name T160
Test name
Test status
Simulation time 362179988573 ps
CPU time 4989.23 seconds
Started Jul 15 06:35:21 PM PDT 24
Finished Jul 15 07:58:32 PM PDT 24
Peak memory 637880 kb
Host smart-766bb0db-c939-4e23-937a-9aa22d0ffed6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1242646628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.1242646628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.161797228
Short name T226
Test name
Test status
Simulation time 603787754764 ps
CPU time 3859.14 seconds
Started Jul 15 06:35:22 PM PDT 24
Finished Jul 15 07:39:42 PM PDT 24
Peak memory 561488 kb
Host smart-e7bfa961-754b-47c0-a587-a78dd0bbd948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=161797228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.161797228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.70622805
Short name T508
Test name
Test status
Simulation time 38233215 ps
CPU time 0.79 seconds
Started Jul 15 06:35:41 PM PDT 24
Finished Jul 15 06:35:42 PM PDT 24
Peak memory 205436 kb
Host smart-9994c39a-7fdb-4293-b4c1-40bc4dde1962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70622805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.70622805 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.2655700026
Short name T274
Test name
Test status
Simulation time 1542163412 ps
CPU time 25.35 seconds
Started Jul 15 06:35:39 PM PDT 24
Finished Jul 15 06:36:05 PM PDT 24
Peak memory 220028 kb
Host smart-522ff230-d6b7-4d06-b538-b675df3f3b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655700026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2655700026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.902105745
Short name T170
Test name
Test status
Simulation time 27568001465 ps
CPU time 475.68 seconds
Started Jul 15 06:35:29 PM PDT 24
Finished Jul 15 06:43:25 PM PDT 24
Peak memory 230212 kb
Host smart-bea34857-2b36-475e-b2fa-7ca217cd065a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902105745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.902105745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.3682385295
Short name T18
Test name
Test status
Simulation time 11045441061 ps
CPU time 88.42 seconds
Started Jul 15 06:35:38 PM PDT 24
Finished Jul 15 06:37:07 PM PDT 24
Peak memory 228180 kb
Host smart-45379a5a-4f01-4709-8199-5abd62ba6d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682385295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3682385295 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.869458883
Short name T728
Test name
Test status
Simulation time 618718674 ps
CPU time 20.84 seconds
Started Jul 15 06:35:42 PM PDT 24
Finished Jul 15 06:36:03 PM PDT 24
Peak memory 235964 kb
Host smart-3e16b2e7-de13-4575-9c67-d6dada132240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869458883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.869458883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.2877833991
Short name T984
Test name
Test status
Simulation time 1235547872 ps
CPU time 6.3 seconds
Started Jul 15 06:35:40 PM PDT 24
Finished Jul 15 06:35:47 PM PDT 24
Peak memory 207500 kb
Host smart-c7e12732-a817-493f-8129-07009687f0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877833991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2877833991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.3083922921
Short name T467
Test name
Test status
Simulation time 29627418 ps
CPU time 1.2 seconds
Started Jul 15 06:35:41 PM PDT 24
Finished Jul 15 06:35:42 PM PDT 24
Peak memory 215476 kb
Host smart-34e0c736-d6af-41ad-ae48-b012bb2d31f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083922921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3083922921 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.4283052473
Short name T409
Test name
Test status
Simulation time 758723872851 ps
CPU time 2131.1 seconds
Started Jul 15 06:35:28 PM PDT 24
Finished Jul 15 07:10:59 PM PDT 24
Peak memory 415936 kb
Host smart-235bd0f1-6218-4120-95f3-8fede711dde4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283052473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.4283052473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.1099468310
Short name T191
Test name
Test status
Simulation time 3977723620 ps
CPU time 150.84 seconds
Started Jul 15 06:35:28 PM PDT 24
Finished Jul 15 06:37:59 PM PDT 24
Peak memory 233760 kb
Host smart-082fd591-9e28-4e7f-9d26-a6f14fc08daf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099468310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1099468310 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.241563356
Short name T831
Test name
Test status
Simulation time 2198464240 ps
CPU time 9.77 seconds
Started Jul 15 06:35:28 PM PDT 24
Finished Jul 15 06:35:38 PM PDT 24
Peak memory 215892 kb
Host smart-0d46340e-9722-4fef-8594-fd9fec1f42cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241563356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.241563356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.2775788240
Short name T905
Test name
Test status
Simulation time 1539027805 ps
CPU time 82.62 seconds
Started Jul 15 06:35:42 PM PDT 24
Finished Jul 15 06:37:05 PM PDT 24
Peak memory 250372 kb
Host smart-8264f18a-2fce-4ba5-9c9f-1f75a136db7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2775788240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2775788240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.902796166
Short name T898
Test name
Test status
Simulation time 244049160 ps
CPU time 4.27 seconds
Started Jul 15 06:35:33 PM PDT 24
Finished Jul 15 06:35:37 PM PDT 24
Peak memory 215648 kb
Host smart-ddb62596-ca03-47a7-8c2f-27a3194032db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902796166 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.kmac_test_vectors_kmac.902796166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.3285879276
Short name T1015
Test name
Test status
Simulation time 121378028 ps
CPU time 4.02 seconds
Started Jul 15 06:35:34 PM PDT 24
Finished Jul 15 06:35:38 PM PDT 24
Peak memory 215616 kb
Host smart-4b36c480-2954-41e8-bebb-b629cc15d2b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285879276 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.3285879276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.3281895681
Short name T555
Test name
Test status
Simulation time 391475652448 ps
CPU time 1963.88 seconds
Started Jul 15 06:35:27 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 395140 kb
Host smart-8b20834c-d96b-448b-9e6f-3f78ea976882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3281895681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3281895681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.14445456
Short name T642
Test name
Test status
Simulation time 253685624570 ps
CPU time 1850.51 seconds
Started Jul 15 06:35:29 PM PDT 24
Finished Jul 15 07:06:20 PM PDT 24
Peak memory 372676 kb
Host smart-010aa111-b5ac-478f-9a13-dc4838a611a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=14445456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.14445456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.3221189450
Short name T428
Test name
Test status
Simulation time 13736378992 ps
CPU time 1098.35 seconds
Started Jul 15 06:35:32 PM PDT 24
Finished Jul 15 06:53:50 PM PDT 24
Peak memory 337232 kb
Host smart-4a2ad9a4-3261-460d-861f-1aa49a4002d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3221189450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3221189450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.1387213332
Short name T556
Test name
Test status
Simulation time 38580067212 ps
CPU time 755.16 seconds
Started Jul 15 06:35:34 PM PDT 24
Finished Jul 15 06:48:09 PM PDT 24
Peak memory 290536 kb
Host smart-fbff73f5-e36a-488b-9d52-293c5eb2242b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1387213332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.1387213332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.2855830712
Short name T532
Test name
Test status
Simulation time 1753033551989 ps
CPU time 5391.82 seconds
Started Jul 15 06:35:33 PM PDT 24
Finished Jul 15 08:05:25 PM PDT 24
Peak memory 668568 kb
Host smart-404c3152-424b-4d22-ac0a-8955b1a4ff3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2855830712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2855830712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.2592224439
Short name T981
Test name
Test status
Simulation time 145713628275 ps
CPU time 3763.6 seconds
Started Jul 15 06:35:35 PM PDT 24
Finished Jul 15 07:38:19 PM PDT 24
Peak memory 563600 kb
Host smart-0d9024d2-b5f4-44d9-91e3-5d20eb1fe8af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2592224439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2592224439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1684315118
Short name T1026
Test name
Test status
Simulation time 18848358 ps
CPU time 0.8 seconds
Started Jul 15 06:35:51 PM PDT 24
Finished Jul 15 06:35:53 PM PDT 24
Peak memory 205236 kb
Host smart-d48e3a8b-95c1-4d5f-ac53-3d9c73551dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684315118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1684315118 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.3246792480
Short name T110
Test name
Test status
Simulation time 6126498481 ps
CPU time 133.41 seconds
Started Jul 15 06:35:52 PM PDT 24
Finished Jul 15 06:38:06 PM PDT 24
Peak memory 232304 kb
Host smart-ac593f2c-fcf0-417e-9bdf-aa6beb322ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246792480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3246792480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.2944056180
Short name T43
Test name
Test status
Simulation time 34133852351 ps
CPU time 429.98 seconds
Started Jul 15 06:35:44 PM PDT 24
Finished Jul 15 06:42:55 PM PDT 24
Peak memory 236896 kb
Host smart-da7f040a-b964-4392-8bd0-4cedb894de4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944056180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2944056180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.1301015993
Short name T975
Test name
Test status
Simulation time 10118289499 ps
CPU time 75.13 seconds
Started Jul 15 06:35:51 PM PDT 24
Finished Jul 15 06:37:07 PM PDT 24
Peak memory 226400 kb
Host smart-8889509c-cad2-4e2f-ae2a-73985b31e96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301015993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1301015993 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.1398271204
Short name T812
Test name
Test status
Simulation time 8988597697 ps
CPU time 151.54 seconds
Started Jul 15 06:35:52 PM PDT 24
Finished Jul 15 06:38:24 PM PDT 24
Peak memory 248792 kb
Host smart-1c458e9c-4e4b-4bbe-bda3-4c0fce105195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398271204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1398271204 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.540623609
Short name T478
Test name
Test status
Simulation time 2106033699 ps
CPU time 5.89 seconds
Started Jul 15 06:35:51 PM PDT 24
Finished Jul 15 06:35:58 PM PDT 24
Peak memory 215456 kb
Host smart-5f161ef9-85e7-4b87-84c1-b348578b2c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540623609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.540623609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.818371135
Short name T824
Test name
Test status
Simulation time 30235275 ps
CPU time 1.24 seconds
Started Jul 15 06:35:51 PM PDT 24
Finished Jul 15 06:35:53 PM PDT 24
Peak memory 215556 kb
Host smart-461f783b-3347-4f8b-9e5e-c434f8728f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818371135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.818371135 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.1370856316
Short name T497
Test name
Test status
Simulation time 14970313138 ps
CPU time 411.14 seconds
Started Jul 15 06:35:43 PM PDT 24
Finished Jul 15 06:42:35 PM PDT 24
Peak memory 258452 kb
Host smart-68d77556-038d-43d4-be62-445937f5a60c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370856316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.1370856316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.2614530865
Short name T1059
Test name
Test status
Simulation time 39842611607 ps
CPU time 320.7 seconds
Started Jul 15 06:35:43 PM PDT 24
Finished Jul 15 06:41:04 PM PDT 24
Peak memory 246868 kb
Host smart-94825808-ec89-481b-be27-b4d8b0c57e39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614530865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2614530865 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3324267771
Short name T564
Test name
Test status
Simulation time 3304367932 ps
CPU time 52.39 seconds
Started Jul 15 06:35:44 PM PDT 24
Finished Jul 15 06:36:37 PM PDT 24
Peak memory 223824 kb
Host smart-81bd7c6c-f892-4ac4-ad38-46a827db4f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324267771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3324267771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.2613171460
Short name T336
Test name
Test status
Simulation time 514182065540 ps
CPU time 1287.05 seconds
Started Jul 15 06:35:52 PM PDT 24
Finished Jul 15 06:57:19 PM PDT 24
Peak memory 347412 kb
Host smart-42d67ffa-d110-441e-98c0-ba3243633530
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2613171460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2613171460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.2879922152
Short name T1052
Test name
Test status
Simulation time 66853941 ps
CPU time 3.98 seconds
Started Jul 15 06:35:44 PM PDT 24
Finished Jul 15 06:35:49 PM PDT 24
Peak memory 215592 kb
Host smart-f5ada0db-f454-4aa6-8c6c-48ac10da5483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879922152 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.2879922152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1009639331
Short name T916
Test name
Test status
Simulation time 1009828530 ps
CPU time 5.07 seconds
Started Jul 15 06:35:51 PM PDT 24
Finished Jul 15 06:35:57 PM PDT 24
Peak memory 215604 kb
Host smart-a843fb37-f69d-4690-98ec-3fad90ac34ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009639331 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1009639331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.2271049410
Short name T985
Test name
Test status
Simulation time 267448842784 ps
CPU time 1610.41 seconds
Started Jul 15 06:35:44 PM PDT 24
Finished Jul 15 07:02:35 PM PDT 24
Peak memory 390356 kb
Host smart-9d103faf-1946-40d1-aadf-12817e96ee99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2271049410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2271049410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.3794393599
Short name T1076
Test name
Test status
Simulation time 78993406612 ps
CPU time 1743.61 seconds
Started Jul 15 06:35:45 PM PDT 24
Finished Jul 15 07:04:49 PM PDT 24
Peak memory 372604 kb
Host smart-aeb9f771-0d14-4acc-821e-fefc886cf1a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3794393599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.3794393599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.3720377190
Short name T483
Test name
Test status
Simulation time 48853037398 ps
CPU time 1297.75 seconds
Started Jul 15 06:35:44 PM PDT 24
Finished Jul 15 06:57:23 PM PDT 24
Peak memory 336700 kb
Host smart-d1aacbae-e989-4329-98ee-8b6da37fda1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3720377190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3720377190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.1127166503
Short name T673
Test name
Test status
Simulation time 45202022497 ps
CPU time 867.85 seconds
Started Jul 15 06:35:44 PM PDT 24
Finished Jul 15 06:50:12 PM PDT 24
Peak memory 294880 kb
Host smart-501781d6-ecd8-4677-8cb7-77e361ae9373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1127166503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1127166503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.2079710852
Short name T691
Test name
Test status
Simulation time 213477226935 ps
CPU time 4081.15 seconds
Started Jul 15 06:35:44 PM PDT 24
Finished Jul 15 07:43:46 PM PDT 24
Peak memory 658384 kb
Host smart-6a7b74f3-1d67-4714-8512-fd13776fd169
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2079710852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2079710852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.3728603103
Short name T458
Test name
Test status
Simulation time 435195423314 ps
CPU time 4048.01 seconds
Started Jul 15 06:35:44 PM PDT 24
Finished Jul 15 07:43:13 PM PDT 24
Peak memory 564776 kb
Host smart-395a0a40-601f-4ea9-8f8e-84f0b452e1ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3728603103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3728603103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.3956397503
Short name T300
Test name
Test status
Simulation time 61540068 ps
CPU time 0.74 seconds
Started Jul 15 06:35:59 PM PDT 24
Finished Jul 15 06:36:00 PM PDT 24
Peak memory 205280 kb
Host smart-2f204ca3-bdde-46f8-b833-885546c3a7cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956397503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3956397503 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.2339634183
Short name T928
Test name
Test status
Simulation time 7088095421 ps
CPU time 149.71 seconds
Started Jul 15 06:36:00 PM PDT 24
Finished Jul 15 06:38:30 PM PDT 24
Peak memory 235752 kb
Host smart-4c91c01f-c49b-43d6-8dab-c5f1b7746c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339634183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2339634183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.3224819041
Short name T761
Test name
Test status
Simulation time 66414008949 ps
CPU time 849.4 seconds
Started Jul 15 06:35:56 PM PDT 24
Finished Jul 15 06:50:06 PM PDT 24
Peak memory 232736 kb
Host smart-0998b519-163c-4202-b575-9e48168b8f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224819041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3224819041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.2298583027
Short name T315
Test name
Test status
Simulation time 2658766128 ps
CPU time 71.26 seconds
Started Jul 15 06:36:00 PM PDT 24
Finished Jul 15 06:37:12 PM PDT 24
Peak memory 226060 kb
Host smart-bf34877f-8399-45ee-ae00-809ee51ae52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298583027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2298583027 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3551202100
Short name T674
Test name
Test status
Simulation time 3502295948 ps
CPU time 28.1 seconds
Started Jul 15 06:35:59 PM PDT 24
Finished Jul 15 06:36:28 PM PDT 24
Peak memory 231984 kb
Host smart-5595d77b-7e07-4d6d-bd0d-b8be18cf2825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551202100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3551202100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.640266022
Short name T525
Test name
Test status
Simulation time 2937491206 ps
CPU time 4.86 seconds
Started Jul 15 06:36:00 PM PDT 24
Finished Jul 15 06:36:05 PM PDT 24
Peak memory 207352 kb
Host smart-2c6a4398-c515-4baa-b338-d57df794c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640266022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.640266022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1269467968
Short name T59
Test name
Test status
Simulation time 29218868 ps
CPU time 1.23 seconds
Started Jul 15 06:36:01 PM PDT 24
Finished Jul 15 06:36:03 PM PDT 24
Peak memory 215532 kb
Host smart-b8c25605-7e0a-4d16-844a-0939563e05da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269467968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1269467968 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.2854213209
Short name T190
Test name
Test status
Simulation time 82523792047 ps
CPU time 1561.31 seconds
Started Jul 15 06:35:53 PM PDT 24
Finished Jul 15 07:01:55 PM PDT 24
Peak memory 415436 kb
Host smart-caa6c402-082f-412e-aed1-3a3776423f0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854213209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.2854213209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1280616946
Short name T337
Test name
Test status
Simulation time 70375723718 ps
CPU time 443.73 seconds
Started Jul 15 06:35:54 PM PDT 24
Finished Jul 15 06:43:18 PM PDT 24
Peak memory 248880 kb
Host smart-d76b78f9-3311-45d5-ba4f-bf291deedb9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280616946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1280616946 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3023257640
Short name T410
Test name
Test status
Simulation time 339211901 ps
CPU time 18.38 seconds
Started Jul 15 06:35:52 PM PDT 24
Finished Jul 15 06:36:11 PM PDT 24
Peak memory 219364 kb
Host smart-3698daae-925f-4a18-8cc9-06f4c01ef6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023257640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3023257640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.2976219053
Short name T282
Test name
Test status
Simulation time 4166351931 ps
CPU time 273.08 seconds
Started Jul 15 06:35:59 PM PDT 24
Finished Jul 15 06:40:33 PM PDT 24
Peak memory 289544 kb
Host smart-89705e8c-71d8-4bbf-9613-980f0b3b748f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2976219053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2976219053 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.1503953623
Short name T954
Test name
Test status
Simulation time 352369108 ps
CPU time 5.08 seconds
Started Jul 15 06:35:55 PM PDT 24
Finished Jul 15 06:36:00 PM PDT 24
Peak memory 215620 kb
Host smart-a684eb21-8e60-4e6f-8148-e04dcc4783dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503953623 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.1503953623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3232390987
Short name T636
Test name
Test status
Simulation time 380837163 ps
CPU time 4.8 seconds
Started Jul 15 06:35:54 PM PDT 24
Finished Jul 15 06:36:00 PM PDT 24
Peak memory 215668 kb
Host smart-8c71f4ef-7326-4576-be52-4de47f1bc9aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232390987 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3232390987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.1530503081
Short name T163
Test name
Test status
Simulation time 68327497657 ps
CPU time 1830.11 seconds
Started Jul 15 06:35:55 PM PDT 24
Finished Jul 15 07:06:26 PM PDT 24
Peak memory 396124 kb
Host smart-b4543118-671c-4017-b00e-30d9da926a8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1530503081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.1530503081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.3851210771
Short name T1006
Test name
Test status
Simulation time 100664672475 ps
CPU time 1450.51 seconds
Started Jul 15 06:35:56 PM PDT 24
Finished Jul 15 07:00:07 PM PDT 24
Peak memory 389216 kb
Host smart-41164749-1bf6-470d-8c71-f7edac2383f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3851210771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3851210771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.999179285
Short name T933
Test name
Test status
Simulation time 296546192453 ps
CPU time 1441.73 seconds
Started Jul 15 06:35:54 PM PDT 24
Finished Jul 15 06:59:56 PM PDT 24
Peak memory 341048 kb
Host smart-6119fbf7-ac5d-4e44-93b4-3b91a26cd476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=999179285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.999179285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.1647718633
Short name T77
Test name
Test status
Simulation time 33396442025 ps
CPU time 970.46 seconds
Started Jul 15 06:35:54 PM PDT 24
Finished Jul 15 06:52:05 PM PDT 24
Peak memory 295164 kb
Host smart-d3a8423f-2fc9-4d02-8cbe-69fc53cb530b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1647718633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.1647718633 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.1657978685
Short name T942
Test name
Test status
Simulation time 52679105170 ps
CPU time 4009.74 seconds
Started Jul 15 06:35:54 PM PDT 24
Finished Jul 15 07:42:44 PM PDT 24
Peak memory 645348 kb
Host smart-86970792-04a8-4145-90b9-59182c240b57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1657978685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1657978685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.1208942149
Short name T931
Test name
Test status
Simulation time 146051040839 ps
CPU time 3691.14 seconds
Started Jul 15 06:35:57 PM PDT 24
Finished Jul 15 07:37:29 PM PDT 24
Peak memory 564632 kb
Host smart-56f24c9d-8def-4955-91f3-dc90f8bc24ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1208942149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1208942149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.3764240457
Short name T703
Test name
Test status
Simulation time 55215829 ps
CPU time 0.76 seconds
Started Jul 15 06:36:18 PM PDT 24
Finished Jul 15 06:36:20 PM PDT 24
Peak memory 205220 kb
Host smart-5a5ec03f-830e-427b-9c04-72f219a7024b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764240457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3764240457 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.3121080902
Short name T843
Test name
Test status
Simulation time 13812908225 ps
CPU time 263.84 seconds
Started Jul 15 06:36:17 PM PDT 24
Finished Jul 15 06:40:42 PM PDT 24
Peak memory 242404 kb
Host smart-e788e6ad-111c-4440-8a40-8aa6a12fdc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121080902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3121080902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.2675750747
Short name T684
Test name
Test status
Simulation time 40603881011 ps
CPU time 794.83 seconds
Started Jul 15 06:36:05 PM PDT 24
Finished Jul 15 06:49:21 PM PDT 24
Peak memory 233160 kb
Host smart-029e55f2-1b1e-4772-a1ed-286d4170d10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675750747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2675750747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.3817279842
Short name T269
Test name
Test status
Simulation time 6635067095 ps
CPU time 190.42 seconds
Started Jul 15 06:36:17 PM PDT 24
Finished Jul 15 06:39:29 PM PDT 24
Peak memory 239796 kb
Host smart-975e3001-9b9b-40c0-8d20-36edd8134524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817279842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3817279842 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.3148994822
Short name T475
Test name
Test status
Simulation time 29763966814 ps
CPU time 283.49 seconds
Started Jul 15 06:36:17 PM PDT 24
Finished Jul 15 06:41:03 PM PDT 24
Peak memory 259192 kb
Host smart-b071070d-33f5-48f7-8e83-c629829ff7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148994822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3148994822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.1612614921
Short name T538
Test name
Test status
Simulation time 735268741 ps
CPU time 4.1 seconds
Started Jul 15 06:36:18 PM PDT 24
Finished Jul 15 06:36:23 PM PDT 24
Peak memory 215544 kb
Host smart-c2ce06b2-df25-41d8-bd93-8b1a01eaa8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612614921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1612614921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2550504166
Short name T94
Test name
Test status
Simulation time 151468467 ps
CPU time 1.34 seconds
Started Jul 15 06:36:18 PM PDT 24
Finished Jul 15 06:36:21 PM PDT 24
Peak memory 215532 kb
Host smart-1fc1f061-859e-43e5-8fd5-3879c28a7067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550504166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2550504166 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.732645467
Short name T80
Test name
Test status
Simulation time 98713336595 ps
CPU time 2361.67 seconds
Started Jul 15 06:36:05 PM PDT 24
Finished Jul 15 07:15:27 PM PDT 24
Peak memory 440612 kb
Host smart-7e6ec534-ee69-4ffe-a63c-94b42e29d021
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732645467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_an
d_output.732645467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.1300750935
Short name T866
Test name
Test status
Simulation time 1722128385 ps
CPU time 137.71 seconds
Started Jul 15 06:36:05 PM PDT 24
Finished Jul 15 06:38:23 PM PDT 24
Peak memory 231488 kb
Host smart-25c3b0ce-a69d-430a-9c5e-b9900954b248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300750935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1300750935 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.1217154872
Short name T405
Test name
Test status
Simulation time 503725774 ps
CPU time 9.36 seconds
Started Jul 15 06:36:01 PM PDT 24
Finished Jul 15 06:36:11 PM PDT 24
Peak memory 215608 kb
Host smart-6a77baff-5d96-4dc3-9403-7f7712b18faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217154872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1217154872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.3495760468
Short name T56
Test name
Test status
Simulation time 198742367304 ps
CPU time 1442.35 seconds
Started Jul 15 06:36:17 PM PDT 24
Finished Jul 15 07:00:20 PM PDT 24
Peak memory 412516 kb
Host smart-66b7736f-08ab-4948-b28d-ab90c72b09e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3495760468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3495760468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.1514782269
Short name T266
Test name
Test status
Simulation time 65727117 ps
CPU time 4.2 seconds
Started Jul 15 06:36:12 PM PDT 24
Finished Jul 15 06:36:16 PM PDT 24
Peak memory 215604 kb
Host smart-f38471f5-67e6-445c-827c-531eedf3569f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514782269 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.1514782269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.1274787656
Short name T373
Test name
Test status
Simulation time 176281051 ps
CPU time 4.55 seconds
Started Jul 15 06:36:16 PM PDT 24
Finished Jul 15 06:36:21 PM PDT 24
Peak memory 215596 kb
Host smart-aeb9ad32-fbf3-4ca5-a0ea-78d25d896bdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274787656 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.1274787656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.1949034584
Short name T561
Test name
Test status
Simulation time 19348193368 ps
CPU time 1587.59 seconds
Started Jul 15 06:36:04 PM PDT 24
Finished Jul 15 07:02:32 PM PDT 24
Peak memory 386948 kb
Host smart-92640425-b304-4b1b-83e1-0b6e6be77550
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1949034584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.1949034584 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.3171148092
Short name T637
Test name
Test status
Simulation time 248958541330 ps
CPU time 1739.49 seconds
Started Jul 15 06:36:05 PM PDT 24
Finished Jul 15 07:05:05 PM PDT 24
Peak memory 366240 kb
Host smart-3c067cb9-c709-4302-9792-d3e7f7af03b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3171148092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.3171148092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.800866867
Short name T451
Test name
Test status
Simulation time 67939296756 ps
CPU time 1405 seconds
Started Jul 15 06:36:05 PM PDT 24
Finished Jul 15 06:59:30 PM PDT 24
Peak memory 325740 kb
Host smart-820fe6b1-94ed-4c96-b712-c50df733979b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=800866867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.800866867 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.712464952
Short name T355
Test name
Test status
Simulation time 214132906722 ps
CPU time 958.68 seconds
Started Jul 15 06:36:05 PM PDT 24
Finished Jul 15 06:52:04 PM PDT 24
Peak memory 292192 kb
Host smart-eac74cf0-e215-45f7-903f-725d5bbe095a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=712464952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.712464952 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.2731423068
Short name T799
Test name
Test status
Simulation time 381479712620 ps
CPU time 4667.22 seconds
Started Jul 15 06:36:04 PM PDT 24
Finished Jul 15 07:53:52 PM PDT 24
Peak memory 643288 kb
Host smart-069cc0fa-8cee-4db4-9a2b-53aada9adb74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2731423068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.2731423068 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.4109079946
Short name T759
Test name
Test status
Simulation time 291615180274 ps
CPU time 3923.97 seconds
Started Jul 15 06:36:11 PM PDT 24
Finished Jul 15 07:41:36 PM PDT 24
Peak memory 547372 kb
Host smart-8bf1f1b2-b591-464c-9c88-fab0b61f86c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4109079946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.4109079946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.595312063
Short name T251
Test name
Test status
Simulation time 12324264 ps
CPU time 0.74 seconds
Started Jul 15 06:36:33 PM PDT 24
Finished Jul 15 06:36:34 PM PDT 24
Peak memory 205280 kb
Host smart-bab28778-c9dc-4597-ba4c-2695f8da18fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595312063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.595312063 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.186681399
Short name T923
Test name
Test status
Simulation time 5465691169 ps
CPU time 74.77 seconds
Started Jul 15 06:36:28 PM PDT 24
Finished Jul 15 06:37:43 PM PDT 24
Peak memory 228420 kb
Host smart-d7a42d57-dd76-4a24-b013-524fcd686944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186681399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.186681399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.3697613990
Short name T727
Test name
Test status
Simulation time 86066895584 ps
CPU time 640.28 seconds
Started Jul 15 06:36:20 PM PDT 24
Finished Jul 15 06:47:01 PM PDT 24
Peak memory 231924 kb
Host smart-dec899fd-c3d9-4a2b-b9a1-036d41a61922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697613990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3697613990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.2097748192
Short name T154
Test name
Test status
Simulation time 12677563351 ps
CPU time 256.21 seconds
Started Jul 15 06:36:28 PM PDT 24
Finished Jul 15 06:40:45 PM PDT 24
Peak memory 246044 kb
Host smart-1543c69b-0823-443f-8704-bd8ffb4546db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097748192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2097748192 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.2918837054
Short name T86
Test name
Test status
Simulation time 2453347323 ps
CPU time 119.57 seconds
Started Jul 15 06:36:29 PM PDT 24
Finished Jul 15 06:38:29 PM PDT 24
Peak memory 240252 kb
Host smart-94b6be75-b470-439c-b06e-afc94594fcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918837054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2918837054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.3155063788
Short name T479
Test name
Test status
Simulation time 776432839 ps
CPU time 4.71 seconds
Started Jul 15 06:36:28 PM PDT 24
Finished Jul 15 06:36:33 PM PDT 24
Peak memory 207280 kb
Host smart-7a16fbf1-a17e-4a8d-9fb5-be835d6c00de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155063788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3155063788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.1962503238
Short name T60
Test name
Test status
Simulation time 59006781 ps
CPU time 1.52 seconds
Started Jul 15 06:36:34 PM PDT 24
Finished Jul 15 06:36:36 PM PDT 24
Peak memory 215488 kb
Host smart-077c4694-11f4-4de6-b988-fab639fb1ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962503238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1962503238 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1845318771
Short name T377
Test name
Test status
Simulation time 1032103312666 ps
CPU time 1522.62 seconds
Started Jul 15 06:36:18 PM PDT 24
Finished Jul 15 07:01:42 PM PDT 24
Peak memory 355880 kb
Host smart-31a871e5-70c4-417e-8bd8-bc00b1d2b856
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845318771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1845318771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.1653303460
Short name T952
Test name
Test status
Simulation time 23593855494 ps
CPU time 337.47 seconds
Started Jul 15 06:36:19 PM PDT 24
Finished Jul 15 06:41:58 PM PDT 24
Peak memory 245244 kb
Host smart-eba70727-4473-41e0-a6fc-3227bee2027c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653303460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1653303460 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.1971923751
Short name T1050
Test name
Test status
Simulation time 2099417392 ps
CPU time 51.36 seconds
Started Jul 15 06:36:20 PM PDT 24
Finished Jul 15 06:37:12 PM PDT 24
Peak memory 216644 kb
Host smart-f379b8fc-5e30-4463-a48d-77e831b2ecf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971923751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1971923751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.1401172033
Short name T524
Test name
Test status
Simulation time 12189860460 ps
CPU time 222.43 seconds
Started Jul 15 06:36:34 PM PDT 24
Finished Jul 15 06:40:17 PM PDT 24
Peak memory 266792 kb
Host smart-b4280dcc-544c-4a6d-acca-4da7a88d1f16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1401172033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1401172033 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.2849161991
Short name T1021
Test name
Test status
Simulation time 3902937782 ps
CPU time 5.64 seconds
Started Jul 15 06:36:28 PM PDT 24
Finished Jul 15 06:36:34 PM PDT 24
Peak memory 215680 kb
Host smart-1ffe9675-4015-40d7-a4f4-e463c60e5af9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849161991 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.2849161991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.3815445566
Short name T72
Test name
Test status
Simulation time 363544506 ps
CPU time 4.59 seconds
Started Jul 15 06:36:26 PM PDT 24
Finished Jul 15 06:36:31 PM PDT 24
Peak memory 215652 kb
Host smart-1de8e889-4689-4b3f-89ba-4a0e6d5cfba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815445566 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.3815445566 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.3638152265
Short name T895
Test name
Test status
Simulation time 37277475682 ps
CPU time 1538.18 seconds
Started Jul 15 06:36:20 PM PDT 24
Finished Jul 15 07:01:59 PM PDT 24
Peak memory 387960 kb
Host smart-7247fad7-1509-4c29-ac27-bb3a6422d736
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3638152265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.3638152265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.3471110922
Short name T457
Test name
Test status
Simulation time 17599450547 ps
CPU time 1469.06 seconds
Started Jul 15 06:36:19 PM PDT 24
Finished Jul 15 07:00:49 PM PDT 24
Peak memory 370588 kb
Host smart-de220169-e442-4a00-88ef-c9245b39b57a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3471110922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3471110922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.3168413738
Short name T510
Test name
Test status
Simulation time 72212606577 ps
CPU time 1473.43 seconds
Started Jul 15 06:36:22 PM PDT 24
Finished Jul 15 07:00:56 PM PDT 24
Peak memory 339948 kb
Host smart-e84202c1-d04e-442b-84a6-a70725e8753e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3168413738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3168413738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.3581261606
Short name T917
Test name
Test status
Simulation time 32886993183 ps
CPU time 932.58 seconds
Started Jul 15 06:36:20 PM PDT 24
Finished Jul 15 06:51:54 PM PDT 24
Peak memory 296064 kb
Host smart-1ced7a6c-4f7d-446b-9328-b7c9fd2d3880
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3581261606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.3581261606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.3000359371
Short name T241
Test name
Test status
Simulation time 53367191741 ps
CPU time 4108.73 seconds
Started Jul 15 06:36:24 PM PDT 24
Finished Jul 15 07:44:53 PM PDT 24
Peak memory 656936 kb
Host smart-ea364526-7c6d-41e0-af9c-dff0741028c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3000359371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.3000359371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.3157818615
Short name T280
Test name
Test status
Simulation time 180574458049 ps
CPU time 3473.92 seconds
Started Jul 15 06:36:27 PM PDT 24
Finished Jul 15 07:34:22 PM PDT 24
Peak memory 562016 kb
Host smart-1b3fdb68-fea8-4568-a643-ffed2582c77a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3157818615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.3157818615 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.1316869426
Short name T805
Test name
Test status
Simulation time 43115806 ps
CPU time 0.8 seconds
Started Jul 15 06:32:50 PM PDT 24
Finished Jul 15 06:32:52 PM PDT 24
Peak memory 205300 kb
Host smart-43812c79-0b90-4d7f-be92-43698b1532b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316869426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1316869426 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.4184143417
Short name T1018
Test name
Test status
Simulation time 24756302206 ps
CPU time 153.91 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 06:35:18 PM PDT 24
Peak memory 233964 kb
Host smart-bffeda4e-f472-4b3b-9432-8a3276923a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184143417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.4184143417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.1759740435
Short name T449
Test name
Test status
Simulation time 16318310120 ps
CPU time 291.74 seconds
Started Jul 15 06:32:43 PM PDT 24
Finished Jul 15 06:37:37 PM PDT 24
Peak memory 245532 kb
Host smart-ac9fc07e-3b1d-4318-bdee-e4c883cbe73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759740435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1759740435 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.3891589618
Short name T361
Test name
Test status
Simulation time 28119977001 ps
CPU time 599.88 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 06:42:44 PM PDT 24
Peak memory 230220 kb
Host smart-4056bd2b-11e5-4dd1-866d-eab6fb842c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891589618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3891589618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.1581084851
Short name T783
Test name
Test status
Simulation time 6067478504 ps
CPU time 33.57 seconds
Started Jul 15 06:32:44 PM PDT 24
Finished Jul 15 06:33:19 PM PDT 24
Peak memory 223704 kb
Host smart-a53d1bbe-992f-419f-a712-0acb4628bd7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1581084851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1581084851 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.116544382
Short name T384
Test name
Test status
Simulation time 1192523319 ps
CPU time 30.62 seconds
Started Jul 15 06:32:46 PM PDT 24
Finished Jul 15 06:33:19 PM PDT 24
Peak memory 223676 kb
Host smart-9f3139ac-e3c7-43d2-afb7-7cf994e0515d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=116544382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.116544382 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.2782736197
Short name T829
Test name
Test status
Simulation time 5972431404 ps
CPU time 16.73 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 06:33:09 PM PDT 24
Peak memory 216468 kb
Host smart-572dd061-8e9d-401c-a226-12279d0b9974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782736197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2782736197 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.3702121458
Short name T569
Test name
Test status
Simulation time 6923926023 ps
CPU time 142.64 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 06:35:06 PM PDT 24
Peak memory 233596 kb
Host smart-c8370113-e44e-4fff-8539-cbbc90da1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702121458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3702121458 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_key_error.868771318
Short name T583
Test name
Test status
Simulation time 2594353568 ps
CPU time 4.87 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 06:32:49 PM PDT 24
Peak memory 207400 kb
Host smart-92d34edc-ff1b-4541-a605-f6d2998c11bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868771318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.868771318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.960126521
Short name T62
Test name
Test status
Simulation time 37724714 ps
CPU time 1.19 seconds
Started Jul 15 06:32:52 PM PDT 24
Finished Jul 15 06:32:54 PM PDT 24
Peak memory 215544 kb
Host smart-eee45f2f-13cf-477b-ae4f-00d319e2b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960126521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.960126521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.4134381269
Short name T560
Test name
Test status
Simulation time 21536254022 ps
CPU time 511.49 seconds
Started Jul 15 06:32:41 PM PDT 24
Finished Jul 15 06:41:15 PM PDT 24
Peak memory 268472 kb
Host smart-d0e9adeb-d97e-432b-a390-c17f7a8f16b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134381269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.4134381269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.4196361857
Short name T666
Test name
Test status
Simulation time 8078160021 ps
CPU time 150.56 seconds
Started Jul 15 06:32:41 PM PDT 24
Finished Jul 15 06:35:13 PM PDT 24
Peak memory 235548 kb
Host smart-9857dc4e-fa8b-4e1b-8e63-7264e8f001d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196361857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.4196361857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sideload.2359214794
Short name T260
Test name
Test status
Simulation time 25405545509 ps
CPU time 260.18 seconds
Started Jul 15 06:32:43 PM PDT 24
Finished Jul 15 06:37:05 PM PDT 24
Peak memory 238408 kb
Host smart-498a71fa-493f-4a9d-9850-ab64242e3c75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359214794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2359214794 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.2262602963
Short name T17
Test name
Test status
Simulation time 1254674930 ps
CPU time 10.81 seconds
Started Jul 15 06:32:43 PM PDT 24
Finished Jul 15 06:32:56 PM PDT 24
Peak memory 216952 kb
Host smart-16a3311f-f02c-4206-a90b-5342f833db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262602963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2262602963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.3902854480
Short name T136
Test name
Test status
Simulation time 27379976751 ps
CPU time 742.92 seconds
Started Jul 15 06:32:48 PM PDT 24
Finished Jul 15 06:45:13 PM PDT 24
Peak memory 302032 kb
Host smart-8160b9cd-2085-4887-b5c4-8289fbd9cbf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3902854480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3902854480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.1511807285
Short name T735
Test name
Test status
Simulation time 492159443 ps
CPU time 5.61 seconds
Started Jul 15 06:32:40 PM PDT 24
Finished Jul 15 06:32:47 PM PDT 24
Peak memory 215676 kb
Host smart-0cfaeb34-af01-4089-ab34-f7233ebb2610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511807285 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.1511807285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.4272947422
Short name T785
Test name
Test status
Simulation time 64806822 ps
CPU time 3.52 seconds
Started Jul 15 06:32:41 PM PDT 24
Finished Jul 15 06:32:47 PM PDT 24
Peak memory 215604 kb
Host smart-0863e2cf-786a-47e1-8687-5e2f143bbaec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272947422 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.4272947422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.1049506346
Short name T416
Test name
Test status
Simulation time 19310135905 ps
CPU time 1659.19 seconds
Started Jul 15 06:32:43 PM PDT 24
Finished Jul 15 07:00:24 PM PDT 24
Peak memory 402112 kb
Host smart-a70ba323-bc5c-482c-a3c9-23e3a548091d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1049506346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1049506346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1638130597
Short name T290
Test name
Test status
Simulation time 18932749587 ps
CPU time 1431.16 seconds
Started Jul 15 06:32:43 PM PDT 24
Finished Jul 15 06:56:36 PM PDT 24
Peak memory 389848 kb
Host smart-d0f4393b-9d46-4daf-927d-0f5ce1888d48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1638130597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1638130597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3501569611
Short name T306
Test name
Test status
Simulation time 14162399767 ps
CPU time 1198.54 seconds
Started Jul 15 06:32:42 PM PDT 24
Finished Jul 15 06:52:43 PM PDT 24
Peak memory 342652 kb
Host smart-5f2a61a9-6582-446d-a20e-fd04a965c70d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3501569611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3501569611 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.105356479
Short name T340
Test name
Test status
Simulation time 41037949810 ps
CPU time 787.26 seconds
Started Jul 15 06:32:44 PM PDT 24
Finished Jul 15 06:45:54 PM PDT 24
Peak memory 301988 kb
Host smart-7ff308ea-2e2a-46f8-923c-c151f4887bd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=105356479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.105356479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.3904563037
Short name T951
Test name
Test status
Simulation time 746527941959 ps
CPU time 4897.01 seconds
Started Jul 15 06:32:45 PM PDT 24
Finished Jul 15 07:54:25 PM PDT 24
Peak memory 639416 kb
Host smart-e60b3579-356c-4051-9f85-08b5984d39e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3904563037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3904563037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2032927108
Short name T1003
Test name
Test status
Simulation time 41132284 ps
CPU time 0.76 seconds
Started Jul 15 06:36:50 PM PDT 24
Finished Jul 15 06:36:51 PM PDT 24
Peak memory 205248 kb
Host smart-c16d9bf1-c744-4159-96c8-b5a6d6721849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032927108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2032927108 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.1483316491
Short name T196
Test name
Test status
Simulation time 1654675174 ps
CPU time 15.51 seconds
Started Jul 15 06:36:43 PM PDT 24
Finished Jul 15 06:36:59 PM PDT 24
Peak memory 217036 kb
Host smart-5420698b-78cb-45e1-8da4-fa6c8adb8fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483316491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1483316491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.3421471778
Short name T171
Test name
Test status
Simulation time 30965652663 ps
CPU time 612.59 seconds
Started Jul 15 06:36:32 PM PDT 24
Finished Jul 15 06:46:45 PM PDT 24
Peak memory 238892 kb
Host smart-5ab23cee-73f4-4383-8645-32366175ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421471778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3421471778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.564177487
Short name T906
Test name
Test status
Simulation time 7496167223 ps
CPU time 147.24 seconds
Started Jul 15 06:36:44 PM PDT 24
Finished Jul 15 06:39:12 PM PDT 24
Peak memory 236724 kb
Host smart-d7b812b7-9d6a-477a-8c73-d9e9afaf9b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564177487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.564177487 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.3955863268
Short name T529
Test name
Test status
Simulation time 3646320858 ps
CPU time 289.24 seconds
Started Jul 15 06:36:43 PM PDT 24
Finished Jul 15 06:41:32 PM PDT 24
Peak memory 256564 kb
Host smart-09fad868-7cf2-45ac-9985-4071a6841b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955863268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3955863268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.855649831
Short name T67
Test name
Test status
Simulation time 3944467768 ps
CPU time 5.16 seconds
Started Jul 15 06:36:43 PM PDT 24
Finished Jul 15 06:36:49 PM PDT 24
Peak memory 215580 kb
Host smart-0056ff4b-588b-42f1-9a26-5fa97b5591ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855649831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.855649831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.851115002
Short name T890
Test name
Test status
Simulation time 422818032 ps
CPU time 1.24 seconds
Started Jul 15 06:36:44 PM PDT 24
Finished Jul 15 06:36:46 PM PDT 24
Peak memory 215516 kb
Host smart-d323399c-cb09-4aff-9627-387eb901ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851115002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.851115002 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.3023504806
Short name T1029
Test name
Test status
Simulation time 110991481897 ps
CPU time 652.77 seconds
Started Jul 15 06:36:32 PM PDT 24
Finished Jul 15 06:47:25 PM PDT 24
Peak memory 275112 kb
Host smart-b90585ee-e603-4c36-aedc-42ec6809279d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023504806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.3023504806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.476216994
Short name T366
Test name
Test status
Simulation time 12147239873 ps
CPU time 81.59 seconds
Started Jul 15 06:36:33 PM PDT 24
Finished Jul 15 06:37:55 PM PDT 24
Peak memory 224992 kb
Host smart-b76c4ab7-cd8e-4e51-9c46-942da5aebd72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476216994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.476216994 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.422098942
Short name T594
Test name
Test status
Simulation time 478619075 ps
CPU time 7.44 seconds
Started Jul 15 06:36:32 PM PDT 24
Finished Jul 15 06:36:39 PM PDT 24
Peak memory 223828 kb
Host smart-781eac5b-6357-499a-a977-bf0d98facc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422098942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.422098942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.2871504054
Short name T970
Test name
Test status
Simulation time 34721953018 ps
CPU time 625.06 seconds
Started Jul 15 06:36:49 PM PDT 24
Finished Jul 15 06:47:14 PM PDT 24
Peak memory 315336 kb
Host smart-a2e034dc-807e-4e13-93d7-4ee936853d90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2871504054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2871504054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.3998087837
Short name T543
Test name
Test status
Simulation time 762084702 ps
CPU time 4.89 seconds
Started Jul 15 06:36:37 PM PDT 24
Finished Jul 15 06:36:42 PM PDT 24
Peak memory 215676 kb
Host smart-80bfe1a8-3ed6-485f-9126-651ad7f11101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998087837 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.3998087837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.703722295
Short name T671
Test name
Test status
Simulation time 174705512 ps
CPU time 4.29 seconds
Started Jul 15 06:36:38 PM PDT 24
Finished Jul 15 06:36:42 PM PDT 24
Peak memory 215620 kb
Host smart-23684179-d3a5-40df-acda-5cb4bbc4eeb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703722295 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.kmac_test_vectors_kmac_xof.703722295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.2201754203
Short name T263
Test name
Test status
Simulation time 71383775448 ps
CPU time 1548.43 seconds
Started Jul 15 06:36:34 PM PDT 24
Finished Jul 15 07:02:23 PM PDT 24
Peak memory 387128 kb
Host smart-c50e50eb-867c-4c06-82fb-289a8ed4617b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2201754203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2201754203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.1225377986
Short name T402
Test name
Test status
Simulation time 243749014587 ps
CPU time 1597.05 seconds
Started Jul 15 06:36:37 PM PDT 24
Finished Jul 15 07:03:15 PM PDT 24
Peak memory 373540 kb
Host smart-a77beaba-70a0-4aac-b9ce-bf307e897bbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1225377986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.1225377986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.2629626506
Short name T726
Test name
Test status
Simulation time 47145733514 ps
CPU time 1250.65 seconds
Started Jul 15 06:36:39 PM PDT 24
Finished Jul 15 06:57:31 PM PDT 24
Peak memory 327328 kb
Host smart-dad8f16b-863d-46ce-a63c-0fa87deda36a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2629626506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2629626506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.1163790106
Short name T649
Test name
Test status
Simulation time 32872015524 ps
CPU time 977.02 seconds
Started Jul 15 06:36:38 PM PDT 24
Finished Jul 15 06:52:55 PM PDT 24
Peak memory 296300 kb
Host smart-d1c70a3b-a1ab-446d-b767-60f8f4ab11a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1163790106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.1163790106 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.2610642712
Short name T657
Test name
Test status
Simulation time 682672364107 ps
CPU time 4536.32 seconds
Started Jul 15 06:36:39 PM PDT 24
Finished Jul 15 07:52:17 PM PDT 24
Peak memory 641976 kb
Host smart-7e69ae99-deb1-435a-9b42-3ad6bafd534a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2610642712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.2610642712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.2425222376
Short name T367
Test name
Test status
Simulation time 439606134129 ps
CPU time 4176.27 seconds
Started Jul 15 06:36:37 PM PDT 24
Finished Jul 15 07:46:15 PM PDT 24
Peak memory 555820 kb
Host smart-a1256f5c-1170-48ab-b5e5-4fc503bbe537
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2425222376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.2425222376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.1567034169
Short name T638
Test name
Test status
Simulation time 36551080 ps
CPU time 0.77 seconds
Started Jul 15 06:37:06 PM PDT 24
Finished Jul 15 06:37:07 PM PDT 24
Peak memory 205276 kb
Host smart-480b30b9-4807-4aa3-a430-f648940bd249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567034169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1567034169 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3121089885
Short name T749
Test name
Test status
Simulation time 7827840114 ps
CPU time 86.76 seconds
Started Jul 15 06:36:59 PM PDT 24
Finished Jul 15 06:38:26 PM PDT 24
Peak memory 228460 kb
Host smart-db526a30-059c-4f4a-a43d-fa784c715552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121089885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3121089885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.3978160743
Short name T549
Test name
Test status
Simulation time 97814318346 ps
CPU time 550.82 seconds
Started Jul 15 06:36:49 PM PDT 24
Finished Jul 15 06:46:01 PM PDT 24
Peak memory 230092 kb
Host smart-744c49f0-f87c-429f-9e80-3228d31bdeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978160743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.3978160743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2512862554
Short name T469
Test name
Test status
Simulation time 3315307076 ps
CPU time 20.3 seconds
Started Jul 15 06:37:01 PM PDT 24
Finished Jul 15 06:37:21 PM PDT 24
Peak memory 218128 kb
Host smart-5f8275d7-f600-4238-b98f-82c85d494792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512862554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2512862554 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.2406407652
Short name T956
Test name
Test status
Simulation time 18600203869 ps
CPU time 192.71 seconds
Started Jul 15 06:37:00 PM PDT 24
Finished Jul 15 06:40:13 PM PDT 24
Peak memory 248456 kb
Host smart-8a79e68f-5314-44e7-8738-0cc44d0c2477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406407652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2406407652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1312446259
Short name T352
Test name
Test status
Simulation time 2243527321 ps
CPU time 5.98 seconds
Started Jul 15 06:37:08 PM PDT 24
Finished Jul 15 06:37:15 PM PDT 24
Peak memory 215616 kb
Host smart-ba9e1223-12b4-45ba-9e93-a7cef276968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312446259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1312446259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.1338308137
Short name T880
Test name
Test status
Simulation time 35546023 ps
CPU time 1.27 seconds
Started Jul 15 06:37:07 PM PDT 24
Finished Jul 15 06:37:09 PM PDT 24
Peak memory 215496 kb
Host smart-0c14caf8-9e7a-4145-bbc9-0b4dc6096e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338308137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1338308137 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.1974468425
Short name T466
Test name
Test status
Simulation time 7052646879 ps
CPU time 137.57 seconds
Started Jul 15 06:36:49 PM PDT 24
Finished Jul 15 06:39:07 PM PDT 24
Peak memory 232488 kb
Host smart-1cd05594-1e11-4a85-b8ec-3a1004940726
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974468425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.1974468425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1206609225
Short name T681
Test name
Test status
Simulation time 12246331976 ps
CPU time 120.07 seconds
Started Jul 15 06:36:49 PM PDT 24
Finished Jul 15 06:38:49 PM PDT 24
Peak memory 228928 kb
Host smart-72560dac-5bac-472c-af3d-058921015f61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206609225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1206609225 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.4034041760
Short name T914
Test name
Test status
Simulation time 488943330 ps
CPU time 6.82 seconds
Started Jul 15 06:36:50 PM PDT 24
Finished Jul 15 06:36:57 PM PDT 24
Peak memory 218628 kb
Host smart-e32b66b9-e5cf-484e-a766-395114a9ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034041760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.4034041760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.1122467954
Short name T708
Test name
Test status
Simulation time 32665764965 ps
CPU time 403.72 seconds
Started Jul 15 06:37:06 PM PDT 24
Finished Jul 15 06:43:50 PM PDT 24
Peak memory 296876 kb
Host smart-494da172-90ad-49ae-81be-a2753152e7e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1122467954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1122467954 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.3403018736
Short name T772
Test name
Test status
Simulation time 491011282 ps
CPU time 5.64 seconds
Started Jul 15 06:36:55 PM PDT 24
Finished Jul 15 06:37:01 PM PDT 24
Peak memory 215616 kb
Host smart-0a636e6b-cff6-4099-b710-ffccbf36bcce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403018736 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.3403018736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.2637186709
Short name T1014
Test name
Test status
Simulation time 64114364 ps
CPU time 3.75 seconds
Started Jul 15 06:37:01 PM PDT 24
Finished Jul 15 06:37:05 PM PDT 24
Peak memory 215592 kb
Host smart-a8d4f8a4-68c2-4a75-8d6b-7e1f5fb17cc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637186709 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.2637186709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.3484805079
Short name T884
Test name
Test status
Simulation time 1372167757615 ps
CPU time 1941.04 seconds
Started Jul 15 06:36:49 PM PDT 24
Finished Jul 15 07:09:11 PM PDT 24
Peak memory 388180 kb
Host smart-d968f1d2-ef4b-4416-9839-2d0fa13c435e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3484805079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3484805079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.218271868
Short name T231
Test name
Test status
Simulation time 78291312676 ps
CPU time 1654.85 seconds
Started Jul 15 06:36:56 PM PDT 24
Finished Jul 15 07:04:32 PM PDT 24
Peak memory 363940 kb
Host smart-bb4c1bdb-7271-4eb4-80a5-1ce3ee0b020a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=218271868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.218271868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.2847668503
Short name T233
Test name
Test status
Simulation time 96964731677 ps
CPU time 1295.33 seconds
Started Jul 15 06:36:54 PM PDT 24
Finished Jul 15 06:58:30 PM PDT 24
Peak memory 333012 kb
Host smart-0bd26507-c91e-4bc6-8963-b5021dec4318
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2847668503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2847668503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1702072816
Short name T437
Test name
Test status
Simulation time 50815332788 ps
CPU time 962.76 seconds
Started Jul 15 06:36:55 PM PDT 24
Finished Jul 15 06:52:58 PM PDT 24
Peak memory 294792 kb
Host smart-b4badca1-19b4-4aa3-a667-ac8b9ad19edb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1702072816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1702072816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.3711591506
Short name T204
Test name
Test status
Simulation time 852897694231 ps
CPU time 5398.6 seconds
Started Jul 15 06:36:55 PM PDT 24
Finished Jul 15 08:06:55 PM PDT 24
Peak memory 648128 kb
Host smart-dc78740c-477c-4cba-aeae-20b4544e13c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3711591506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.3711591506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.873110638
Short name T533
Test name
Test status
Simulation time 597754869110 ps
CPU time 3855.74 seconds
Started Jul 15 06:36:56 PM PDT 24
Finished Jul 15 07:41:13 PM PDT 24
Peak memory 550624 kb
Host smart-d3e856b0-c26d-4822-8999-12466e4e37f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=873110638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.873110638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.3115247641
Short name T338
Test name
Test status
Simulation time 22680045 ps
CPU time 0.85 seconds
Started Jul 15 06:37:19 PM PDT 24
Finished Jul 15 06:37:20 PM PDT 24
Peak memory 205308 kb
Host smart-98a7d491-fae0-49e4-be17-d499804ea046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115247641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3115247641 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.4216353356
Short name T734
Test name
Test status
Simulation time 2775049352 ps
CPU time 64.09 seconds
Started Jul 15 06:37:18 PM PDT 24
Finished Jul 15 06:38:22 PM PDT 24
Peak memory 226188 kb
Host smart-2a317d4c-8ad7-4d6e-bb57-771da715d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216353356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.4216353356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.522626769
Short name T670
Test name
Test status
Simulation time 6239981212 ps
CPU time 561.18 seconds
Started Jul 15 06:37:13 PM PDT 24
Finished Jul 15 06:46:35 PM PDT 24
Peak memory 231500 kb
Host smart-3bc08143-929a-4403-bc21-0c662e1f5bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522626769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.522626769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.316545317
Short name T463
Test name
Test status
Simulation time 10323926816 ps
CPU time 221.16 seconds
Started Jul 15 06:37:16 PM PDT 24
Finished Jul 15 06:40:57 PM PDT 24
Peak memory 239688 kb
Host smart-9a106639-957e-43d7-bd67-dd944c4be144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316545317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.316545317 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.3160005692
Short name T904
Test name
Test status
Simulation time 40634134042 ps
CPU time 340.65 seconds
Started Jul 15 06:37:16 PM PDT 24
Finished Jul 15 06:42:57 PM PDT 24
Peak memory 264820 kb
Host smart-93b8090b-d2f0-4d12-9c94-f4217d705324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160005692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3160005692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2507860782
Short name T450
Test name
Test status
Simulation time 2607620025 ps
CPU time 7 seconds
Started Jul 15 06:37:16 PM PDT 24
Finished Jul 15 06:37:24 PM PDT 24
Peak memory 207380 kb
Host smart-4de79f57-6ab8-4afc-98e3-327ed6cff92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507860782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2507860782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2080877313
Short name T531
Test name
Test status
Simulation time 91747515 ps
CPU time 1.37 seconds
Started Jul 15 06:37:18 PM PDT 24
Finished Jul 15 06:37:19 PM PDT 24
Peak memory 216952 kb
Host smart-fbb76647-2109-4213-ba47-0c0cd87e3245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080877313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2080877313 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.470153976
Short name T519
Test name
Test status
Simulation time 273748966003 ps
CPU time 1661.03 seconds
Started Jul 15 06:37:12 PM PDT 24
Finished Jul 15 07:04:54 PM PDT 24
Peak memory 365008 kb
Host smart-e61a8d59-7838-4863-ab99-d49a2cf75e1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470153976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_an
d_output.470153976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.3341171296
Short name T132
Test name
Test status
Simulation time 4129785462 ps
CPU time 156.64 seconds
Started Jul 15 06:37:12 PM PDT 24
Finished Jul 15 06:39:49 PM PDT 24
Peak memory 234352 kb
Host smart-5fd4ac71-2afd-401c-9b74-adbd3e596357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341171296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3341171296 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.3667982892
Short name T213
Test name
Test status
Simulation time 1466538114 ps
CPU time 28.55 seconds
Started Jul 15 06:37:12 PM PDT 24
Finished Jul 15 06:37:41 PM PDT 24
Peak memory 218660 kb
Host smart-933f7de1-eb23-4355-ac77-6f8f971ca7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667982892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3667982892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.188935076
Short name T651
Test name
Test status
Simulation time 41604603647 ps
CPU time 987.92 seconds
Started Jul 15 06:37:19 PM PDT 24
Finished Jul 15 06:53:48 PM PDT 24
Peak memory 314008 kb
Host smart-4caa0813-6105-437d-8f46-2a6b6ad0c835
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=188935076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.188935076 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.1783655186
Short name T369
Test name
Test status
Simulation time 243337124 ps
CPU time 4.22 seconds
Started Jul 15 06:37:14 PM PDT 24
Finished Jul 15 06:37:19 PM PDT 24
Peak memory 215636 kb
Host smart-fcc3c3b0-6b89-4a9b-801c-58e28a9edcd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783655186 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.1783655186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.655698224
Short name T844
Test name
Test status
Simulation time 66583262 ps
CPU time 3.74 seconds
Started Jul 15 06:37:17 PM PDT 24
Finished Jul 15 06:37:21 PM PDT 24
Peak memory 215612 kb
Host smart-8a476d2c-c37a-4096-a3e7-6a340b40df38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655698224 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.kmac_test_vectors_kmac_xof.655698224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3855780021
Short name T589
Test name
Test status
Simulation time 75678947745 ps
CPU time 1552.91 seconds
Started Jul 15 06:37:12 PM PDT 24
Finished Jul 15 07:03:06 PM PDT 24
Peak memory 393636 kb
Host smart-1bec893a-a8a1-4bcd-97e1-a0b597f696ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3855780021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3855780021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.1450912037
Short name T997
Test name
Test status
Simulation time 90097239783 ps
CPU time 1639.21 seconds
Started Jul 15 06:37:14 PM PDT 24
Finished Jul 15 07:04:34 PM PDT 24
Peak memory 369164 kb
Host smart-90248e94-789a-44ab-a83b-fedad53e7d96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1450912037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.1450912037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.3013192225
Short name T514
Test name
Test status
Simulation time 13947433369 ps
CPU time 1035.57 seconds
Started Jul 15 06:37:12 PM PDT 24
Finished Jul 15 06:54:29 PM PDT 24
Peak memory 329732 kb
Host smart-01350809-490b-4e95-81ef-c798ab81a98f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3013192225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3013192225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.2726432313
Short name T676
Test name
Test status
Simulation time 66543978172 ps
CPU time 703.78 seconds
Started Jul 15 06:37:12 PM PDT 24
Finished Jul 15 06:48:57 PM PDT 24
Peak memory 291020 kb
Host smart-bd1fc9ed-1a33-4302-9de7-8abeeec30008
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2726432313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.2726432313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.1077219907
Short name T764
Test name
Test status
Simulation time 538164444590 ps
CPU time 5296.19 seconds
Started Jul 15 06:37:13 PM PDT 24
Finished Jul 15 08:05:30 PM PDT 24
Peak memory 656232 kb
Host smart-b43d5180-0e11-4a7c-9f16-04b945867def
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1077219907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.1077219907 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.3817769991
Short name T293
Test name
Test status
Simulation time 180393826493 ps
CPU time 3464.52 seconds
Started Jul 15 06:37:12 PM PDT 24
Finished Jul 15 07:34:57 PM PDT 24
Peak memory 561488 kb
Host smart-f59ddcf0-a78f-4a8b-9e0e-bf3cff2d4b2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3817769991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.3817769991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.3177873440
Short name T983
Test name
Test status
Simulation time 16351601 ps
CPU time 0.74 seconds
Started Jul 15 06:37:33 PM PDT 24
Finished Jul 15 06:37:34 PM PDT 24
Peak memory 205216 kb
Host smart-a569a088-3134-415e-9b10-f1710c1374c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177873440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3177873440 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.2414051468
Short name T677
Test name
Test status
Simulation time 60529805193 ps
CPU time 243.26 seconds
Started Jul 15 06:37:33 PM PDT 24
Finished Jul 15 06:41:36 PM PDT 24
Peak memory 242060 kb
Host smart-68fcd3d9-d2a8-499b-bbfd-e1cb5a6ec9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414051468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2414051468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.304623781
Short name T976
Test name
Test status
Simulation time 23693570923 ps
CPU time 522.77 seconds
Started Jul 15 06:37:29 PM PDT 24
Finished Jul 15 06:46:12 PM PDT 24
Peak memory 231132 kb
Host smart-b0ccea6d-da89-4475-a7ea-dac07411dedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304623781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.304623781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.2223526767
Short name T699
Test name
Test status
Simulation time 32229323144 ps
CPU time 283.21 seconds
Started Jul 15 06:37:32 PM PDT 24
Finished Jul 15 06:42:16 PM PDT 24
Peak memory 246120 kb
Host smart-ce0bec98-ee11-42a6-ae69-29e09c0fb72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223526767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2223526767 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.2046739461
Short name T87
Test name
Test status
Simulation time 5482683362 ps
CPU time 37.99 seconds
Started Jul 15 06:37:34 PM PDT 24
Finished Jul 15 06:38:13 PM PDT 24
Peak memory 232040 kb
Host smart-c972bddd-bd9b-4966-be02-55e4ad43f2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046739461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2046739461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.449088693
Short name T631
Test name
Test status
Simulation time 7332821038 ps
CPU time 9.41 seconds
Started Jul 15 06:37:33 PM PDT 24
Finished Jul 15 06:37:43 PM PDT 24
Peak memory 207368 kb
Host smart-9840ec1a-7f02-47cb-91af-7426ee189a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449088693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.449088693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.3178054470
Short name T958
Test name
Test status
Simulation time 127837796 ps
CPU time 3.03 seconds
Started Jul 15 06:37:34 PM PDT 24
Finished Jul 15 06:37:37 PM PDT 24
Peak memory 217656 kb
Host smart-928d2be5-c669-4be2-9c3c-3bdcd5455cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178054470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3178054470 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.2263269989
Short name T860
Test name
Test status
Simulation time 173144049888 ps
CPU time 805.49 seconds
Started Jul 15 06:37:23 PM PDT 24
Finished Jul 15 06:50:49 PM PDT 24
Peak memory 290544 kb
Host smart-56fa1e3b-7dd0-4ffe-a9aa-4eab66c0c01e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263269989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.2263269989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.2568706964
Short name T37
Test name
Test status
Simulation time 4565954503 ps
CPU time 69.26 seconds
Started Jul 15 06:37:29 PM PDT 24
Finished Jul 15 06:38:39 PM PDT 24
Peak memory 223808 kb
Host smart-bbd0ccbd-6b1d-4a10-9b01-b9bcc01135aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568706964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2568706964 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.2183619834
Short name T627
Test name
Test status
Simulation time 202818636 ps
CPU time 11.17 seconds
Started Jul 15 06:37:16 PM PDT 24
Finished Jul 15 06:37:27 PM PDT 24
Peak memory 223792 kb
Host smart-ec492f87-96ca-44bb-82d0-7333a3faf045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183619834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2183619834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3709881240
Short name T663
Test name
Test status
Simulation time 170893519484 ps
CPU time 912.25 seconds
Started Jul 15 06:37:33 PM PDT 24
Finished Jul 15 06:52:46 PM PDT 24
Peak memory 346908 kb
Host smart-40fabee1-5691-498d-a870-80f0c723ed6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3709881240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3709881240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.1559537911
Short name T1061
Test name
Test status
Simulation time 73218038 ps
CPU time 3.93 seconds
Started Jul 15 06:37:29 PM PDT 24
Finished Jul 15 06:37:33 PM PDT 24
Peak memory 215596 kb
Host smart-78ac5a87-9d91-4ae9-a4de-1c08d434e484
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559537911 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.1559537911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.493691252
Short name T849
Test name
Test status
Simulation time 131911318 ps
CPU time 3.93 seconds
Started Jul 15 06:37:27 PM PDT 24
Finished Jul 15 06:37:31 PM PDT 24
Peak memory 215688 kb
Host smart-e15daf2e-6403-458c-a268-9a8f637f54d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493691252 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.kmac_test_vectors_kmac_xof.493691252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.3424910948
Short name T872
Test name
Test status
Simulation time 821340396698 ps
CPU time 2145.5 seconds
Started Jul 15 06:37:29 PM PDT 24
Finished Jul 15 07:13:15 PM PDT 24
Peak memory 396952 kb
Host smart-ac5f774d-b238-42fb-afe3-0ec2e3fe4a37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3424910948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3424910948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.4208277311
Short name T498
Test name
Test status
Simulation time 17930489709 ps
CPU time 1591.56 seconds
Started Jul 15 06:37:22 PM PDT 24
Finished Jul 15 07:03:54 PM PDT 24
Peak memory 373680 kb
Host smart-a88ec3a7-5d09-413b-a689-63a1dafcb6e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4208277311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.4208277311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.957771759
Short name T427
Test name
Test status
Simulation time 152829896260 ps
CPU time 1180.8 seconds
Started Jul 15 06:37:23 PM PDT 24
Finished Jul 15 06:57:04 PM PDT 24
Peak memory 337576 kb
Host smart-2c0bdbea-ac1f-4024-97c8-f0dc2072bb65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=957771759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.957771759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.3586589607
Short name T186
Test name
Test status
Simulation time 187158321351 ps
CPU time 980.86 seconds
Started Jul 15 06:37:22 PM PDT 24
Finished Jul 15 06:53:44 PM PDT 24
Peak memory 294640 kb
Host smart-7d74783e-eda4-42fb-ae9c-2aeeeaf6bc7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3586589607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3586589607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.3553240922
Short name T1025
Test name
Test status
Simulation time 172068335513 ps
CPU time 4547.64 seconds
Started Jul 15 06:37:29 PM PDT 24
Finished Jul 15 07:53:18 PM PDT 24
Peak memory 650320 kb
Host smart-8e40d12d-ed78-47d3-9645-d7c962d0b6e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3553240922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3553240922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.3044416422
Short name T345
Test name
Test status
Simulation time 177170936180 ps
CPU time 3266.06 seconds
Started Jul 15 06:37:28 PM PDT 24
Finished Jul 15 07:31:55 PM PDT 24
Peak memory 545144 kb
Host smart-373fa99d-407a-4b64-9bcc-e74087847c77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3044416422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.3044416422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.2484131580
Short name T559
Test name
Test status
Simulation time 59623061 ps
CPU time 0.77 seconds
Started Jul 15 06:37:44 PM PDT 24
Finished Jul 15 06:37:45 PM PDT 24
Peak memory 205232 kb
Host smart-25798495-7d8f-4082-95da-4b70e0d3c697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484131580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2484131580 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.4267057244
Short name T853
Test name
Test status
Simulation time 7000928469 ps
CPU time 35.22 seconds
Started Jul 15 06:37:45 PM PDT 24
Finished Jul 15 06:38:20 PM PDT 24
Peak memory 223952 kb
Host smart-bf18d56e-b31c-4a0f-a988-b1b14811e36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267057244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.4267057244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.2325785383
Short name T966
Test name
Test status
Simulation time 7344009582 ps
CPU time 114.72 seconds
Started Jul 15 06:37:44 PM PDT 24
Finished Jul 15 06:39:39 PM PDT 24
Peak memory 232004 kb
Host smart-34a0ef05-31d1-48e2-a11e-df16604de51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325785383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2325785383 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.4250679683
Short name T245
Test name
Test status
Simulation time 3107417969 ps
CPU time 239.07 seconds
Started Jul 15 06:37:45 PM PDT 24
Finished Jul 15 06:41:45 PM PDT 24
Peak memory 256624 kb
Host smart-8163cbb3-f861-4e9b-a965-2d4655fce176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250679683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.4250679683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.1510497580
Short name T570
Test name
Test status
Simulation time 1719697166 ps
CPU time 9.17 seconds
Started Jul 15 06:37:44 PM PDT 24
Finished Jul 15 06:37:53 PM PDT 24
Peak memory 207304 kb
Host smart-a32899bd-da4c-4d56-bde7-d74770c6ae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510497580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1510497580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2970525444
Short name T596
Test name
Test status
Simulation time 42647298 ps
CPU time 1.37 seconds
Started Jul 15 06:37:45 PM PDT 24
Finished Jul 15 06:37:46 PM PDT 24
Peak memory 216996 kb
Host smart-b1cecadf-9dde-4e42-9711-bb7a05a9e424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970525444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2970525444 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.3439895325
Short name T2
Test name
Test status
Simulation time 76172453417 ps
CPU time 948.27 seconds
Started Jul 15 06:37:36 PM PDT 24
Finished Jul 15 06:53:25 PM PDT 24
Peak memory 313068 kb
Host smart-eddd5a06-7a8c-4e60-8fb2-ab4ab72e9e01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439895325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.3439895325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.136342314
Short name T343
Test name
Test status
Simulation time 14538603563 ps
CPU time 384.29 seconds
Started Jul 15 06:37:37 PM PDT 24
Finished Jul 15 06:44:02 PM PDT 24
Peak memory 247940 kb
Host smart-655a03ed-4816-4068-9ace-6d3ea1d5f27a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136342314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.136342314 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2126496387
Short name T551
Test name
Test status
Simulation time 1131141474 ps
CPU time 14.85 seconds
Started Jul 15 06:37:36 PM PDT 24
Finished Jul 15 06:37:51 PM PDT 24
Peak memory 217956 kb
Host smart-11c48a03-a65c-4570-b354-70132315132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126496387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2126496387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.3960295349
Short name T744
Test name
Test status
Simulation time 129094815 ps
CPU time 4.11 seconds
Started Jul 15 06:37:38 PM PDT 24
Finished Jul 15 06:37:42 PM PDT 24
Peak memory 215676 kb
Host smart-73bd584b-d9e7-4f1e-8c0a-3f3554897810
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960295349 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.3960295349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.3018709520
Short name T502
Test name
Test status
Simulation time 171513438 ps
CPU time 4.35 seconds
Started Jul 15 06:37:44 PM PDT 24
Finished Jul 15 06:37:49 PM PDT 24
Peak memory 215620 kb
Host smart-743f5587-ec70-4445-9383-44d2f0c8d922
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018709520 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.3018709520 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.2873898711
Short name T321
Test name
Test status
Simulation time 64008732616 ps
CPU time 1789.4 seconds
Started Jul 15 06:37:39 PM PDT 24
Finished Jul 15 07:07:28 PM PDT 24
Peak memory 387080 kb
Host smart-78b95100-d0b1-48ed-9e0d-40363d03454b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2873898711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2873898711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.437565806
Short name T215
Test name
Test status
Simulation time 91065041566 ps
CPU time 1722.89 seconds
Started Jul 15 06:37:37 PM PDT 24
Finished Jul 15 07:06:20 PM PDT 24
Peak memory 358804 kb
Host smart-a1fc9d8b-307d-488a-a10e-bfa9e28e7700
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=437565806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.437565806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.2349840899
Short name T859
Test name
Test status
Simulation time 54713130520 ps
CPU time 1185.92 seconds
Started Jul 15 06:37:39 PM PDT 24
Finished Jul 15 06:57:25 PM PDT 24
Peak memory 336012 kb
Host smart-d0651585-01aa-4c07-bc80-5d62c1e8439c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2349840899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.2349840899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.767650101
Short name T773
Test name
Test status
Simulation time 65985479463 ps
CPU time 910 seconds
Started Jul 15 06:37:38 PM PDT 24
Finished Jul 15 06:52:48 PM PDT 24
Peak memory 297060 kb
Host smart-11f19da6-9096-4724-8e87-b6bf0226dbd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=767650101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.767650101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.212296270
Short name T867
Test name
Test status
Simulation time 1713165515576 ps
CPU time 4726.24 seconds
Started Jul 15 06:37:38 PM PDT 24
Finished Jul 15 07:56:25 PM PDT 24
Peak memory 646372 kb
Host smart-f3cf942f-e0ab-4114-9a56-164c2e192b20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=212296270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.212296270 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.986659624
Short name T205
Test name
Test status
Simulation time 387237991476 ps
CPU time 3489.76 seconds
Started Jul 15 06:37:36 PM PDT 24
Finished Jul 15 07:35:47 PM PDT 24
Peak memory 547096 kb
Host smart-9ab1f210-49b7-48d7-9be4-6122a02f8536
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=986659624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.986659624 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.2902778511
Short name T586
Test name
Test status
Simulation time 37958897 ps
CPU time 0.77 seconds
Started Jul 15 06:37:58 PM PDT 24
Finished Jul 15 06:37:59 PM PDT 24
Peak memory 205308 kb
Host smart-db5d0bfe-d76e-4dcd-b26e-ef62e9c2be17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902778511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2902778511 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.2038092746
Short name T153
Test name
Test status
Simulation time 19003097752 ps
CPU time 239.52 seconds
Started Jul 15 06:37:57 PM PDT 24
Finished Jul 15 06:41:57 PM PDT 24
Peak memory 245460 kb
Host smart-0eb6b9ad-fd31-45d6-9f5b-a6567d179fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038092746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2038092746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3391691914
Short name T1012
Test name
Test status
Simulation time 3012659808 ps
CPU time 20.3 seconds
Started Jul 15 06:37:53 PM PDT 24
Finished Jul 15 06:38:14 PM PDT 24
Peak memory 223828 kb
Host smart-b6c71e66-4f72-4c9f-bb20-9e713424658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391691914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3391691914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.1524923797
Short name T820
Test name
Test status
Simulation time 3899193958 ps
CPU time 13.58 seconds
Started Jul 15 06:37:58 PM PDT 24
Finished Jul 15 06:38:12 PM PDT 24
Peak memory 215684 kb
Host smart-0ffa0799-4784-4d08-b585-bbeffffed052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524923797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1524923797 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.829030764
Short name T766
Test name
Test status
Simulation time 694894041 ps
CPU time 45.77 seconds
Started Jul 15 06:37:57 PM PDT 24
Finished Jul 15 06:38:43 PM PDT 24
Peak memory 231956 kb
Host smart-f92e068d-8bcc-4c15-a9e7-42a7126f61ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829030764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.829030764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.726047264
Short name T21
Test name
Test status
Simulation time 3654903642 ps
CPU time 6.19 seconds
Started Jul 15 06:37:58 PM PDT 24
Finished Jul 15 06:38:04 PM PDT 24
Peak memory 207476 kb
Host smart-10cd50a0-1947-499c-a681-865d82ce6a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726047264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.726047264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.2943118605
Short name T775
Test name
Test status
Simulation time 91345958 ps
CPU time 1.22 seconds
Started Jul 15 06:37:59 PM PDT 24
Finished Jul 15 06:38:00 PM PDT 24
Peak memory 215796 kb
Host smart-5d037ecf-de20-4f61-a93b-297024e6f5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943118605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2943118605 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.4239357864
Short name T901
Test name
Test status
Simulation time 63951894173 ps
CPU time 2247.54 seconds
Started Jul 15 06:37:43 PM PDT 24
Finished Jul 15 07:15:11 PM PDT 24
Peak memory 471344 kb
Host smart-6fad96d1-7581-4a3e-b980-e9dc8b7323f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239357864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.4239357864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.2039586548
Short name T731
Test name
Test status
Simulation time 16912281119 ps
CPU time 169.96 seconds
Started Jul 15 06:37:50 PM PDT 24
Finished Jul 15 06:40:40 PM PDT 24
Peak memory 233252 kb
Host smart-71cd2d25-30dc-49a6-a153-4b1afe52bde7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039586548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2039586548 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.2726049181
Short name T994
Test name
Test status
Simulation time 853337431 ps
CPU time 22.72 seconds
Started Jul 15 06:37:45 PM PDT 24
Finished Jul 15 06:38:08 PM PDT 24
Peak memory 216580 kb
Host smart-46193fbc-8300-4986-b0db-84342cc4b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726049181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2726049181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.444979152
Short name T1033
Test name
Test status
Simulation time 285758587363 ps
CPU time 545.73 seconds
Started Jul 15 06:37:58 PM PDT 24
Finished Jul 15 06:47:04 PM PDT 24
Peak memory 288392 kb
Host smart-33da8afd-eeea-488a-9f3e-e50e3c0f9f64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=444979152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.444979152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.3955495061
Short name T256
Test name
Test status
Simulation time 93691378 ps
CPU time 3.84 seconds
Started Jul 15 06:38:00 PM PDT 24
Finished Jul 15 06:38:04 PM PDT 24
Peak memory 215616 kb
Host smart-d896fad2-5e2f-405b-aa35-b669aa6e5bec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955495061 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.3955495061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.3338084193
Short name T511
Test name
Test status
Simulation time 70680467 ps
CPU time 4.09 seconds
Started Jul 15 06:37:57 PM PDT 24
Finished Jul 15 06:38:02 PM PDT 24
Peak memory 215624 kb
Host smart-5693141e-0972-4427-bea6-650409f6ee94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338084193 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.3338084193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.3630500125
Short name T1049
Test name
Test status
Simulation time 18671138359 ps
CPU time 1517.94 seconds
Started Jul 15 06:37:50 PM PDT 24
Finished Jul 15 07:03:08 PM PDT 24
Peak memory 370232 kb
Host smart-dfe5b0d9-da66-4e20-9c02-269e1175e524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3630500125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.3630500125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.1296599024
Short name T203
Test name
Test status
Simulation time 67433638175 ps
CPU time 1610.66 seconds
Started Jul 15 06:37:51 PM PDT 24
Finished Jul 15 07:04:42 PM PDT 24
Peak memory 391164 kb
Host smart-c516fe61-9806-4abc-a97e-5889c266c4a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1296599024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.1296599024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.1077470068
Short name T322
Test name
Test status
Simulation time 194315918704 ps
CPU time 1296.85 seconds
Started Jul 15 06:37:50 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 332512 kb
Host smart-570029d2-821d-46cb-a58b-efd210eea94e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1077470068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.1077470068 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2879484152
Short name T712
Test name
Test status
Simulation time 10697278430 ps
CPU time 753.72 seconds
Started Jul 15 06:37:51 PM PDT 24
Finished Jul 15 06:50:25 PM PDT 24
Peak memory 292848 kb
Host smart-b693b199-0fa4-4197-b067-46a78af0ed91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2879484152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2879484152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.2077979102
Short name T395
Test name
Test status
Simulation time 1099755006035 ps
CPU time 5077.77 seconds
Started Jul 15 06:37:49 PM PDT 24
Finished Jul 15 08:02:28 PM PDT 24
Peak memory 635600 kb
Host smart-67afe476-1ec6-4dea-85b3-8826fb139ff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2077979102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.2077979102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.194409896
Short name T85
Test name
Test status
Simulation time 1449698320256 ps
CPU time 4628.45 seconds
Started Jul 15 06:37:49 PM PDT 24
Finished Jul 15 07:54:59 PM PDT 24
Peak memory 563344 kb
Host smart-d761b496-394b-4a13-b40c-5a863a094478
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=194409896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.194409896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.4041686946
Short name T864
Test name
Test status
Simulation time 47981372 ps
CPU time 0.79 seconds
Started Jul 15 06:38:15 PM PDT 24
Finished Jul 15 06:38:16 PM PDT 24
Peak memory 205292 kb
Host smart-8d182386-ebd8-43a6-bde7-41f81e3c7378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041686946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.4041686946 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.3143451494
Short name T1036
Test name
Test status
Simulation time 8627830895 ps
CPU time 176.21 seconds
Started Jul 15 06:38:10 PM PDT 24
Finished Jul 15 06:41:07 PM PDT 24
Peak memory 237528 kb
Host smart-ae066b76-934b-4d3a-ab4b-c4dd3a990469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143451494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3143451494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3993248135
Short name T537
Test name
Test status
Simulation time 872622387 ps
CPU time 70.72 seconds
Started Jul 15 06:38:02 PM PDT 24
Finished Jul 15 06:39:13 PM PDT 24
Peak memory 219580 kb
Host smart-87249ac9-de9a-40a8-896c-fd71ee97e909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993248135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3993248135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.3436335402
Short name T986
Test name
Test status
Simulation time 23327202715 ps
CPU time 232.89 seconds
Started Jul 15 06:38:10 PM PDT 24
Finished Jul 15 06:42:03 PM PDT 24
Peak memory 239240 kb
Host smart-023dca75-bad5-4dc4-a001-41d3d08f28a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436335402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3436335402 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.2090213944
Short name T587
Test name
Test status
Simulation time 5443735431 ps
CPU time 117.32 seconds
Started Jul 15 06:38:09 PM PDT 24
Finished Jul 15 06:40:07 PM PDT 24
Peak memory 240244 kb
Host smart-02567a5b-4f9c-4c19-87aa-1af748752a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090213944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2090213944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.1566941190
Short name T499
Test name
Test status
Simulation time 16644979188 ps
CPU time 13.62 seconds
Started Jul 15 06:38:08 PM PDT 24
Finished Jul 15 06:38:22 PM PDT 24
Peak memory 207444 kb
Host smart-50cafeed-5508-41e9-93ef-7bc8594b90ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566941190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1566941190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.3097926486
Short name T9
Test name
Test status
Simulation time 765197393 ps
CPU time 13.2 seconds
Started Jul 15 06:38:15 PM PDT 24
Finished Jul 15 06:38:28 PM PDT 24
Peak memory 223760 kb
Host smart-f95c015d-4302-4b8c-a9b0-cb8ed844e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097926486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3097926486 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.4054847813
Short name T993
Test name
Test status
Simulation time 96221639055 ps
CPU time 2243.39 seconds
Started Jul 15 06:38:04 PM PDT 24
Finished Jul 15 07:15:28 PM PDT 24
Peak memory 439260 kb
Host smart-63cd7f86-caae-467c-9682-3b3269165df3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054847813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.4054847813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.2746833976
Short name T504
Test name
Test status
Simulation time 1388452675 ps
CPU time 107.25 seconds
Started Jul 15 06:38:05 PM PDT 24
Finished Jul 15 06:39:53 PM PDT 24
Peak memory 228408 kb
Host smart-0ce53946-946b-41d8-b8bb-78360be573e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746833976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2746833976 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.1126993791
Short name T429
Test name
Test status
Simulation time 641058832 ps
CPU time 11.58 seconds
Started Jul 15 06:37:56 PM PDT 24
Finished Jul 15 06:38:08 PM PDT 24
Peak memory 218288 kb
Host smart-c4b8d1db-72b2-4333-ae7d-9e1b0948bc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126993791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1126993791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.3953147006
Short name T816
Test name
Test status
Simulation time 20812663759 ps
CPU time 1145.03 seconds
Started Jul 15 06:38:15 PM PDT 24
Finished Jul 15 06:57:21 PM PDT 24
Peak memory 338776 kb
Host smart-e14c15a7-ee0e-4222-822f-5afbaeb06e16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3953147006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3953147006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.3575832103
Short name T990
Test name
Test status
Simulation time 610319783 ps
CPU time 4.64 seconds
Started Jul 15 06:38:10 PM PDT 24
Finished Jul 15 06:38:15 PM PDT 24
Peak memory 215636 kb
Host smart-7985c2aa-4dfa-4a2a-b93f-d97c1dae04df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575832103 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.3575832103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.629390804
Short name T407
Test name
Test status
Simulation time 133485693 ps
CPU time 4.3 seconds
Started Jul 15 06:38:10 PM PDT 24
Finished Jul 15 06:38:15 PM PDT 24
Peak memory 215584 kb
Host smart-ef416e11-35e0-4915-8f35-e9ee441e4590
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629390804 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.kmac_test_vectors_kmac_xof.629390804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.2042893251
Short name T1010
Test name
Test status
Simulation time 129859778203 ps
CPU time 1806.39 seconds
Started Jul 15 06:38:02 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 392412 kb
Host smart-c751ce62-8458-415d-ab13-d34674f2f413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2042893251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2042893251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.613787645
Short name T590
Test name
Test status
Simulation time 326643975743 ps
CPU time 1678.86 seconds
Started Jul 15 06:38:03 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 370264 kb
Host smart-3d6cc78c-3f54-4b30-8424-df241aa49e5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=613787645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.613787645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.4198795744
Short name T472
Test name
Test status
Simulation time 13751801735 ps
CPU time 1088.22 seconds
Started Jul 15 06:38:05 PM PDT 24
Finished Jul 15 06:56:14 PM PDT 24
Peak memory 334348 kb
Host smart-9e37c5c6-ce6c-4711-a58f-0290d615181f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4198795744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.4198795744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.1658992101
Short name T218
Test name
Test status
Simulation time 67867115505 ps
CPU time 919.05 seconds
Started Jul 15 06:38:03 PM PDT 24
Finished Jul 15 06:53:23 PM PDT 24
Peak memory 294812 kb
Host smart-ea60de06-ba2a-447f-a412-275ac2e25fe3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1658992101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1658992101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.4121573229
Short name T794
Test name
Test status
Simulation time 105564016285 ps
CPU time 4137.95 seconds
Started Jul 15 06:38:05 PM PDT 24
Finished Jul 15 07:47:04 PM PDT 24
Peak memory 646240 kb
Host smart-d42bb231-2d07-460f-869c-9e9bd6e51f05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4121573229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.4121573229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.1589484426
Short name T422
Test name
Test status
Simulation time 87227158722 ps
CPU time 3408.5 seconds
Started Jul 15 06:38:10 PM PDT 24
Finished Jul 15 07:34:59 PM PDT 24
Peak memory 550124 kb
Host smart-81dd55b4-993c-4a63-a0f6-f18682d18df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1589484426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.1589484426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1281970997
Short name T948
Test name
Test status
Simulation time 62150430 ps
CPU time 0.81 seconds
Started Jul 15 06:38:33 PM PDT 24
Finished Jul 15 06:38:34 PM PDT 24
Peak memory 205276 kb
Host smart-1cb92a1f-b530-4657-8eef-110895833c67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281970997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1281970997 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.2320186675
Short name T292
Test name
Test status
Simulation time 7728395887 ps
CPU time 144.86 seconds
Started Jul 15 06:38:26 PM PDT 24
Finished Jul 15 06:40:51 PM PDT 24
Peak memory 233012 kb
Host smart-c198b8fb-873b-4ce6-9e4f-d56abeb42ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320186675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2320186675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.2961519577
Short name T81
Test name
Test status
Simulation time 12120070071 ps
CPU time 89.3 seconds
Started Jul 15 06:38:18 PM PDT 24
Finished Jul 15 06:39:48 PM PDT 24
Peak memory 223844 kb
Host smart-5a9f2d82-a558-4002-ae49-1e2270bd1105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961519577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.2961519577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.731349802
Short name T957
Test name
Test status
Simulation time 22799822893 ps
CPU time 313.7 seconds
Started Jul 15 06:38:24 PM PDT 24
Finished Jul 15 06:43:38 PM PDT 24
Peak memory 244372 kb
Host smart-e4a2f14c-5215-43ae-b2a0-870cf6f70293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731349802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.731349802 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.2724720601
Short name T869
Test name
Test status
Simulation time 5063034165 ps
CPU time 50.16 seconds
Started Jul 15 06:38:26 PM PDT 24
Finished Jul 15 06:39:17 PM PDT 24
Peak memory 232008 kb
Host smart-7f479f9f-86b4-4777-b78c-81153b5a3a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724720601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2724720601 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.1838110312
Short name T513
Test name
Test status
Simulation time 1464077899 ps
CPU time 8.23 seconds
Started Jul 15 06:38:24 PM PDT 24
Finished Jul 15 06:38:33 PM PDT 24
Peak memory 215512 kb
Host smart-73b7af37-9b13-4fa6-9341-0271f3b48481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838110312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1838110312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.3402722799
Short name T967
Test name
Test status
Simulation time 130551379 ps
CPU time 1.31 seconds
Started Jul 15 06:38:26 PM PDT 24
Finished Jul 15 06:38:28 PM PDT 24
Peak memory 215760 kb
Host smart-faac63f2-2b73-438c-a6bd-00c6c2e3d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402722799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3402722799 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.3424551043
Short name T319
Test name
Test status
Simulation time 53373425166 ps
CPU time 1142.19 seconds
Started Jul 15 06:38:13 PM PDT 24
Finished Jul 15 06:57:16 PM PDT 24
Peak memory 338828 kb
Host smart-0266fead-647f-40de-8555-ab8629897e0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424551043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.3424551043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.3574377873
Short name T473
Test name
Test status
Simulation time 53240842312 ps
CPU time 313.08 seconds
Started Jul 15 06:38:15 PM PDT 24
Finished Jul 15 06:43:28 PM PDT 24
Peak memory 242548 kb
Host smart-87a0d64e-f542-4474-a945-a232e10fa297
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574377873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3574377873 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.2285930564
Short name T668
Test name
Test status
Simulation time 1197613619 ps
CPU time 10.55 seconds
Started Jul 15 06:38:15 PM PDT 24
Finished Jul 15 06:38:26 PM PDT 24
Peak memory 221704 kb
Host smart-8215c7da-6541-4d68-8803-f1d73a76aa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285930564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2285930564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.1359649506
Short name T938
Test name
Test status
Simulation time 93629674010 ps
CPU time 1182.92 seconds
Started Jul 15 06:38:32 PM PDT 24
Finished Jul 15 06:58:15 PM PDT 24
Peak memory 347356 kb
Host smart-55e4ba69-5b1c-41fc-87b1-9ec8c63377b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1359649506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1359649506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.336810659
Short name T573
Test name
Test status
Simulation time 515990506 ps
CPU time 5.18 seconds
Started Jul 15 06:38:27 PM PDT 24
Finished Jul 15 06:38:32 PM PDT 24
Peak memory 215688 kb
Host smart-79de3e11-2ba2-4490-85dc-062017fe1623
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336810659 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.kmac_test_vectors_kmac.336810659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.144598805
Short name T350
Test name
Test status
Simulation time 177458601 ps
CPU time 4.58 seconds
Started Jul 15 06:38:25 PM PDT 24
Finished Jul 15 06:38:30 PM PDT 24
Peak memory 215636 kb
Host smart-0f5e7127-ab08-4e59-85d4-98b102b2d982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144598805 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.kmac_test_vectors_kmac_xof.144598805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2764400764
Short name T924
Test name
Test status
Simulation time 106047318023 ps
CPU time 1843.06 seconds
Started Jul 15 06:38:20 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 389284 kb
Host smart-ed57183d-753f-493d-8804-472e67ab7383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2764400764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2764400764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.2531231575
Short name T237
Test name
Test status
Simulation time 92467955979 ps
CPU time 1848.97 seconds
Started Jul 15 06:38:20 PM PDT 24
Finished Jul 15 07:09:10 PM PDT 24
Peak memory 373848 kb
Host smart-6979e291-988e-4ed9-b394-d6f6fb11826b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2531231575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2531231575 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.1326294255
Short name T545
Test name
Test status
Simulation time 26701533574 ps
CPU time 1081.5 seconds
Started Jul 15 06:38:20 PM PDT 24
Finished Jul 15 06:56:21 PM PDT 24
Peak memory 329064 kb
Host smart-371f38ed-4d0e-4dfe-8ad0-2f3d170499f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1326294255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.1326294255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.3121402928
Short name T415
Test name
Test status
Simulation time 40543067063 ps
CPU time 757.2 seconds
Started Jul 15 06:38:20 PM PDT 24
Finished Jul 15 06:50:58 PM PDT 24
Peak memory 299612 kb
Host smart-ecbac329-f8e9-48c3-a4d3-b98181b46252
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3121402928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3121402928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.1557082013
Short name T863
Test name
Test status
Simulation time 232512975437 ps
CPU time 4036.46 seconds
Started Jul 15 06:38:18 PM PDT 24
Finished Jul 15 07:45:35 PM PDT 24
Peak memory 656764 kb
Host smart-8e9eedec-664d-4d3e-9844-307d6df8107b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1557082013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.1557082013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.3060790856
Short name T249
Test name
Test status
Simulation time 686871410001 ps
CPU time 4271.76 seconds
Started Jul 15 06:38:21 PM PDT 24
Finished Jul 15 07:49:33 PM PDT 24
Peak memory 545588 kb
Host smart-dd38aada-7add-4ded-9373-f2712f891d44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3060790856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.3060790856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.570013375
Short name T254
Test name
Test status
Simulation time 16936142 ps
CPU time 0.78 seconds
Started Jul 15 06:38:42 PM PDT 24
Finished Jul 15 06:38:43 PM PDT 24
Peak memory 205272 kb
Host smart-c9e3c027-e244-4dc7-9a67-edb762489fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570013375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.570013375 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_burst_write.545911915
Short name T419
Test name
Test status
Simulation time 50351407472 ps
CPU time 237.87 seconds
Started Jul 15 06:38:30 PM PDT 24
Finished Jul 15 06:42:28 PM PDT 24
Peak memory 225308 kb
Host smart-45256561-de10-406d-93af-7043098bcda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545911915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.545911915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.2125479929
Short name T888
Test name
Test status
Simulation time 5134191413 ps
CPU time 95.56 seconds
Started Jul 15 06:38:37 PM PDT 24
Finished Jul 15 06:40:13 PM PDT 24
Peak memory 229468 kb
Host smart-1e25fcd4-43f9-4998-9549-f7dde2a255db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125479929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2125479929 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.2298470555
Short name T277
Test name
Test status
Simulation time 14075982207 ps
CPU time 278.1 seconds
Started Jul 15 06:38:39 PM PDT 24
Finished Jul 15 06:43:18 PM PDT 24
Peak memory 249824 kb
Host smart-641b0ccb-31eb-42f4-95dc-38d17727e581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298470555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2298470555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.1863400023
Short name T456
Test name
Test status
Simulation time 881664075 ps
CPU time 5.19 seconds
Started Jul 15 06:38:39 PM PDT 24
Finished Jul 15 06:38:45 PM PDT 24
Peak memory 215492 kb
Host smart-199879b8-22b9-4237-af54-78d96ac6a3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863400023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1863400023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.607611424
Short name T588
Test name
Test status
Simulation time 744331609 ps
CPU time 1.36 seconds
Started Jul 15 06:38:37 PM PDT 24
Finished Jul 15 06:38:39 PM PDT 24
Peak memory 215584 kb
Host smart-00d2af5e-8b72-494c-a809-8f859777a46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607611424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.607611424 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.4090683819
Short name T874
Test name
Test status
Simulation time 27284975427 ps
CPU time 603.3 seconds
Started Jul 15 06:38:31 PM PDT 24
Finished Jul 15 06:48:35 PM PDT 24
Peak memory 271020 kb
Host smart-aa8d03a0-dc76-49cd-8a9d-80f71be712a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090683819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.4090683819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.2095062847
Short name T1066
Test name
Test status
Simulation time 4024372459 ps
CPU time 273.48 seconds
Started Jul 15 06:38:30 PM PDT 24
Finished Jul 15 06:43:04 PM PDT 24
Peak memory 242240 kb
Host smart-40ee47de-fbda-4ac8-b18e-a03edfecf8b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095062847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2095062847 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.2955357048
Short name T989
Test name
Test status
Simulation time 551092450 ps
CPU time 29.25 seconds
Started Jul 15 06:38:29 PM PDT 24
Finished Jul 15 06:38:59 PM PDT 24
Peak memory 219176 kb
Host smart-6c9882f0-aa29-4f54-8f45-9a232da05237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955357048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2955357048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.2844991242
Short name T44
Test name
Test status
Simulation time 10632237749 ps
CPU time 595.45 seconds
Started Jul 15 06:38:39 PM PDT 24
Finished Jul 15 06:48:36 PM PDT 24
Peak memory 312876 kb
Host smart-d4883672-14d9-4f07-a893-f8ff1abcf2cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2844991242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2844991242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.1531397352
Short name T261
Test name
Test status
Simulation time 246283559 ps
CPU time 4.02 seconds
Started Jul 15 06:38:37 PM PDT 24
Finished Jul 15 06:38:41 PM PDT 24
Peak memory 215748 kb
Host smart-321025f5-38b5-4f37-a71e-51e703e41345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531397352 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.1531397352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2443244675
Short name T270
Test name
Test status
Simulation time 172912930 ps
CPU time 4.84 seconds
Started Jul 15 06:38:37 PM PDT 24
Finished Jul 15 06:38:43 PM PDT 24
Peak memory 215628 kb
Host smart-07d8b3fe-1646-485e-a488-f59d98c869cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443244675 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2443244675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.4138824090
Short name T795
Test name
Test status
Simulation time 82711906929 ps
CPU time 1751.84 seconds
Started Jul 15 06:38:29 PM PDT 24
Finished Jul 15 07:07:42 PM PDT 24
Peak memory 377876 kb
Host smart-bd7234b3-352f-476d-99bd-a4f4df78af1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4138824090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.4138824090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.2528592760
Short name T453
Test name
Test status
Simulation time 70579120662 ps
CPU time 1443.34 seconds
Started Jul 15 06:38:36 PM PDT 24
Finished Jul 15 07:02:40 PM PDT 24
Peak memory 371884 kb
Host smart-3fc78037-8a78-4f46-a086-e27855ad7830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2528592760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.2528592760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.3142469579
Short name T698
Test name
Test status
Simulation time 143994052224 ps
CPU time 1376.04 seconds
Started Jul 15 06:38:37 PM PDT 24
Finished Jul 15 07:01:33 PM PDT 24
Peak memory 330612 kb
Host smart-015f7570-5cf4-45b7-87ba-2e56273af1d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3142469579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3142469579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.1264314377
Short name T214
Test name
Test status
Simulation time 48709505142 ps
CPU time 926.99 seconds
Started Jul 15 06:38:36 PM PDT 24
Finished Jul 15 06:54:04 PM PDT 24
Peak memory 294244 kb
Host smart-308c036c-3f83-4021-8cdb-365127e80c8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1264314377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.1264314377 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.3838766199
Short name T268
Test name
Test status
Simulation time 52807331750 ps
CPU time 3847.61 seconds
Started Jul 15 06:38:39 PM PDT 24
Finished Jul 15 07:42:48 PM PDT 24
Peak memory 660428 kb
Host smart-450ba3ae-5b71-4416-8a6d-53956afd3b65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3838766199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3838766199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.1865082215
Short name T238
Test name
Test status
Simulation time 301054557103 ps
CPU time 3838.54 seconds
Started Jul 15 06:38:38 PM PDT 24
Finished Jul 15 07:42:37 PM PDT 24
Peak memory 556756 kb
Host smart-7128627b-4827-45e5-bb4f-18f97b2e8d6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1865082215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1865082215 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.3447908322
Short name T1005
Test name
Test status
Simulation time 15590096 ps
CPU time 0.78 seconds
Started Jul 15 06:38:59 PM PDT 24
Finished Jul 15 06:39:00 PM PDT 24
Peak memory 205276 kb
Host smart-5ae4ed08-909c-49c9-ac4f-53255d9103a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447908322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3447908322 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3927214428
Short name T833
Test name
Test status
Simulation time 21520715915 ps
CPU time 212.96 seconds
Started Jul 15 06:38:53 PM PDT 24
Finished Jul 15 06:42:27 PM PDT 24
Peak memory 240004 kb
Host smart-812c83d6-a1ed-4e67-9c51-553252f5b5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927214428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3927214428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.2699120253
Short name T1079
Test name
Test status
Simulation time 85295190806 ps
CPU time 501.73 seconds
Started Jul 15 06:38:42 PM PDT 24
Finished Jul 15 06:47:05 PM PDT 24
Peak memory 230708 kb
Host smart-02c1e659-f3b8-42a2-bdde-99dd95733f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699120253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2699120253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.3988058772
Short name T742
Test name
Test status
Simulation time 21205663916 ps
CPU time 338.46 seconds
Started Jul 15 06:38:52 PM PDT 24
Finished Jul 15 06:44:30 PM PDT 24
Peak memory 245452 kb
Host smart-ccb5f840-015f-406d-bdcc-fef0a054a6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988058772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3988058772 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.338653570
Short name T295
Test name
Test status
Simulation time 12285034941 ps
CPU time 294.6 seconds
Started Jul 15 06:38:53 PM PDT 24
Finished Jul 15 06:43:48 PM PDT 24
Peak memory 253648 kb
Host smart-9aad2d87-b1e7-46dd-ad90-7d2a4659dca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338653570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.338653570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.753754190
Short name T973
Test name
Test status
Simulation time 4767247357 ps
CPU time 2.08 seconds
Started Jul 15 06:38:54 PM PDT 24
Finished Jul 15 06:38:57 PM PDT 24
Peak memory 207400 kb
Host smart-40d68536-eada-43c2-99f1-a74fc21ced27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753754190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.753754190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.4078485373
Short name T945
Test name
Test status
Simulation time 145295182 ps
CPU time 1.27 seconds
Started Jul 15 06:38:53 PM PDT 24
Finished Jul 15 06:38:54 PM PDT 24
Peak memory 215700 kb
Host smart-187ea0db-ef8a-4580-8d4f-f302a545e0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078485373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.4078485373 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.3096125061
Short name T623
Test name
Test status
Simulation time 354677386886 ps
CPU time 2636.74 seconds
Started Jul 15 06:38:42 PM PDT 24
Finished Jul 15 07:22:39 PM PDT 24
Peak memory 477836 kb
Host smart-a97ba897-2f67-4d03-ab78-8c66a9ab4a25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096125061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.3096125061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.493027142
Short name T639
Test name
Test status
Simulation time 2930565649 ps
CPU time 78.36 seconds
Started Jul 15 06:38:41 PM PDT 24
Finished Jul 15 06:40:00 PM PDT 24
Peak memory 225660 kb
Host smart-936f10f8-a773-4813-9272-7446c77194e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493027142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.493027142 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1101387816
Short name T207
Test name
Test status
Simulation time 3199173638 ps
CPU time 14.3 seconds
Started Jul 15 06:38:43 PM PDT 24
Finished Jul 15 06:38:58 PM PDT 24
Peak memory 215908 kb
Host smart-f19ee43b-a202-4be0-a086-dd0e49433975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101387816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1101387816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.882666919
Short name T380
Test name
Test status
Simulation time 37525239408 ps
CPU time 311.74 seconds
Started Jul 15 06:38:54 PM PDT 24
Finished Jul 15 06:44:06 PM PDT 24
Peak memory 272708 kb
Host smart-a4c77f41-629b-488d-a70c-ba569368bd69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=882666919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.882666919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.4286028499
Short name T658
Test name
Test status
Simulation time 214399792 ps
CPU time 4.85 seconds
Started Jul 15 06:38:46 PM PDT 24
Finished Jul 15 06:38:51 PM PDT 24
Peak memory 215712 kb
Host smart-176177b1-a9fd-4ee9-bee6-d4738fba6d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286028499 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.4286028499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.2117840572
Short name T386
Test name
Test status
Simulation time 314531974 ps
CPU time 4.26 seconds
Started Jul 15 06:38:48 PM PDT 24
Finished Jul 15 06:38:53 PM PDT 24
Peak memory 215616 kb
Host smart-e75f98ac-79cf-4100-9e0f-600cf3d88f3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117840572 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.2117840572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.216056939
Short name T894
Test name
Test status
Simulation time 410398280360 ps
CPU time 2042.18 seconds
Started Jul 15 06:38:43 PM PDT 24
Finished Jul 15 07:12:46 PM PDT 24
Peak memory 397252 kb
Host smart-8163b274-c251-4a9b-b406-2edf74b01c1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=216056939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.216056939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.683690129
Short name T1038
Test name
Test status
Simulation time 249402250362 ps
CPU time 1704.89 seconds
Started Jul 15 06:38:43 PM PDT 24
Finished Jul 15 07:07:08 PM PDT 24
Peak memory 366840 kb
Host smart-9992580f-6865-40b6-9d9f-f4420ffce3aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=683690129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.683690129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3455441742
Short name T542
Test name
Test status
Simulation time 13685524033 ps
CPU time 1021.23 seconds
Started Jul 15 06:38:42 PM PDT 24
Finished Jul 15 06:55:44 PM PDT 24
Peak memory 336008 kb
Host smart-f2c947a0-46e4-4fd8-bb63-d1ba8ae779ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3455441742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3455441742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.497655020
Short name T910
Test name
Test status
Simulation time 34408328033 ps
CPU time 828.28 seconds
Started Jul 15 06:38:42 PM PDT 24
Finished Jul 15 06:52:31 PM PDT 24
Peak memory 298976 kb
Host smart-70e19e5c-e679-46d1-b965-db45375c0886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=497655020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.497655020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.616697453
Short name T939
Test name
Test status
Simulation time 50475081785 ps
CPU time 3991.84 seconds
Started Jul 15 06:38:49 PM PDT 24
Finished Jul 15 07:45:21 PM PDT 24
Peak memory 643444 kb
Host smart-24ce4cb2-0a32-4336-8e10-6edad427f315
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=616697453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.616697453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.702484078
Short name T779
Test name
Test status
Simulation time 575335113381 ps
CPU time 3715.04 seconds
Started Jul 15 06:38:47 PM PDT 24
Finished Jul 15 07:40:43 PM PDT 24
Peak memory 552052 kb
Host smart-62b01da7-e35b-41e1-966e-7b97a1ea9153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=702484078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.702484078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.2704021677
Short name T291
Test name
Test status
Simulation time 31940641 ps
CPU time 0.78 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 06:32:53 PM PDT 24
Peak memory 205292 kb
Host smart-c1cae759-38f8-43a5-ae7f-24a961f6750b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704021677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2704021677 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.3033843258
Short name T563
Test name
Test status
Simulation time 10403894562 ps
CPU time 115 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 06:34:47 PM PDT 24
Peak memory 230376 kb
Host smart-df7017d6-6c2f-438f-b627-be7ac19d1448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033843258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3033843258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.1485837423
Short name T507
Test name
Test status
Simulation time 39985911148 ps
CPU time 176.94 seconds
Started Jul 15 06:32:49 PM PDT 24
Finished Jul 15 06:35:47 PM PDT 24
Peak memory 236744 kb
Host smart-10dabf80-61ae-4837-ae5e-2184df4ede13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485837423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.1485837423 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.2085020714
Short name T308
Test name
Test status
Simulation time 19473498311 ps
CPU time 475.02 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 06:40:47 PM PDT 24
Peak memory 229456 kb
Host smart-15198356-3cec-40d0-a6e7-c56c52522818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085020714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2085020714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.958469294
Short name T925
Test name
Test status
Simulation time 1503172105 ps
CPU time 26.09 seconds
Started Jul 15 06:32:48 PM PDT 24
Finished Jul 15 06:33:16 PM PDT 24
Peak memory 223684 kb
Host smart-2dd689fa-4028-428d-8644-ed0e76017c69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=958469294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.958469294 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2990714133
Short name T1027
Test name
Test status
Simulation time 2319397744 ps
CPU time 13.21 seconds
Started Jul 15 06:32:49 PM PDT 24
Finished Jul 15 06:33:03 PM PDT 24
Peak memory 223760 kb
Host smart-8d7b5d78-97f0-4190-ab9f-0c7669fd2191
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2990714133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2990714133 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.216717766
Short name T688
Test name
Test status
Simulation time 5599273986 ps
CPU time 88.62 seconds
Started Jul 15 06:32:46 PM PDT 24
Finished Jul 15 06:34:17 PM PDT 24
Peak memory 228960 kb
Host smart-afa9436a-e400-41d9-b1a4-b70f5660b88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216717766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.216717766 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.517453262
Short name T607
Test name
Test status
Simulation time 434427362 ps
CPU time 33.76 seconds
Started Jul 15 06:32:48 PM PDT 24
Finished Jul 15 06:33:23 PM PDT 24
Peak memory 239700 kb
Host smart-245244f4-f169-4d37-b97b-124f5669b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517453262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.517453262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.1437850820
Short name T63
Test name
Test status
Simulation time 647210207 ps
CPU time 2.33 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 06:32:54 PM PDT 24
Peak memory 215452 kb
Host smart-8f85861e-071b-4f55-a2a0-671d7b3bd927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437850820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1437850820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.2556678935
Short name T988
Test name
Test status
Simulation time 119298098 ps
CPU time 1.14 seconds
Started Jul 15 06:32:49 PM PDT 24
Finished Jul 15 06:32:51 PM PDT 24
Peak memory 215596 kb
Host smart-dd6cf95c-b6df-4b52-9f8c-88be3741b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556678935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2556678935 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.1893822556
Short name T554
Test name
Test status
Simulation time 44851111773 ps
CPU time 1901.86 seconds
Started Jul 15 06:32:48 PM PDT 24
Finished Jul 15 07:04:31 PM PDT 24
Peak memory 424404 kb
Host smart-5c690428-f26c-49ea-a8bb-03e854d628d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893822556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.1893822556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3890444561
Short name T1037
Test name
Test status
Simulation time 67161039603 ps
CPU time 258.25 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 06:37:10 PM PDT 24
Peak memory 240212 kb
Host smart-5e6fe35a-f2ab-463b-a9be-8a02c8969b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890444561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3890444561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2716626994
Short name T75
Test name
Test status
Simulation time 4317050708 ps
CPU time 32.73 seconds
Started Jul 15 06:32:49 PM PDT 24
Finished Jul 15 06:33:23 PM PDT 24
Peak memory 240552 kb
Host smart-1f7b2f85-78e1-4115-be2f-26e5456d5542
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716626994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2716626994 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.1602710483
Short name T932
Test name
Test status
Simulation time 3973140873 ps
CPU time 318.06 seconds
Started Jul 15 06:32:50 PM PDT 24
Finished Jul 15 06:38:09 PM PDT 24
Peak memory 247228 kb
Host smart-0ba99e6e-5d9c-4e1a-b77f-8c400b70874b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602710483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1602710483 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.984016045
Short name T960
Test name
Test status
Simulation time 2728464541 ps
CPU time 11.75 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 06:33:04 PM PDT 24
Peak memory 217256 kb
Host smart-04af0507-73cb-48c1-9f1d-34007253741d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984016045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.984016045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.3450432046
Short name T371
Test name
Test status
Simulation time 10120577040 ps
CPU time 11.51 seconds
Started Jul 15 06:32:50 PM PDT 24
Finished Jul 15 06:33:02 PM PDT 24
Peak memory 221304 kb
Host smart-f961ce68-715c-4a1c-8f65-8e624bd31ae6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3450432046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3450432046 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.3657951950
Short name T230
Test name
Test status
Simulation time 171843331 ps
CPU time 4.71 seconds
Started Jul 15 06:32:48 PM PDT 24
Finished Jul 15 06:32:54 PM PDT 24
Peak memory 215592 kb
Host smart-7fb8a69d-af00-495c-817c-461f6b396faa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657951950 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.3657951950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.492828808
Short name T557
Test name
Test status
Simulation time 66626229 ps
CPU time 3.93 seconds
Started Jul 15 06:32:48 PM PDT 24
Finished Jul 15 06:32:54 PM PDT 24
Peak memory 215580 kb
Host smart-14a035ba-f145-4675-91ca-1b4a9f580b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492828808 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.kmac_test_vectors_kmac_xof.492828808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.928015279
Short name T1047
Test name
Test status
Simulation time 190965580074 ps
CPU time 1856.66 seconds
Started Jul 15 06:32:52 PM PDT 24
Finished Jul 15 07:03:50 PM PDT 24
Peak memory 398968 kb
Host smart-67dba359-2d12-48e7-9a78-9008d81ff168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=928015279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.928015279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.2234337345
Short name T616
Test name
Test status
Simulation time 72740334932 ps
CPU time 1524.74 seconds
Started Jul 15 06:32:52 PM PDT 24
Finished Jul 15 06:58:18 PM PDT 24
Peak memory 368580 kb
Host smart-e76fb550-0c18-4828-9c49-a78be281f1f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2234337345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2234337345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2888599289
Short name T480
Test name
Test status
Simulation time 32972418868 ps
CPU time 1164.82 seconds
Started Jul 15 06:32:49 PM PDT 24
Finished Jul 15 06:52:15 PM PDT 24
Peak memory 325676 kb
Host smart-60d32955-703c-4cdc-9c6f-bf52f40481ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2888599289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2888599289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.4202829607
Short name T240
Test name
Test status
Simulation time 38047817215 ps
CPU time 845.38 seconds
Started Jul 15 06:32:50 PM PDT 24
Finished Jul 15 06:46:56 PM PDT 24
Peak memory 295372 kb
Host smart-9b5bc28b-e859-4c44-8129-047079d3813e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4202829607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.4202829607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.1321442715
Short name T900
Test name
Test status
Simulation time 330265982056 ps
CPU time 4481.51 seconds
Started Jul 15 06:32:51 PM PDT 24
Finished Jul 15 07:47:34 PM PDT 24
Peak memory 649984 kb
Host smart-66717906-cacf-4955-b8aa-5f268f2a461c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1321442715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1321442715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.4207451916
Short name T889
Test name
Test status
Simulation time 93851153658 ps
CPU time 3261.64 seconds
Started Jul 15 06:32:49 PM PDT 24
Finished Jul 15 07:27:12 PM PDT 24
Peak memory 558912 kb
Host smart-3cb3e7a1-38e2-44da-9254-5b1634e6de79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4207451916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.4207451916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.2224405328
Short name T516
Test name
Test status
Simulation time 15353637 ps
CPU time 0.77 seconds
Started Jul 15 06:39:12 PM PDT 24
Finished Jul 15 06:39:14 PM PDT 24
Peak memory 205288 kb
Host smart-46a9b3fa-ddfd-44bd-b860-e13845f47220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224405328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2224405328 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3333868627
Short name T630
Test name
Test status
Simulation time 9680080681 ps
CPU time 214.05 seconds
Started Jul 15 06:38:59 PM PDT 24
Finished Jul 15 06:42:34 PM PDT 24
Peak memory 241180 kb
Host smart-a5343574-e2f6-406b-973a-9dd8e5cad172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333868627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3333868627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.2852991850
Short name T659
Test name
Test status
Simulation time 24175898461 ps
CPU time 745.34 seconds
Started Jul 15 06:39:00 PM PDT 24
Finished Jul 15 06:51:26 PM PDT 24
Peak memory 232532 kb
Host smart-5941a321-23be-41c9-8826-5975d90cac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852991850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2852991850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2982853967
Short name T111
Test name
Test status
Simulation time 6213340228 ps
CPU time 254.12 seconds
Started Jul 15 06:38:59 PM PDT 24
Finished Jul 15 06:43:13 PM PDT 24
Peak memory 243920 kb
Host smart-94fee3a5-4ad7-4142-89be-499d7ae3a4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982853967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2982853967 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.893378072
Short name T577
Test name
Test status
Simulation time 14039028193 ps
CPU time 269.24 seconds
Started Jul 15 06:39:10 PM PDT 24
Finished Jul 15 06:43:40 PM PDT 24
Peak memory 251668 kb
Host smart-a73deb3a-d064-4530-b59d-4e76b7af81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893378072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.893378072 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.59248451
Short name T562
Test name
Test status
Simulation time 2046769084 ps
CPU time 5.44 seconds
Started Jul 15 06:39:09 PM PDT 24
Finished Jul 15 06:39:15 PM PDT 24
Peak memory 215604 kb
Host smart-acd1defa-798a-4f50-8d5c-b11b5a70af2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59248451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.59248451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.822161143
Short name T6
Test name
Test status
Simulation time 55756118 ps
CPU time 1.2 seconds
Started Jul 15 06:39:10 PM PDT 24
Finished Jul 15 06:39:11 PM PDT 24
Peak memory 215548 kb
Host smart-c92f04fa-2329-40cd-bef5-c0300edb8d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822161143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.822161143 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.465156192
Short name T697
Test name
Test status
Simulation time 15019166311 ps
CPU time 340.23 seconds
Started Jul 15 06:38:59 PM PDT 24
Finished Jul 15 06:44:39 PM PDT 24
Peak memory 250460 kb
Host smart-b37d8315-850e-4967-827d-73a6c15a7c05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465156192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.465156192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.2133613751
Short name T609
Test name
Test status
Simulation time 15511342186 ps
CPU time 194.6 seconds
Started Jul 15 06:38:58 PM PDT 24
Finished Jul 15 06:42:13 PM PDT 24
Peak memory 238928 kb
Host smart-f8756e0f-4f3b-4a46-8c6a-ddde2fea4c85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133613751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2133613751 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.2341212022
Short name T14
Test name
Test status
Simulation time 1301495959 ps
CPU time 17.14 seconds
Started Jul 15 06:38:58 PM PDT 24
Finished Jul 15 06:39:16 PM PDT 24
Peak memory 218368 kb
Host smart-4d1f43f1-32a3-429b-82e7-ebab5306fd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341212022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2341212022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.2785998814
Short name T790
Test name
Test status
Simulation time 11752590111 ps
CPU time 228.35 seconds
Started Jul 15 06:39:13 PM PDT 24
Finished Jul 15 06:43:02 PM PDT 24
Peak memory 243260 kb
Host smart-0276bb8e-c97c-46e7-8a26-9e5c269fab2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2785998814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2785998814 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.3023161125
Short name T741
Test name
Test status
Simulation time 131903066 ps
CPU time 4.38 seconds
Started Jul 15 06:38:59 PM PDT 24
Finished Jul 15 06:39:04 PM PDT 24
Peak memory 215620 kb
Host smart-54964d38-86da-4a00-9484-d952844bc029
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023161125 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.3023161125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.3552989772
Short name T919
Test name
Test status
Simulation time 393583342 ps
CPU time 4.54 seconds
Started Jul 15 06:39:00 PM PDT 24
Finished Jul 15 06:39:05 PM PDT 24
Peak memory 215660 kb
Host smart-64cc2462-2ece-48c2-939b-228cb085c133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552989772 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.3552989772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.3511991756
Short name T83
Test name
Test status
Simulation time 75249978501 ps
CPU time 1650.31 seconds
Started Jul 15 06:38:58 PM PDT 24
Finished Jul 15 07:06:29 PM PDT 24
Peak memory 391424 kb
Host smart-50648718-56ec-48bf-b588-2134c6579db2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3511991756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.3511991756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.411462802
Short name T694
Test name
Test status
Simulation time 63516526828 ps
CPU time 1742.71 seconds
Started Jul 15 06:38:59 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 373116 kb
Host smart-f623675f-e682-47ca-9ae1-d28d92f634a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=411462802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.411462802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.3776008961
Short name T316
Test name
Test status
Simulation time 151760206509 ps
CPU time 1437.41 seconds
Started Jul 15 06:38:59 PM PDT 24
Finished Jul 15 07:02:57 PM PDT 24
Peak memory 339616 kb
Host smart-974e01a3-65d9-492b-b3c3-60cc4ff2a8ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3776008961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.3776008961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1940250177
Short name T326
Test name
Test status
Simulation time 51710240845 ps
CPU time 993.12 seconds
Started Jul 15 06:38:58 PM PDT 24
Finished Jul 15 06:55:32 PM PDT 24
Peak memory 298160 kb
Host smart-3e4e4660-480f-41cc-95eb-be4dc9dc3000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1940250177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1940250177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.2912908771
Short name T953
Test name
Test status
Simulation time 301300183773 ps
CPU time 3833.81 seconds
Started Jul 15 06:38:59 PM PDT 24
Finished Jul 15 07:42:54 PM PDT 24
Peak memory 657780 kb
Host smart-cf2a45ec-06a2-434d-8705-b189b8917888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2912908771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.2912908771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.1056456274
Short name T767
Test name
Test status
Simulation time 893124531248 ps
CPU time 4000.62 seconds
Started Jul 15 06:39:01 PM PDT 24
Finished Jul 15 07:45:42 PM PDT 24
Peak memory 558432 kb
Host smart-fad39928-2674-4693-a4aa-f2f9e59fc4c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1056456274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.1056456274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.363833560
Short name T211
Test name
Test status
Simulation time 13757800 ps
CPU time 0.77 seconds
Started Jul 15 06:39:18 PM PDT 24
Finished Jul 15 06:39:19 PM PDT 24
Peak memory 205288 kb
Host smart-74575f8c-3e5f-43e5-888c-c4f5fd291c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363833560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.363833560 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.1724190823
Short name T284
Test name
Test status
Simulation time 4365127612 ps
CPU time 28.08 seconds
Started Jul 15 06:39:13 PM PDT 24
Finished Jul 15 06:39:41 PM PDT 24
Peak memory 223828 kb
Host smart-643d51a5-02a9-4f51-a531-f22e802acabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724190823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1724190823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.3952166044
Short name T696
Test name
Test status
Simulation time 6632522132 ps
CPU time 561.38 seconds
Started Jul 15 06:39:09 PM PDT 24
Finished Jul 15 06:48:31 PM PDT 24
Peak memory 232104 kb
Host smart-a07c9f60-7226-4cb7-9697-9541d6fb7451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952166044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3952166044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.315586438
Short name T755
Test name
Test status
Simulation time 4272101460 ps
CPU time 73.76 seconds
Started Jul 15 06:39:11 PM PDT 24
Finished Jul 15 06:40:26 PM PDT 24
Peak memory 224576 kb
Host smart-ad1d91e8-2eaa-4e5f-827c-033edc5cb0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315586438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.315586438 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.3400241574
Short name T247
Test name
Test status
Simulation time 12433405408 ps
CPU time 229.01 seconds
Started Jul 15 06:39:11 PM PDT 24
Finished Jul 15 06:43:01 PM PDT 24
Peak memory 248448 kb
Host smart-4316697e-b7fa-461f-a12f-500c8e53f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400241574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3400241574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.175162625
Short name T598
Test name
Test status
Simulation time 106756752 ps
CPU time 1.29 seconds
Started Jul 15 06:39:11 PM PDT 24
Finished Jul 15 06:39:13 PM PDT 24
Peak memory 215572 kb
Host smart-0af43b1d-9c04-4572-a519-f5de12a858a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175162625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.175162625 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.2917319001
Short name T493
Test name
Test status
Simulation time 11831022524 ps
CPU time 929.57 seconds
Started Jul 15 06:39:12 PM PDT 24
Finished Jul 15 06:54:42 PM PDT 24
Peak memory 319588 kb
Host smart-9c442fc4-29e5-41ac-88a3-305ea264b6ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917319001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.2917319001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.3053265433
Short name T378
Test name
Test status
Simulation time 3074186572 ps
CPU time 253.03 seconds
Started Jul 15 06:39:10 PM PDT 24
Finished Jul 15 06:43:24 PM PDT 24
Peak memory 241272 kb
Host smart-6138878e-57b5-4c2b-9f0f-39273d649745
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053265433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3053265433 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.809451481
Short name T391
Test name
Test status
Simulation time 1129397461 ps
CPU time 24.36 seconds
Started Jul 15 06:39:10 PM PDT 24
Finished Jul 15 06:39:34 PM PDT 24
Peak memory 216712 kb
Host smart-86e1acbd-8ae0-4816-a308-9b052d52f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809451481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.809451481 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.3010817496
Short name T460
Test name
Test status
Simulation time 8524450454 ps
CPU time 149.58 seconds
Started Jul 15 06:39:18 PM PDT 24
Finished Jul 15 06:41:49 PM PDT 24
Peak memory 256532 kb
Host smart-a52947c5-6f81-4180-a2c3-256456120b0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3010817496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3010817496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.3865727604
Short name T392
Test name
Test status
Simulation time 72536964 ps
CPU time 4.3 seconds
Started Jul 15 06:39:11 PM PDT 24
Finished Jul 15 06:39:15 PM PDT 24
Peak memory 215648 kb
Host smart-f9f69eb6-723a-4194-9bb5-072ad094d781
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865727604 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.3865727604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1437034954
Short name T915
Test name
Test status
Simulation time 3425898131 ps
CPU time 6.1 seconds
Started Jul 15 06:39:13 PM PDT 24
Finished Jul 15 06:39:19 PM PDT 24
Peak memory 215596 kb
Host smart-57677f16-ec60-4abe-a329-c72e8ef8252c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437034954 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1437034954 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.3082949341
Short name T228
Test name
Test status
Simulation time 66783312834 ps
CPU time 1775.66 seconds
Started Jul 15 06:39:12 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 395344 kb
Host smart-5d25eda0-98cc-4736-9b68-1aa9ede9d8d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3082949341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.3082949341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.57679308
Short name T317
Test name
Test status
Simulation time 64372078761 ps
CPU time 1726.18 seconds
Started Jul 15 06:39:12 PM PDT 24
Finished Jul 15 07:07:59 PM PDT 24
Peak memory 377556 kb
Host smart-c91e0f9d-dab5-4998-8945-47ea76eb92ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57679308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.57679308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.364417248
Short name T388
Test name
Test status
Simulation time 14088588629 ps
CPU time 1185.81 seconds
Started Jul 15 06:39:12 PM PDT 24
Finished Jul 15 06:58:59 PM PDT 24
Peak memory 338468 kb
Host smart-637545ff-f687-4560-aa39-4cbc7946062d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=364417248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.364417248 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.47074194
Short name T1019
Test name
Test status
Simulation time 201500114497 ps
CPU time 911.57 seconds
Started Jul 15 06:39:09 PM PDT 24
Finished Jul 15 06:54:21 PM PDT 24
Peak memory 292648 kb
Host smart-91fce1f2-7c86-49be-8490-5cafeddebb7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=47074194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.47074194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.3471512603
Short name T365
Test name
Test status
Simulation time 1061412952541 ps
CPU time 5243.47 seconds
Started Jul 15 06:39:08 PM PDT 24
Finished Jul 15 08:06:33 PM PDT 24
Peak memory 642804 kb
Host smart-65e2718e-4cfb-4d5d-b081-a89db211fb51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3471512603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3471512603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.56117997
Short name T272
Test name
Test status
Simulation time 181061759277 ps
CPU time 3319.37 seconds
Started Jul 15 06:39:09 PM PDT 24
Finished Jul 15 07:34:29 PM PDT 24
Peak memory 565688 kb
Host smart-d087b604-ff6a-45f1-9cb4-5fade2d9067b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=56117997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.56117997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.2657849743
Short name T383
Test name
Test status
Simulation time 51671801 ps
CPU time 0.82 seconds
Started Jul 15 06:39:38 PM PDT 24
Finished Jul 15 06:39:39 PM PDT 24
Peak memory 205276 kb
Host smart-5453365e-7428-4aa7-a286-311292ead984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657849743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2657849743 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2071761937
Short name T836
Test name
Test status
Simulation time 3839033215 ps
CPU time 39.09 seconds
Started Jul 15 06:39:29 PM PDT 24
Finished Jul 15 06:40:09 PM PDT 24
Peak memory 223848 kb
Host smart-15d83ba4-b2b0-4276-974b-75bfeda1821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071761937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2071761937 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.499954072
Short name T265
Test name
Test status
Simulation time 20065081333 ps
CPU time 635.68 seconds
Started Jul 15 06:39:18 PM PDT 24
Finished Jul 15 06:49:55 PM PDT 24
Peak memory 231504 kb
Host smart-09a57de0-921c-4c2d-ad17-2be5492711df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499954072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.499954072 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.2543723301
Short name T411
Test name
Test status
Simulation time 36143429622 ps
CPU time 215.67 seconds
Started Jul 15 06:39:29 PM PDT 24
Finished Jul 15 06:43:05 PM PDT 24
Peak memory 242384 kb
Host smart-ae62d582-9809-4791-99ee-669ab69e7571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543723301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2543723301 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.1135286733
Short name T862
Test name
Test status
Simulation time 7657530771 ps
CPU time 229.4 seconds
Started Jul 15 06:39:33 PM PDT 24
Finished Jul 15 06:43:22 PM PDT 24
Peak memory 256552 kb
Host smart-4889fffc-dff4-438c-8a49-315f0073fedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135286733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1135286733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.4100492341
Short name T65
Test name
Test status
Simulation time 7543796618 ps
CPU time 9.2 seconds
Started Jul 15 06:39:32 PM PDT 24
Finished Jul 15 06:39:41 PM PDT 24
Peak memory 207604 kb
Host smart-a3dda429-db82-4d71-acfd-eeb7a3c14bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100492341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.4100492341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.4036209690
Short name T454
Test name
Test status
Simulation time 141988591423 ps
CPU time 1662.96 seconds
Started Jul 15 06:39:19 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 404180 kb
Host smart-4b2d0563-ad14-4283-9967-0ed9d039cfbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036209690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.4036209690 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.2684771589
Short name T200
Test name
Test status
Simulation time 12964857292 ps
CPU time 307.14 seconds
Started Jul 15 06:39:18 PM PDT 24
Finished Jul 15 06:44:26 PM PDT 24
Peak memory 246812 kb
Host smart-426bfd42-b64c-4a8d-a537-db76c012dcd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684771589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2684771589 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1202405418
Short name T222
Test name
Test status
Simulation time 600957829 ps
CPU time 29.25 seconds
Started Jul 15 06:39:18 PM PDT 24
Finished Jul 15 06:39:48 PM PDT 24
Peak memory 216640 kb
Host smart-edfdf709-cec2-49b3-9ae6-aa15c3b99cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202405418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1202405418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.2834300155
Short name T835
Test name
Test status
Simulation time 19519634501 ps
CPU time 260.96 seconds
Started Jul 15 06:39:30 PM PDT 24
Finished Jul 15 06:43:51 PM PDT 24
Peak memory 273292 kb
Host smart-62493222-61a9-4395-bc02-a41bc49ed502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2834300155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2834300155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.1948898861
Short name T1070
Test name
Test status
Simulation time 64187853 ps
CPU time 4.27 seconds
Started Jul 15 06:39:32 PM PDT 24
Finished Jul 15 06:39:37 PM PDT 24
Peak memory 215604 kb
Host smart-8d203c77-7e67-4c8c-b14c-7a0b005d2a7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948898861 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.1948898861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.4207968391
Short name T830
Test name
Test status
Simulation time 827117063 ps
CPU time 4.5 seconds
Started Jul 15 06:39:30 PM PDT 24
Finished Jul 15 06:39:35 PM PDT 24
Peak memory 215680 kb
Host smart-210c6f58-72df-466f-9e7b-2a93e2461339
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207968391 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.4207968391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.3191512363
Short name T84
Test name
Test status
Simulation time 640764730557 ps
CPU time 2054.03 seconds
Started Jul 15 06:39:25 PM PDT 24
Finished Jul 15 07:13:40 PM PDT 24
Peak memory 386616 kb
Host smart-c9ee45a5-ea23-4796-80d3-a39d58df0dbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3191512363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.3191512363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.3729193291
Short name T711
Test name
Test status
Simulation time 371334421043 ps
CPU time 1948.49 seconds
Started Jul 15 06:39:23 PM PDT 24
Finished Jul 15 07:11:52 PM PDT 24
Peak memory 379200 kb
Host smart-c711a78b-4846-45cb-b847-c1f07c4ad238
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3729193291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.3729193291 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3199291963
Short name T839
Test name
Test status
Simulation time 97351321621 ps
CPU time 1419.67 seconds
Started Jul 15 06:39:26 PM PDT 24
Finished Jul 15 07:03:06 PM PDT 24
Peak memory 333576 kb
Host smart-5f96f6d7-6e65-4f7c-9d06-7927f9159f14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3199291963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3199291963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.3000290471
Short name T798
Test name
Test status
Simulation time 9698221168 ps
CPU time 764.6 seconds
Started Jul 15 06:39:26 PM PDT 24
Finished Jul 15 06:52:11 PM PDT 24
Peak memory 290976 kb
Host smart-b9103c81-c31a-4053-9c3a-4d2bc4d85728
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3000290471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3000290471 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.492518445
Short name T628
Test name
Test status
Simulation time 222271015933 ps
CPU time 4786.16 seconds
Started Jul 15 06:39:25 PM PDT 24
Finished Jul 15 07:59:12 PM PDT 24
Peak memory 648464 kb
Host smart-95a9703d-9480-43d2-b96f-58e79b07dc74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=492518445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.492518445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_alert_test.2144432699
Short name T246
Test name
Test status
Simulation time 16022348 ps
CPU time 0.79 seconds
Started Jul 15 06:39:47 PM PDT 24
Finished Jul 15 06:39:48 PM PDT 24
Peak memory 205276 kb
Host smart-501ee893-8c6b-4558-a9a6-2e54bc0287cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144432699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2144432699 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2793879800
Short name T468
Test name
Test status
Simulation time 1916468153 ps
CPU time 62.49 seconds
Started Jul 15 06:39:47 PM PDT 24
Finished Jul 15 06:40:49 PM PDT 24
Peak memory 226612 kb
Host smart-7749c4f4-d9f9-41a8-8951-b0b7f544b160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793879800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2793879800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.1074432956
Short name T92
Test name
Test status
Simulation time 117514285917 ps
CPU time 634.37 seconds
Started Jul 15 06:39:37 PM PDT 24
Finished Jul 15 06:50:12 PM PDT 24
Peak memory 230316 kb
Host smart-a67f8ddc-5278-4eb8-9abf-a7340f775bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074432956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1074432956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.1719888665
Short name T946
Test name
Test status
Simulation time 28423425549 ps
CPU time 165.72 seconds
Started Jul 15 06:39:48 PM PDT 24
Finished Jul 15 06:42:35 PM PDT 24
Peak memory 236412 kb
Host smart-e87bdc32-f229-49ae-bdec-8da46a0996ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719888665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1719888665 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.1226727413
Short name T804
Test name
Test status
Simulation time 4028239488 ps
CPU time 280.13 seconds
Started Jul 15 06:39:48 PM PDT 24
Finished Jul 15 06:44:29 PM PDT 24
Peak memory 263812 kb
Host smart-4f25202b-7999-49b3-ba10-f791a86066e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226727413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1226727413 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.1931312851
Short name T964
Test name
Test status
Simulation time 1498055980 ps
CPU time 4.3 seconds
Started Jul 15 06:39:48 PM PDT 24
Finished Jul 15 06:39:52 PM PDT 24
Peak memory 207388 kb
Host smart-0521ee50-1fb3-44b1-bc33-b13e09caa7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931312851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1931312851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.3213134296
Short name T362
Test name
Test status
Simulation time 64588197 ps
CPU time 1.24 seconds
Started Jul 15 06:39:49 PM PDT 24
Finished Jul 15 06:39:51 PM PDT 24
Peak memory 215584 kb
Host smart-f217ecdd-9711-428f-b68e-119c6ea2d745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213134296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3213134296 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.3490066807
Short name T253
Test name
Test status
Simulation time 399649755443 ps
CPU time 2040.05 seconds
Started Jul 15 06:39:39 PM PDT 24
Finished Jul 15 07:13:40 PM PDT 24
Peak memory 411988 kb
Host smart-06f4ad17-2a03-452e-a609-d3c272e46762
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490066807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.3490066807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.2817380784
Short name T961
Test name
Test status
Simulation time 552215135 ps
CPU time 12.65 seconds
Started Jul 15 06:39:39 PM PDT 24
Finished Jul 15 06:39:53 PM PDT 24
Peak memory 217468 kb
Host smart-a957c5eb-afc3-49be-8ece-da4e088964d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817380784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2817380784 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.2203853368
Short name T566
Test name
Test status
Simulation time 7562523604 ps
CPU time 40.59 seconds
Started Jul 15 06:39:38 PM PDT 24
Finished Jul 15 06:40:19 PM PDT 24
Peak memory 219148 kb
Host smart-05737f16-214b-45e6-ac29-67ee695169f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203853368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2203853368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.2520062401
Short name T536
Test name
Test status
Simulation time 482951568 ps
CPU time 4.89 seconds
Started Jul 15 06:39:43 PM PDT 24
Finished Jul 15 06:39:48 PM PDT 24
Peak memory 215604 kb
Host smart-249a397d-0dba-489c-9ffc-8c9ff87531fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520062401 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.2520062401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.3708367279
Short name T328
Test name
Test status
Simulation time 333544752 ps
CPU time 4.69 seconds
Started Jul 15 06:39:46 PM PDT 24
Finished Jul 15 06:39:51 PM PDT 24
Peak memory 215600 kb
Host smart-50273698-35e7-43cc-b124-65313e523b62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708367279 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.3708367279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.1378610583
Short name T244
Test name
Test status
Simulation time 19594635651 ps
CPU time 1533.28 seconds
Started Jul 15 06:39:37 PM PDT 24
Finished Jul 15 07:05:11 PM PDT 24
Peak memory 387224 kb
Host smart-41b94d24-d321-4f6e-9f80-6173ae2090f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1378610583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.1378610583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3858950878
Short name T209
Test name
Test status
Simulation time 856256764417 ps
CPU time 1625.64 seconds
Started Jul 15 06:39:38 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 367316 kb
Host smart-e3753df8-8bc7-48eb-8a6b-c3b50d6587b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3858950878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3858950878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.2334473914
Short name T753
Test name
Test status
Simulation time 27236363915 ps
CPU time 1122.87 seconds
Started Jul 15 06:39:43 PM PDT 24
Finished Jul 15 06:58:27 PM PDT 24
Peak memory 329060 kb
Host smart-74304d62-685c-4409-9f8b-11a48c859896
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2334473914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2334473914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.282601028
Short name T421
Test name
Test status
Simulation time 50768885310 ps
CPU time 986.92 seconds
Started Jul 15 06:39:43 PM PDT 24
Finished Jul 15 06:56:10 PM PDT 24
Peak memory 294636 kb
Host smart-4b57365d-1f9e-40ce-baed-0f091d7b99bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=282601028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.282601028 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.360770495
Short name T632
Test name
Test status
Simulation time 505482896734 ps
CPU time 4928.69 seconds
Started Jul 15 06:39:42 PM PDT 24
Finished Jul 15 08:01:52 PM PDT 24
Peak memory 636100 kb
Host smart-43380a43-2b20-4736-b6ad-6b9d533b98fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=360770495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.360770495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.1061515251
Short name T1042
Test name
Test status
Simulation time 187784987974 ps
CPU time 3907.91 seconds
Started Jul 15 06:39:46 PM PDT 24
Finished Jul 15 07:44:55 PM PDT 24
Peak memory 551636 kb
Host smart-cba4a031-513b-4790-9f27-41c3f8385737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1061515251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.1061515251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.2413231693
Short name T582
Test name
Test status
Simulation time 68516794 ps
CPU time 0.8 seconds
Started Jul 15 06:40:06 PM PDT 24
Finished Jul 15 06:40:08 PM PDT 24
Peak memory 205248 kb
Host smart-f57e7244-bea2-42e6-ab6c-4e8ef4d3c478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413231693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2413231693 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.39324998
Short name T911
Test name
Test status
Simulation time 9486443941 ps
CPU time 187.98 seconds
Started Jul 15 06:40:00 PM PDT 24
Finished Jul 15 06:43:08 PM PDT 24
Peak memory 236936 kb
Host smart-c61a3163-05bf-4966-a83c-27fa0462435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39324998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.39324998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.3655270165
Short name T137
Test name
Test status
Simulation time 9177027183 ps
CPU time 161.23 seconds
Started Jul 15 06:39:47 PM PDT 24
Finished Jul 15 06:42:29 PM PDT 24
Peak memory 223256 kb
Host smart-854d3f22-b551-4981-8efa-c0c6f1e2f30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655270165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.3655270165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.1898317841
Short name T93
Test name
Test status
Simulation time 32020183887 ps
CPU time 278.81 seconds
Started Jul 15 06:40:01 PM PDT 24
Finished Jul 15 06:44:40 PM PDT 24
Peak memory 244752 kb
Host smart-44b96a33-b6a3-4b4d-946b-f941d2193da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898317841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1898317841 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2258588135
Short name T48
Test name
Test status
Simulation time 5272113716 ps
CPU time 131.84 seconds
Started Jul 15 06:39:59 PM PDT 24
Finished Jul 15 06:42:11 PM PDT 24
Peak memory 240212 kb
Host smart-f2f39e5b-86bc-485a-857e-5ad73631ac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258588135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2258588135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.2312268712
Short name T446
Test name
Test status
Simulation time 1169439561 ps
CPU time 6.11 seconds
Started Jul 15 06:40:01 PM PDT 24
Finished Jul 15 06:40:08 PM PDT 24
Peak memory 215484 kb
Host smart-25b8f1b9-ae3f-4b26-a69c-8efe4f0169ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312268712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2312268712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.70005656
Short name T678
Test name
Test status
Simulation time 3506397841 ps
CPU time 39.39 seconds
Started Jul 15 06:39:59 PM PDT 24
Finished Jul 15 06:40:39 PM PDT 24
Peak memory 232036 kb
Host smart-86cf2574-c5b3-499d-b252-eb42ecb4a56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70005656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.70005656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.2693355870
Short name T494
Test name
Test status
Simulation time 14550494384 ps
CPU time 1203.57 seconds
Started Jul 15 06:39:48 PM PDT 24
Finished Jul 15 06:59:52 PM PDT 24
Peak memory 356468 kb
Host smart-79addb93-2533-42ba-9d56-8236820d46bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693355870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.2693355870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.2552825340
Short name T608
Test name
Test status
Simulation time 3667101837 ps
CPU time 74.04 seconds
Started Jul 15 06:39:49 PM PDT 24
Finished Jul 15 06:41:03 PM PDT 24
Peak memory 225180 kb
Host smart-42bddc98-030e-4db2-82f3-9814cad9d459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552825340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2552825340 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.2689140404
Short name T886
Test name
Test status
Simulation time 724204206 ps
CPU time 34.78 seconds
Started Jul 15 06:39:48 PM PDT 24
Finished Jul 15 06:40:23 PM PDT 24
Peak memory 219656 kb
Host smart-45114fb2-c17b-4761-b4ed-a7eb5eaac25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689140404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2689140404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.4247859936
Short name T23
Test name
Test status
Simulation time 23536706910 ps
CPU time 231.47 seconds
Started Jul 15 06:39:58 PM PDT 24
Finished Jul 15 06:43:50 PM PDT 24
Peak memory 271312 kb
Host smart-68bab989-c010-499e-917b-d22e3e918bd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4247859936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4247859936 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.3847138608
Short name T1024
Test name
Test status
Simulation time 168780829 ps
CPU time 4.67 seconds
Started Jul 15 06:39:54 PM PDT 24
Finished Jul 15 06:39:59 PM PDT 24
Peak memory 215736 kb
Host smart-dc915201-fbd9-4cae-85a2-9603d66da82c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847138608 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.3847138608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.1365080317
Short name T553
Test name
Test status
Simulation time 388828846 ps
CPU time 4.43 seconds
Started Jul 15 06:39:54 PM PDT 24
Finished Jul 15 06:39:59 PM PDT 24
Peak memory 215600 kb
Host smart-2921d65a-beee-4630-8e0d-fc0ce2e4cc75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365080317 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.1365080317 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.311818791
Short name T613
Test name
Test status
Simulation time 18859933099 ps
CPU time 1594.5 seconds
Started Jul 15 06:39:55 PM PDT 24
Finished Jul 15 07:06:30 PM PDT 24
Peak memory 378308 kb
Host smart-e5c022f5-eb0f-4933-9821-25b51b26fe5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=311818791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.311818791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.2813440210
Short name T518
Test name
Test status
Simulation time 309704862027 ps
CPU time 1875.25 seconds
Started Jul 15 06:39:54 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 378872 kb
Host smart-7222f386-1afb-400c-b9ff-12ab5286417f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2813440210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2813440210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.1646839740
Short name T1053
Test name
Test status
Simulation time 47095198472 ps
CPU time 1337.01 seconds
Started Jul 15 06:39:54 PM PDT 24
Finished Jul 15 07:02:11 PM PDT 24
Peak memory 333476 kb
Host smart-a3e2eb52-b130-4cd3-8300-19d79e367eea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1646839740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.1646839740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.132132408
Short name T486
Test name
Test status
Simulation time 97371341970 ps
CPU time 917.4 seconds
Started Jul 15 06:39:54 PM PDT 24
Finished Jul 15 06:55:11 PM PDT 24
Peak memory 289976 kb
Host smart-92cb4848-e480-42ed-953c-eaddce8a5fe4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=132132408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.132132408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.4070065759
Short name T255
Test name
Test status
Simulation time 1394701051537 ps
CPU time 4840.43 seconds
Started Jul 15 06:39:53 PM PDT 24
Finished Jul 15 08:00:35 PM PDT 24
Peak memory 651624 kb
Host smart-32133265-eb94-4279-87a9-9c4cdf8738a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4070065759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.4070065759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.4266994183
Short name T852
Test name
Test status
Simulation time 523325795462 ps
CPU time 4016 seconds
Started Jul 15 06:39:52 PM PDT 24
Finished Jul 15 07:46:49 PM PDT 24
Peak memory 568184 kb
Host smart-18303be3-52b3-423f-8e6e-f3eb4d6a306a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4266994183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.4266994183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.2107687523
Short name T51
Test name
Test status
Simulation time 26731822 ps
CPU time 0.81 seconds
Started Jul 15 06:40:26 PM PDT 24
Finished Jul 15 06:40:27 PM PDT 24
Peak memory 205276 kb
Host smart-b9b3440f-14b2-4cd3-98fc-71b768c7315c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107687523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2107687523 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3139426456
Short name T965
Test name
Test status
Simulation time 6378566256 ps
CPU time 180.68 seconds
Started Jul 15 06:40:15 PM PDT 24
Finished Jul 15 06:43:17 PM PDT 24
Peak memory 238656 kb
Host smart-27c04ecd-352a-4207-aa32-0c41afec7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139426456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3139426456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.583850462
Short name T302
Test name
Test status
Simulation time 77455654630 ps
CPU time 923.62 seconds
Started Jul 15 06:40:06 PM PDT 24
Finished Jul 15 06:55:30 PM PDT 24
Peak memory 232768 kb
Host smart-9f0a0cd1-3da3-4baa-928f-b8c4d8cd02aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583850462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.583850462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.2383674183
Short name T333
Test name
Test status
Simulation time 7311345036 ps
CPU time 148.26 seconds
Started Jul 15 06:40:15 PM PDT 24
Finished Jul 15 06:42:44 PM PDT 24
Peak memory 232640 kb
Host smart-4aadce34-f31a-4b81-b984-1810696d18b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383674183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2383674183 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.1163791136
Short name T49
Test name
Test status
Simulation time 1115472586 ps
CPU time 17.88 seconds
Started Jul 15 06:40:20 PM PDT 24
Finished Jul 15 06:40:38 PM PDT 24
Peak memory 223820 kb
Host smart-d167f1eb-16ef-4490-bc5c-429641ce5058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163791136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1163791136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.1797253825
Short name T374
Test name
Test status
Simulation time 2586792268 ps
CPU time 4.09 seconds
Started Jul 15 06:40:22 PM PDT 24
Finished Jul 15 06:40:26 PM PDT 24
Peak memory 207248 kb
Host smart-5249c4ce-6ee3-4272-a435-435d27b513a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797253825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1797253825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3393341134
Short name T394
Test name
Test status
Simulation time 441880825 ps
CPU time 1.42 seconds
Started Jul 15 06:40:26 PM PDT 24
Finished Jul 15 06:40:28 PM PDT 24
Peak memory 215536 kb
Host smart-3ea50c18-0736-49ec-8e9d-150805489e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393341134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3393341134 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.937442510
Short name T1000
Test name
Test status
Simulation time 88739218316 ps
CPU time 2108.87 seconds
Started Jul 15 06:40:05 PM PDT 24
Finished Jul 15 07:15:14 PM PDT 24
Peak memory 417260 kb
Host smart-b63c15ef-7304-4c8c-bed9-403c1bd5b587
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937442510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_an
d_output.937442510 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.680940972
Short name T640
Test name
Test status
Simulation time 12759176755 ps
CPU time 135.87 seconds
Started Jul 15 06:40:06 PM PDT 24
Finished Jul 15 06:42:22 PM PDT 24
Peak memory 233076 kb
Host smart-9cd2df36-c018-4bc5-938f-238713ab3b4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680940972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.680940972 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.2999001324
Short name T991
Test name
Test status
Simulation time 564580009 ps
CPU time 27.55 seconds
Started Jul 15 06:40:05 PM PDT 24
Finished Jul 15 06:40:32 PM PDT 24
Peak memory 218448 kb
Host smart-d58a1df6-63d3-4c38-b00c-03c69e8f62a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999001324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2999001324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.3493636048
Short name T287
Test name
Test status
Simulation time 26860127283 ps
CPU time 2176.18 seconds
Started Jul 15 06:40:27 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 466240 kb
Host smart-4cc8ac41-83a8-42e1-a59e-22b777f1fd74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3493636048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3493636048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.1841191202
Short name T571
Test name
Test status
Simulation time 651606763 ps
CPU time 4.41 seconds
Started Jul 15 06:40:15 PM PDT 24
Finished Jul 15 06:40:20 PM PDT 24
Peak memory 215628 kb
Host smart-272e3763-536f-43e6-8d07-ad66c6011e6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841191202 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.1841191202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.4113421587
Short name T393
Test name
Test status
Simulation time 648999108 ps
CPU time 4.35 seconds
Started Jul 15 06:40:16 PM PDT 24
Finished Jul 15 06:40:21 PM PDT 24
Peak memory 215584 kb
Host smart-151261db-88a8-4499-8465-95a021d5940c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113421587 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.4113421587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2332545680
Short name T1062
Test name
Test status
Simulation time 94790272935 ps
CPU time 1957.2 seconds
Started Jul 15 06:40:11 PM PDT 24
Finished Jul 15 07:12:48 PM PDT 24
Peak memory 375568 kb
Host smart-6d2e53ea-8b7d-479b-8ecc-d3ef567cc57d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2332545680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2332545680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.1411242779
Short name T680
Test name
Test status
Simulation time 176669871974 ps
CPU time 1754.44 seconds
Started Jul 15 06:40:13 PM PDT 24
Finished Jul 15 07:09:28 PM PDT 24
Peak memory 389380 kb
Host smart-dfcf9278-0a65-4270-a879-f774ae508f61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1411242779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.1411242779 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.1561841936
Short name T242
Test name
Test status
Simulation time 48577381147 ps
CPU time 1256.04 seconds
Started Jul 15 06:40:12 PM PDT 24
Finished Jul 15 07:01:09 PM PDT 24
Peak memory 341364 kb
Host smart-9140c9d2-d1da-4122-8a68-69b403acd8f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1561841936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.1561841936 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.1745559593
Short name T372
Test name
Test status
Simulation time 132585402547 ps
CPU time 971.52 seconds
Started Jul 15 06:40:11 PM PDT 24
Finished Jul 15 06:56:23 PM PDT 24
Peak memory 297340 kb
Host smart-93799694-51cd-43f4-ac45-9ef22577cfd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1745559593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.1745559593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.2808009993
Short name T962
Test name
Test status
Simulation time 179490170725 ps
CPU time 4708.74 seconds
Started Jul 15 06:40:12 PM PDT 24
Finished Jul 15 07:58:41 PM PDT 24
Peak memory 641004 kb
Host smart-b3c45fb8-ddcb-4b43-a4ed-7df511c660fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2808009993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.2808009993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.1441754013
Short name T847
Test name
Test status
Simulation time 45462876372 ps
CPU time 3388.19 seconds
Started Jul 15 06:40:15 PM PDT 24
Finished Jul 15 07:36:44 PM PDT 24
Peak memory 559540 kb
Host smart-a54f1334-d4db-48d8-b415-fbc252a50a0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1441754013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.1441754013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.4060491929
Short name T296
Test name
Test status
Simulation time 64975927 ps
CPU time 0.75 seconds
Started Jul 15 06:40:47 PM PDT 24
Finished Jul 15 06:40:49 PM PDT 24
Peak memory 205228 kb
Host smart-e1ba0633-b812-400e-bbeb-a77654124f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060491929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.4060491929 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.1070418757
Short name T776
Test name
Test status
Simulation time 2102071649 ps
CPU time 84.46 seconds
Started Jul 15 06:40:36 PM PDT 24
Finished Jul 15 06:42:01 PM PDT 24
Peak memory 229412 kb
Host smart-32c575a0-edeb-4572-86c5-a6117a490add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070418757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1070418757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.1970256365
Short name T665
Test name
Test status
Simulation time 22125556798 ps
CPU time 336.83 seconds
Started Jul 15 06:40:26 PM PDT 24
Finished Jul 15 06:46:03 PM PDT 24
Peak memory 228460 kb
Host smart-b2d84ce5-a482-498f-9580-865cf1426a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970256365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1970256365 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.1137772145
Short name T870
Test name
Test status
Simulation time 1983492245 ps
CPU time 31.4 seconds
Started Jul 15 06:40:42 PM PDT 24
Finished Jul 15 06:41:13 PM PDT 24
Peak memory 219352 kb
Host smart-413b94b8-c7fa-4f56-ab80-67753403b81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137772145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1137772145 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.4041448129
Short name T740
Test name
Test status
Simulation time 20988187291 ps
CPU time 215.81 seconds
Started Jul 15 06:40:41 PM PDT 24
Finished Jul 15 06:44:17 PM PDT 24
Peak memory 248440 kb
Host smart-e2babe2e-6b37-4747-bf6a-390c6cab3599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041448129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4041448129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.3125177098
Short name T575
Test name
Test status
Simulation time 4462643454 ps
CPU time 5.75 seconds
Started Jul 15 06:40:41 PM PDT 24
Finished Jul 15 06:40:48 PM PDT 24
Peak memory 207424 kb
Host smart-9dba0382-a5ac-4379-921d-93a3d750955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125177098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3125177098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.1799713372
Short name T33
Test name
Test status
Simulation time 93998394 ps
CPU time 1.35 seconds
Started Jul 15 06:40:39 PM PDT 24
Finished Jul 15 06:40:41 PM PDT 24
Peak memory 215616 kb
Host smart-de96e436-f3c2-4a7a-8594-4a6a239d7ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799713372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1799713372 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1536548299
Short name T82
Test name
Test status
Simulation time 423180408555 ps
CPU time 1345.9 seconds
Started Jul 15 06:40:30 PM PDT 24
Finished Jul 15 07:02:56 PM PDT 24
Peak memory 355868 kb
Host smart-4143c1ec-30bb-408f-8fb0-985f73006a98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536548299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1536548299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.3669506335
Short name T789
Test name
Test status
Simulation time 4488545280 ps
CPU time 331.25 seconds
Started Jul 15 06:40:30 PM PDT 24
Finished Jul 15 06:46:01 PM PDT 24
Peak memory 247304 kb
Host smart-7515e9cc-2d00-4731-b71a-90704fef97fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669506335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3669506335 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1853753298
Short name T709
Test name
Test status
Simulation time 961378015 ps
CPU time 45.89 seconds
Started Jul 15 06:40:27 PM PDT 24
Finished Jul 15 06:41:13 PM PDT 24
Peak memory 218636 kb
Host smart-eb275046-7399-4c87-aa24-8251ed6ad878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853753298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1853753298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.3767652069
Short name T747
Test name
Test status
Simulation time 11331498025 ps
CPU time 345.87 seconds
Started Jul 15 06:40:47 PM PDT 24
Finished Jul 15 06:46:34 PM PDT 24
Peak memory 304428 kb
Host smart-007bd861-b49c-4761-93f0-08495320869c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3767652069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3767652069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.3545052210
Short name T289
Test name
Test status
Simulation time 969525060 ps
CPU time 4.9 seconds
Started Jul 15 06:40:38 PM PDT 24
Finished Jul 15 06:40:44 PM PDT 24
Peak memory 215596 kb
Host smart-de355de6-e493-4fc0-8641-66e1c6d87eb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545052210 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.3545052210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.3341285203
Short name T273
Test name
Test status
Simulation time 650864741 ps
CPU time 4.27 seconds
Started Jul 15 06:40:36 PM PDT 24
Finished Jul 15 06:40:41 PM PDT 24
Peak memory 215600 kb
Host smart-c017bc0b-3503-44de-83f6-cad6ffad58ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341285203 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.3341285203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.349875855
Short name T750
Test name
Test status
Simulation time 67071556671 ps
CPU time 1823.15 seconds
Started Jul 15 06:40:26 PM PDT 24
Finished Jul 15 07:10:50 PM PDT 24
Peak memory 392692 kb
Host smart-373d6f6e-cebf-4db4-865f-48e21e84b8f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=349875855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.349875855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.1340623008
Short name T194
Test name
Test status
Simulation time 18320416636 ps
CPU time 1419.81 seconds
Started Jul 15 06:40:29 PM PDT 24
Finished Jul 15 07:04:09 PM PDT 24
Peak memory 378460 kb
Host smart-3b381285-6e2f-4e56-9d32-77e3da7879af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1340623008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.1340623008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.1345830461
Short name T646
Test name
Test status
Simulation time 13991282830 ps
CPU time 1084.29 seconds
Started Jul 15 06:40:27 PM PDT 24
Finished Jul 15 06:58:32 PM PDT 24
Peak memory 331020 kb
Host smart-b50c14a9-e198-456e-a505-c13ade3a93f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1345830461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.1345830461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.217628912
Short name T909
Test name
Test status
Simulation time 12518462221 ps
CPU time 829.25 seconds
Started Jul 15 06:40:33 PM PDT 24
Finished Jul 15 06:54:23 PM PDT 24
Peak memory 294940 kb
Host smart-208dd13e-355a-47cf-967e-a29e94cc76bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=217628912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.217628912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.3408846019
Short name T430
Test name
Test status
Simulation time 172588167780 ps
CPU time 4763.51 seconds
Started Jul 15 06:40:33 PM PDT 24
Finished Jul 15 07:59:57 PM PDT 24
Peak memory 653972 kb
Host smart-246607c5-2ca3-4d5d-9095-30925ae22301
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3408846019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.3408846019 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.1863460457
Short name T541
Test name
Test status
Simulation time 85809285220 ps
CPU time 3382.51 seconds
Started Jul 15 06:40:32 PM PDT 24
Finished Jul 15 07:36:55 PM PDT 24
Peak memory 555972 kb
Host smart-8c425e89-7ca4-4198-a849-277a1d253d23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1863460457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1863460457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.3596000332
Short name T661
Test name
Test status
Simulation time 17016681 ps
CPU time 0.78 seconds
Started Jul 15 06:41:12 PM PDT 24
Finished Jul 15 06:41:13 PM PDT 24
Peak memory 205296 kb
Host smart-0f074957-e236-4036-8f07-7bc5118569bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596000332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3596000332 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.4278144248
Short name T695
Test name
Test status
Simulation time 4177731681 ps
CPU time 248.32 seconds
Started Jul 15 06:41:10 PM PDT 24
Finished Jul 15 06:45:18 PM PDT 24
Peak memory 244608 kb
Host smart-c721d03c-c32c-4d77-b7b0-7a6736299b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278144248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4278144248 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.1335312566
Short name T15
Test name
Test status
Simulation time 140117578566 ps
CPU time 882.99 seconds
Started Jul 15 06:40:54 PM PDT 24
Finished Jul 15 06:55:37 PM PDT 24
Peak memory 232924 kb
Host smart-bcde3c34-5d2d-4021-b87e-5d825a00fe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335312566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1335312566 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.2072462216
Short name T879
Test name
Test status
Simulation time 8221221635 ps
CPU time 130.55 seconds
Started Jul 15 06:41:09 PM PDT 24
Finished Jul 15 06:43:20 PM PDT 24
Peak memory 232072 kb
Host smart-ac9e9ef0-e395-49d5-8531-0cb6c6408e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072462216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2072462216 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.3100842608
Short name T157
Test name
Test status
Simulation time 2256856907 ps
CPU time 85.94 seconds
Started Jul 15 06:41:08 PM PDT 24
Finished Jul 15 06:42:34 PM PDT 24
Peak memory 240292 kb
Host smart-684f075c-aa85-414d-b2b9-972b9d49358f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100842608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3100842608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.2684754591
Short name T1054
Test name
Test status
Simulation time 2034958914 ps
CPU time 3.68 seconds
Started Jul 15 06:41:09 PM PDT 24
Finished Jul 15 06:41:12 PM PDT 24
Peak memory 207360 kb
Host smart-10a83499-4267-48cb-9714-7d57cd5749e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684754591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2684754591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.3813854631
Short name T34
Test name
Test status
Simulation time 122211176 ps
CPU time 1.51 seconds
Started Jul 15 06:41:09 PM PDT 24
Finished Jul 15 06:41:11 PM PDT 24
Peak memory 217920 kb
Host smart-5d799499-75b1-4933-a41b-4f5aab25f52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813854631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3813854631 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.3062846739
Short name T335
Test name
Test status
Simulation time 91650622362 ps
CPU time 693.05 seconds
Started Jul 15 06:40:47 PM PDT 24
Finished Jul 15 06:52:21 PM PDT 24
Peak memory 282624 kb
Host smart-727b13bd-333c-42af-b84d-8dc381a957ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062846739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.3062846739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.1830876404
Short name T943
Test name
Test status
Simulation time 85481091256 ps
CPU time 183.04 seconds
Started Jul 15 06:40:55 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 231724 kb
Host smart-07602fe9-ac60-4a19-85d2-df19ad4363c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830876404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1830876404 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.1972389894
Short name T845
Test name
Test status
Simulation time 5079496313 ps
CPU time 40.5 seconds
Started Jul 15 06:40:46 PM PDT 24
Finished Jul 15 06:41:27 PM PDT 24
Peak memory 221728 kb
Host smart-c21aa053-a8f1-42e5-957b-ea1cffad97f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972389894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1972389894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.1335654038
Short name T647
Test name
Test status
Simulation time 749218743177 ps
CPU time 1182.47 seconds
Started Jul 15 06:41:13 PM PDT 24
Finished Jul 15 07:00:56 PM PDT 24
Peak memory 299564 kb
Host smart-eea4158d-ef2f-469b-8f53-23554fbef637
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1335654038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1335654038 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.878302716
Short name T1048
Test name
Test status
Simulation time 981775599 ps
CPU time 4.95 seconds
Started Jul 15 06:40:59 PM PDT 24
Finished Jul 15 06:41:04 PM PDT 24
Peak memory 215584 kb
Host smart-011eba5c-829d-4fb2-8ff9-11eda4fcec5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878302716 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.kmac_test_vectors_kmac.878302716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.2841039704
Short name T822
Test name
Test status
Simulation time 227938564 ps
CPU time 4.3 seconds
Started Jul 15 06:41:11 PM PDT 24
Finished Jul 15 06:41:15 PM PDT 24
Peak memory 215700 kb
Host smart-ef7afa48-ca28-4e73-843a-59d154b1d4a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841039704 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.2841039704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.772998518
Short name T701
Test name
Test status
Simulation time 133805985451 ps
CPU time 1796.56 seconds
Started Jul 15 06:40:53 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 395764 kb
Host smart-6c1c8d57-ddf8-4805-bbfa-feee5b1112e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=772998518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.772998518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.563710020
Short name T353
Test name
Test status
Simulation time 128807646126 ps
CPU time 1747.04 seconds
Started Jul 15 06:40:54 PM PDT 24
Finished Jul 15 07:10:01 PM PDT 24
Peak memory 370616 kb
Host smart-b1d7b02d-7a31-4683-a6cb-fced8489903c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=563710020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.563710020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1552062767
Short name T285
Test name
Test status
Simulation time 297425023101 ps
CPU time 1538.7 seconds
Started Jul 15 06:40:59 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 339192 kb
Host smart-7af789bd-2e25-41b5-95ad-f7852219e37f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1552062767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1552062767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.531085561
Short name T412
Test name
Test status
Simulation time 39660132479 ps
CPU time 763.16 seconds
Started Jul 15 06:40:59 PM PDT 24
Finished Jul 15 06:53:42 PM PDT 24
Peak memory 294980 kb
Host smart-b3ec8234-95a6-429f-9b87-f4a9aaae2cd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=531085561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.531085561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.3287795489
Short name T893
Test name
Test status
Simulation time 1217671072306 ps
CPU time 5014.04 seconds
Started Jul 15 06:40:59 PM PDT 24
Finished Jul 15 08:04:34 PM PDT 24
Peak memory 640884 kb
Host smart-40d9485d-afb2-4802-93ed-7d6ec48c2256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3287795489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3287795489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.2973865622
Short name T801
Test name
Test status
Simulation time 176716943132 ps
CPU time 3217 seconds
Started Jul 15 06:41:00 PM PDT 24
Finished Jul 15 07:34:38 PM PDT 24
Peak memory 543464 kb
Host smart-be7fca67-6310-491d-bae5-360853aacb32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2973865622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.2973865622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.2962634804
Short name T52
Test name
Test status
Simulation time 13986927 ps
CPU time 0.81 seconds
Started Jul 15 06:41:29 PM PDT 24
Finished Jul 15 06:41:30 PM PDT 24
Peak memory 205308 kb
Host smart-be5e3109-27f5-4989-bcff-c87d7bf83db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962634804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2962634804 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.2567892200
Short name T1028
Test name
Test status
Simulation time 57778636994 ps
CPU time 211.21 seconds
Started Jul 15 06:41:18 PM PDT 24
Finished Jul 15 06:44:50 PM PDT 24
Peak memory 237556 kb
Host smart-3f1d542a-f490-4a01-adcc-312fd5d7e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567892200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2567892200 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.3356998731
Short name T138
Test name
Test status
Simulation time 55981973574 ps
CPU time 677.92 seconds
Started Jul 15 06:41:14 PM PDT 24
Finished Jul 15 06:52:32 PM PDT 24
Peak memory 231288 kb
Host smart-814af3e6-56c1-46dd-a6bc-c5e6811adf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356998731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3356998731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1862666905
Short name T733
Test name
Test status
Simulation time 34065996352 ps
CPU time 249.61 seconds
Started Jul 15 06:41:21 PM PDT 24
Finished Jul 15 06:45:30 PM PDT 24
Peak memory 243856 kb
Host smart-00655aa8-44ee-49c4-951f-adc7ab6565d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862666905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1862666905 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.3092770778
Short name T329
Test name
Test status
Simulation time 20678544250 ps
CPU time 371.61 seconds
Started Jul 15 06:41:20 PM PDT 24
Finished Jul 15 06:47:32 PM PDT 24
Peak memory 264880 kb
Host smart-26ca5aae-6661-442b-ac67-887c6a91a8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092770778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3092770778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.411501843
Short name T58
Test name
Test status
Simulation time 989230588 ps
CPU time 19.24 seconds
Started Jul 15 06:41:25 PM PDT 24
Finished Jul 15 06:41:44 PM PDT 24
Peak memory 232052 kb
Host smart-5b5372a7-42ef-42a3-943f-2e3aac6a19f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411501843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.411501843 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.2164968373
Short name T593
Test name
Test status
Simulation time 77658481582 ps
CPU time 2287.75 seconds
Started Jul 15 06:41:15 PM PDT 24
Finished Jul 15 07:19:24 PM PDT 24
Peak memory 448044 kb
Host smart-59d152a8-9a1f-451f-8471-45fb5d619656
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164968373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.2164968373 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3304822524
Short name T503
Test name
Test status
Simulation time 3472092035 ps
CPU time 100.22 seconds
Started Jul 15 06:41:15 PM PDT 24
Finished Jul 15 06:42:56 PM PDT 24
Peak memory 225992 kb
Host smart-7757ef55-12e1-4952-8aac-8f56baca88ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304822524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3304822524 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.2269989456
Short name T1055
Test name
Test status
Simulation time 3647024561 ps
CPU time 68.97 seconds
Started Jul 15 06:41:13 PM PDT 24
Finished Jul 15 06:42:22 PM PDT 24
Peak memory 218896 kb
Host smart-0a01eb37-4565-4ca8-91eb-64eac304671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269989456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2269989456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.4192015496
Short name T604
Test name
Test status
Simulation time 49378572654 ps
CPU time 760.48 seconds
Started Jul 15 06:41:28 PM PDT 24
Finished Jul 15 06:54:09 PM PDT 24
Peak memory 354324 kb
Host smart-be9cb6d3-db49-4351-9947-c04a11153466
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4192015496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.4192015496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.3557199079
Short name T819
Test name
Test status
Simulation time 971525998 ps
CPU time 5.66 seconds
Started Jul 15 06:41:17 PM PDT 24
Finished Jul 15 06:41:23 PM PDT 24
Peak memory 215592 kb
Host smart-92f3e2ee-7b8c-4582-ad64-ca2ada407e39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557199079 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.3557199079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2090147360
Short name T838
Test name
Test status
Simulation time 217948755 ps
CPU time 4.68 seconds
Started Jul 15 06:41:19 PM PDT 24
Finished Jul 15 06:41:24 PM PDT 24
Peak memory 215672 kb
Host smart-ef703ec1-e91b-42d2-b998-76d9cde098c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090147360 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2090147360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.1360750010
Short name T1
Test name
Test status
Simulation time 268798167893 ps
CPU time 1775.19 seconds
Started Jul 15 06:41:15 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 389976 kb
Host smart-91a0cb1f-43e7-41d1-b52f-e6e489c3c798
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1360750010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.1360750010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.1157901447
Short name T974
Test name
Test status
Simulation time 495363961650 ps
CPU time 1888.86 seconds
Started Jul 15 06:41:15 PM PDT 24
Finished Jul 15 07:12:44 PM PDT 24
Peak memory 373104 kb
Host smart-96ab8cdf-e980-45d3-b259-0827a89f0af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1157901447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.1157901447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.1836250046
Short name T387
Test name
Test status
Simulation time 98881861421 ps
CPU time 1172.52 seconds
Started Jul 15 06:41:16 PM PDT 24
Finished Jul 15 07:00:49 PM PDT 24
Peak memory 338444 kb
Host smart-50e9f898-8f22-44a3-8b1b-7426bc61cbfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1836250046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.1836250046 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.2922339949
Short name T216
Test name
Test status
Simulation time 122087037670 ps
CPU time 933.43 seconds
Started Jul 15 06:41:18 PM PDT 24
Finished Jul 15 06:56:52 PM PDT 24
Peak memory 296372 kb
Host smart-156fe345-cff9-4461-9634-b960f4ed1695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2922339949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.2922339949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.2467826912
Short name T686
Test name
Test status
Simulation time 521802995093 ps
CPU time 4335.45 seconds
Started Jul 15 06:41:15 PM PDT 24
Finished Jul 15 07:53:31 PM PDT 24
Peak memory 651460 kb
Host smart-b29bb9c0-3b1e-4710-a42d-111590b7dd88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2467826912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2467826912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.1807663316
Short name T1056
Test name
Test status
Simulation time 88340902415 ps
CPU time 3384.06 seconds
Started Jul 15 06:41:13 PM PDT 24
Finished Jul 15 07:37:38 PM PDT 24
Peak memory 562216 kb
Host smart-1568e122-bc10-44d3-b7ad-b926376ad36a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1807663316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1807663316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.1407352110
Short name T408
Test name
Test status
Simulation time 13890608 ps
CPU time 0.75 seconds
Started Jul 15 06:41:49 PM PDT 24
Finished Jul 15 06:41:50 PM PDT 24
Peak memory 205300 kb
Host smart-8f0c981c-7444-4163-90f1-e00ee34c3208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407352110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1407352110 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.2765468145
Short name T112
Test name
Test status
Simulation time 28570491328 ps
CPU time 197.64 seconds
Started Jul 15 06:41:42 PM PDT 24
Finished Jul 15 06:45:00 PM PDT 24
Peak memory 241500 kb
Host smart-672f483d-7418-4f4b-a40a-772e7496e5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765468145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2765468145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.804022380
Short name T913
Test name
Test status
Simulation time 4514284087 ps
CPU time 174.69 seconds
Started Jul 15 06:41:39 PM PDT 24
Finished Jul 15 06:44:34 PM PDT 24
Peak memory 225500 kb
Host smart-2e231ad5-f7c7-42b1-8f03-a5c2de718735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804022380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.804022380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.3918460790
Short name T359
Test name
Test status
Simulation time 14440324911 ps
CPU time 258.38 seconds
Started Jul 15 06:41:44 PM PDT 24
Finished Jul 15 06:46:02 PM PDT 24
Peak memory 243564 kb
Host smart-0c0f31c9-6a94-4624-96d8-33cd30cd08d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918460790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3918460790 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.1954793557
Short name T517
Test name
Test status
Simulation time 9006784653 ps
CPU time 66.96 seconds
Started Jul 15 06:41:48 PM PDT 24
Finished Jul 15 06:42:56 PM PDT 24
Peak memory 240240 kb
Host smart-f666d301-27da-4f21-b8a8-e5a760907a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954793557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1954793557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.1819516772
Short name T929
Test name
Test status
Simulation time 4860184643 ps
CPU time 5.01 seconds
Started Jul 15 06:41:49 PM PDT 24
Finished Jul 15 06:41:54 PM PDT 24
Peak memory 207412 kb
Host smart-8b766c44-9045-44bc-bdae-ff189774c0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819516772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1819516772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.1061618966
Short name T5
Test name
Test status
Simulation time 36891263 ps
CPU time 1.41 seconds
Started Jul 15 06:41:50 PM PDT 24
Finished Jul 15 06:41:52 PM PDT 24
Peak memory 217568 kb
Host smart-73c643ff-1c92-44bd-8c20-5768813baa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061618966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1061618966 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.331961535
Short name T192
Test name
Test status
Simulation time 5533519189 ps
CPU time 456.82 seconds
Started Jul 15 06:41:31 PM PDT 24
Finished Jul 15 06:49:08 PM PDT 24
Peak memory 268564 kb
Host smart-af3bf41d-a799-4237-a3c4-4a3e5faba5cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331961535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_an
d_output.331961535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.4112952108
Short name T1072
Test name
Test status
Simulation time 14773183273 ps
CPU time 268.38 seconds
Started Jul 15 06:41:33 PM PDT 24
Finished Jul 15 06:46:01 PM PDT 24
Peak memory 244836 kb
Host smart-52dbbd6f-0e3a-4e15-bed3-1ddfe06de249
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112952108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.4112952108 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.3534559379
Short name T71
Test name
Test status
Simulation time 7343798558 ps
CPU time 28.87 seconds
Started Jul 15 06:41:33 PM PDT 24
Finished Jul 15 06:42:02 PM PDT 24
Peak memory 219140 kb
Host smart-009c141d-5985-4a88-8195-190e969b7ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534559379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.3534559379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.699725128
Short name T580
Test name
Test status
Simulation time 7059391091 ps
CPU time 581.61 seconds
Started Jul 15 06:41:49 PM PDT 24
Finished Jul 15 06:51:31 PM PDT 24
Peak memory 298616 kb
Host smart-467094c5-0cec-465e-a8ad-7553fe06d2f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=699725128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.699725128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.3572803576
Short name T868
Test name
Test status
Simulation time 68234662 ps
CPU time 4.52 seconds
Started Jul 15 06:41:43 PM PDT 24
Finished Jul 15 06:41:47 PM PDT 24
Peak memory 215636 kb
Host smart-a6accc4e-ab59-4df0-98df-22aab8a55587
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572803576 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.3572803576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3762186782
Short name T629
Test name
Test status
Simulation time 237967514 ps
CPU time 4.18 seconds
Started Jul 15 06:41:45 PM PDT 24
Finished Jul 15 06:41:49 PM PDT 24
Peak memory 215620 kb
Host smart-8df7222f-7c1d-498f-9f4f-74a73c9994b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762186782 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3762186782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.3558646155
Short name T996
Test name
Test status
Simulation time 133852651847 ps
CPU time 1847.05 seconds
Started Jul 15 06:41:37 PM PDT 24
Finished Jul 15 07:12:24 PM PDT 24
Peak memory 396072 kb
Host smart-4adbbe29-a807-44ce-ac21-d2f81cb904b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3558646155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3558646155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.2355028953
Short name T495
Test name
Test status
Simulation time 35702194987 ps
CPU time 1515.2 seconds
Started Jul 15 06:41:36 PM PDT 24
Finished Jul 15 07:06:52 PM PDT 24
Peak memory 375904 kb
Host smart-29a14384-e85a-4084-8943-6dbe22a14121
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2355028953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2355028953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.3881814330
Short name T195
Test name
Test status
Simulation time 48093531271 ps
CPU time 1259.24 seconds
Started Jul 15 06:41:38 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 330464 kb
Host smart-a5e4c544-df44-4c48-b8b2-fd0ba918cac2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3881814330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.3881814330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.2941752757
Short name T771
Test name
Test status
Simulation time 9949525991 ps
CPU time 786.79 seconds
Started Jul 15 06:41:44 PM PDT 24
Finished Jul 15 06:54:51 PM PDT 24
Peak memory 295472 kb
Host smart-bc1c6c17-84b8-4d7a-89a8-f7621b199888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2941752757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.2941752757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.721816285
Short name T3
Test name
Test status
Simulation time 300895975540 ps
CPU time 4043.26 seconds
Started Jul 15 06:41:45 PM PDT 24
Finished Jul 15 07:49:09 PM PDT 24
Peak memory 656324 kb
Host smart-7936ad27-6eb8-450e-938e-27c01400bce7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=721816285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.721816285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3969266326
Short name T325
Test name
Test status
Simulation time 189601395824 ps
CPU time 3767.17 seconds
Started Jul 15 06:41:44 PM PDT 24
Finished Jul 15 07:44:31 PM PDT 24
Peak memory 558164 kb
Host smart-bbc9acf1-87b6-452a-8791-0facba6ace67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3969266326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3969266326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1750091709
Short name T675
Test name
Test status
Simulation time 38026132 ps
CPU time 0.79 seconds
Started Jul 15 06:32:54 PM PDT 24
Finished Jul 15 06:32:55 PM PDT 24
Peak memory 205316 kb
Host smart-8cd94066-d514-4f57-98c2-a5b5053165f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750091709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1750091709 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.3135629316
Short name T858
Test name
Test status
Simulation time 9586480572 ps
CPU time 221.68 seconds
Started Jul 15 06:32:53 PM PDT 24
Finished Jul 15 06:36:35 PM PDT 24
Peak memory 241932 kb
Host smart-1a8f2995-5ec0-4491-a304-1fd27eb78f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135629316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3135629316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.1937278669
Short name T38
Test name
Test status
Simulation time 3720892770 ps
CPU time 58.38 seconds
Started Jul 15 06:32:54 PM PDT 24
Finished Jul 15 06:33:53 PM PDT 24
Peak memory 224016 kb
Host smart-bcf72a88-268c-40ec-a8ae-401ec899179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937278669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1937278669 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.216835045
Short name T324
Test name
Test status
Simulation time 824074402 ps
CPU time 12.07 seconds
Started Jul 15 06:32:54 PM PDT 24
Finished Jul 15 06:33:07 PM PDT 24
Peak memory 217676 kb
Host smart-2ab1b6a6-309d-4740-90e0-4e2d28c9aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216835045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.216835045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.2860867995
Short name T505
Test name
Test status
Simulation time 5766138270 ps
CPU time 29.08 seconds
Started Jul 15 06:32:56 PM PDT 24
Finished Jul 15 06:33:25 PM PDT 24
Peak memory 223644 kb
Host smart-675281cd-36e9-4e8a-87af-585976d77523
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2860867995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2860867995 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1691040761
Short name T1043
Test name
Test status
Simulation time 7389325935 ps
CPU time 22.9 seconds
Started Jul 15 06:33:00 PM PDT 24
Finished Jul 15 06:33:23 PM PDT 24
Peak memory 218728 kb
Host smart-dd9c67c7-ac0e-4301-82b6-1b691369995f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1691040761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1691040761 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.3603629523
Short name T46
Test name
Test status
Simulation time 25479343963 ps
CPU time 53.93 seconds
Started Jul 15 06:32:58 PM PDT 24
Finished Jul 15 06:33:52 PM PDT 24
Peak memory 215656 kb
Host smart-71f4d8d3-daae-4194-85ed-406f9e864731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603629523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3603629523 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.4051422408
Short name T710
Test name
Test status
Simulation time 28158440730 ps
CPU time 266.64 seconds
Started Jul 15 06:32:56 PM PDT 24
Finished Jul 15 06:37:23 PM PDT 24
Peak memory 243888 kb
Host smart-835e4e70-3b97-4eb8-bf19-7a0f1b39486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051422408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.4051422408 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.3883122895
Short name T635
Test name
Test status
Simulation time 1461378145 ps
CPU time 57.63 seconds
Started Jul 15 06:33:01 PM PDT 24
Finished Jul 15 06:33:59 PM PDT 24
Peak memory 240164 kb
Host smart-8efdac8b-2405-41c8-95bc-4e93b239c38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883122895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3883122895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.3359313309
Short name T679
Test name
Test status
Simulation time 5288713644 ps
CPU time 6.69 seconds
Started Jul 15 06:32:54 PM PDT 24
Finished Jul 15 06:33:02 PM PDT 24
Peak memory 207452 kb
Host smart-8062675f-b195-4681-8566-9a89b7ace2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359313309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3359313309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.1459054059
Short name T576
Test name
Test status
Simulation time 165880657 ps
CPU time 1.47 seconds
Started Jul 15 06:32:53 PM PDT 24
Finished Jul 15 06:32:55 PM PDT 24
Peak memory 220252 kb
Host smart-037cb000-a718-4f62-af42-b4f846cecdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459054059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1459054059 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1117540431
Short name T815
Test name
Test status
Simulation time 52506860494 ps
CPU time 1591.35 seconds
Started Jul 15 06:32:54 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 370372 kb
Host smart-cd55012a-b5c0-40fd-a218-675fdd02330b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117540431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1117540431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.2699117193
Short name T774
Test name
Test status
Simulation time 4847712964 ps
CPU time 77.79 seconds
Started Jul 15 06:32:55 PM PDT 24
Finished Jul 15 06:34:14 PM PDT 24
Peak memory 227640 kb
Host smart-599c00e7-bc8d-4cc2-89ae-40158cc706b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699117193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2699117193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.2657821832
Short name T264
Test name
Test status
Simulation time 28749047343 ps
CPU time 123.44 seconds
Started Jul 15 06:33:01 PM PDT 24
Finished Jul 15 06:35:05 PM PDT 24
Peak memory 230380 kb
Host smart-dc14f8eb-1395-4b57-a6e1-235df798aef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657821832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2657821832 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.2239858977
Short name T1064
Test name
Test status
Simulation time 668332583 ps
CPU time 17.41 seconds
Started Jul 15 06:32:55 PM PDT 24
Finished Jul 15 06:33:13 PM PDT 24
Peak memory 215932 kb
Host smart-e89cfdee-88b7-4250-a99c-de773288578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239858977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2239858977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.227364602
Short name T876
Test name
Test status
Simulation time 3825761793 ps
CPU time 300.41 seconds
Started Jul 15 06:32:53 PM PDT 24
Finished Jul 15 06:37:54 PM PDT 24
Peak memory 273232 kb
Host smart-d60319cf-026a-4e26-b4e8-9f9b6c73ca72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=227364602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.227364602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.1662043802
Short name T376
Test name
Test status
Simulation time 1019586651 ps
CPU time 5.48 seconds
Started Jul 15 06:32:57 PM PDT 24
Finished Jul 15 06:33:03 PM PDT 24
Peak memory 215776 kb
Host smart-d30f9b16-4d65-4b9b-a00b-2eb9aef36a45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662043802 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.1662043802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3350483307
Short name T1013
Test name
Test status
Simulation time 945196691 ps
CPU time 5.01 seconds
Started Jul 15 06:32:54 PM PDT 24
Finished Jul 15 06:33:00 PM PDT 24
Peak memory 215720 kb
Host smart-7fc4624c-c663-4d72-8d18-6d9443e70c2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350483307 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3350483307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.151520369
Short name T878
Test name
Test status
Simulation time 93891200166 ps
CPU time 1535.98 seconds
Started Jul 15 06:33:00 PM PDT 24
Finished Jul 15 06:58:37 PM PDT 24
Peak memory 390452 kb
Host smart-b5c45251-55e9-441e-a597-a3d436496eeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=151520369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.151520369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.2891822337
Short name T1058
Test name
Test status
Simulation time 36516128937 ps
CPU time 1525.26 seconds
Started Jul 15 06:32:53 PM PDT 24
Finished Jul 15 06:58:19 PM PDT 24
Peak memory 377392 kb
Host smart-5013d00d-b3c6-482b-9b15-36ceb0d2c37d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2891822337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.2891822337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.196355381
Short name T808
Test name
Test status
Simulation time 97284827483 ps
CPU time 1093.98 seconds
Started Jul 15 06:32:58 PM PDT 24
Finished Jul 15 06:51:12 PM PDT 24
Peak memory 335036 kb
Host smart-2bbb36c6-38d6-4dc1-a9c1-c62ecc35e0ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=196355381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.196355381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.4067893249
Short name T344
Test name
Test status
Simulation time 32921982412 ps
CPU time 901.73 seconds
Started Jul 15 06:32:53 PM PDT 24
Finished Jul 15 06:47:55 PM PDT 24
Peak memory 296532 kb
Host smart-8fb326a3-1463-4f92-97ac-f1505f5f2a7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4067893249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.4067893249 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.395081506
Short name T413
Test name
Test status
Simulation time 105588009881 ps
CPU time 3843.63 seconds
Started Jul 15 06:33:01 PM PDT 24
Finished Jul 15 07:37:05 PM PDT 24
Peak memory 648060 kb
Host smart-c60d3aa7-908f-4be4-b9d1-0c1de8d00d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=395081506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.395081506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.478335702
Short name T758
Test name
Test status
Simulation time 605373410766 ps
CPU time 3990.61 seconds
Started Jul 15 06:32:56 PM PDT 24
Finished Jul 15 07:39:27 PM PDT 24
Peak memory 561180 kb
Host smart-eb7b3f38-600c-43f6-8bcc-bc93e3c32452
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=478335702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.478335702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.3446608776
Short name T339
Test name
Test status
Simulation time 25521964 ps
CPU time 0.83 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:33:07 PM PDT 24
Peak memory 205252 kb
Host smart-e65e57fa-d974-4bfd-bb3c-888c265599fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446608776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3446608776 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.668964113
Short name T578
Test name
Test status
Simulation time 8745359403 ps
CPU time 83.98 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:34:32 PM PDT 24
Peak memory 226900 kb
Host smart-dd58fb90-0693-4081-94f4-c5a50ae2bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668964113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.668964113 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1168574453
Short name T603
Test name
Test status
Simulation time 3362790337 ps
CPU time 19.83 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 06:33:27 PM PDT 24
Peak memory 223796 kb
Host smart-94e818d6-2313-47a1-9db7-337535cf82e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168574453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1168574453 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.3408026549
Short name T448
Test name
Test status
Simulation time 623552475 ps
CPU time 25.6 seconds
Started Jul 15 06:32:55 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 223816 kb
Host smart-6d010b06-6876-4001-a285-7516144825cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408026549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3408026549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.1452482089
Short name T652
Test name
Test status
Simulation time 517236077 ps
CPU time 37.24 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:33:43 PM PDT 24
Peak memory 223680 kb
Host smart-164168ef-8ad9-438b-8ec8-17be1fcbcb7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1452482089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1452482089 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1589594848
Short name T660
Test name
Test status
Simulation time 2578583310 ps
CPU time 16.77 seconds
Started Jul 15 06:33:02 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 223836 kb
Host smart-22f23e4b-7c4b-454e-994c-72d9eada6893
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1589594848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1589594848 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.4198049955
Short name T792
Test name
Test status
Simulation time 100350721 ps
CPU time 1.93 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:33:11 PM PDT 24
Peak memory 220600 kb
Host smart-7db42512-4425-481b-9add-4d78691a54ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198049955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.4198049955 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.276239060
Short name T567
Test name
Test status
Simulation time 18510896358 ps
CPU time 316.08 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:38:22 PM PDT 24
Peak memory 242756 kb
Host smart-76778297-6515-44c2-a804-71c0eab815d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276239060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.276239060 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.3588626018
Short name T491
Test name
Test status
Simulation time 119275993261 ps
CPU time 366.48 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:39:15 PM PDT 24
Peak memory 256656 kb
Host smart-1402cf12-5171-4fdd-9ad3-8d58b8f34c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588626018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3588626018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.3246700606
Short name T61
Test name
Test status
Simulation time 40432592 ps
CPU time 1.28 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:33:07 PM PDT 24
Peak memory 215480 kb
Host smart-fd380177-1bb2-4eb0-8529-7a817ee11b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246700606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3246700606 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.3027674839
Short name T404
Test name
Test status
Simulation time 42273059280 ps
CPU time 1449.71 seconds
Started Jul 15 06:32:53 PM PDT 24
Finished Jul 15 06:57:04 PM PDT 24
Peak memory 376556 kb
Host smart-a220aee0-36f6-4445-94da-8180fb39f228
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027674839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.3027674839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1602967940
Short name T978
Test name
Test status
Simulation time 6411499932 ps
CPU time 113.02 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:35:00 PM PDT 24
Peak memory 229476 kb
Host smart-60b22702-3bf5-4370-a90f-f45eeb4947f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602967940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1602967940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.527320447
Short name T714
Test name
Test status
Simulation time 15610996046 ps
CPU time 301.5 seconds
Started Jul 15 06:32:53 PM PDT 24
Finished Jul 15 06:37:55 PM PDT 24
Peak memory 244568 kb
Host smart-3ecb622f-3cab-4351-8297-8f277fd052be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527320447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.527320447 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.1753006981
Short name T390
Test name
Test status
Simulation time 4660273984 ps
CPU time 20.26 seconds
Started Jul 15 06:32:52 PM PDT 24
Finished Jul 15 06:33:13 PM PDT 24
Peak memory 223916 kb
Host smart-7665a206-d676-415d-8806-c1f10b38f8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753006981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1753006981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.2020083006
Short name T41
Test name
Test status
Simulation time 17485400913 ps
CPU time 1468.04 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:57:34 PM PDT 24
Peak memory 372652 kb
Host smart-24e708db-be76-4c90-a773-22cab4e49677
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2020083006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2020083006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.626606972
Short name T995
Test name
Test status
Simulation time 1094951024 ps
CPU time 4.71 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 06:33:12 PM PDT 24
Peak memory 215616 kb
Host smart-81d2beb8-05ed-408b-b90a-e72069b0d3f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626606972 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.kmac_test_vectors_kmac.626606972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3109561262
Short name T565
Test name
Test status
Simulation time 69591321 ps
CPU time 4.02 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:33:11 PM PDT 24
Peak memory 208744 kb
Host smart-ed3f35ef-4b0f-4634-865f-766616fcaf5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109561262 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3109561262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.2959615206
Short name T585
Test name
Test status
Simulation time 109755913532 ps
CPU time 1872.95 seconds
Started Jul 15 06:32:52 PM PDT 24
Finished Jul 15 07:04:06 PM PDT 24
Peak memory 374460 kb
Host smart-0fdecfef-9f26-41ae-a675-41cc6d90d89f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2959615206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2959615206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.3197749510
Short name T199
Test name
Test status
Simulation time 17990585081 ps
CPU time 1422.3 seconds
Started Jul 15 06:32:55 PM PDT 24
Finished Jul 15 06:56:38 PM PDT 24
Peak memory 368584 kb
Host smart-463c5cd1-382e-4811-b7e1-ed6319c44c6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3197749510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3197749510 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.3406113103
Short name T850
Test name
Test status
Simulation time 236142170313 ps
CPU time 1330.11 seconds
Started Jul 15 06:32:54 PM PDT 24
Finished Jul 15 06:55:05 PM PDT 24
Peak memory 336912 kb
Host smart-b6b1caeb-3a0f-4ec8-a5ac-5be80556916f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3406113103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.3406113103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.1289921021
Short name T934
Test name
Test status
Simulation time 20694744943 ps
CPU time 757.3 seconds
Started Jul 15 06:32:54 PM PDT 24
Finished Jul 15 06:45:33 PM PDT 24
Peak memory 295608 kb
Host smart-cb237d55-8f49-4315-b674-cfb0110159c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1289921021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.1289921021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.26119990
Short name T443
Test name
Test status
Simulation time 101286201621 ps
CPU time 3825.66 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 07:36:54 PM PDT 24
Peak memory 644864 kb
Host smart-c7c8dd46-6500-4c73-b3ee-f88c60164877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=26119990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.26119990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1094702583
Short name T1060
Test name
Test status
Simulation time 553168150916 ps
CPU time 4044.82 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 07:40:31 PM PDT 24
Peak memory 552480 kb
Host smart-101269c7-3dbf-4a7c-b5a0-c35b90ce015e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1094702583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1094702583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.4150092300
Short name T258
Test name
Test status
Simulation time 45305659 ps
CPU time 0.77 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:33:12 PM PDT 24
Peak memory 205088 kb
Host smart-e762da6a-f9ad-42d7-b29d-8edba620d7d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150092300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.4150092300 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.471984844
Short name T1067
Test name
Test status
Simulation time 7187526517 ps
CPU time 134.41 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:35:23 PM PDT 24
Peak memory 234900 kb
Host smart-1ad65080-7b8d-4bea-bcc4-b9ff072e67a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471984844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.471984844 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2990984260
Short name T1007
Test name
Test status
Simulation time 45780049588 ps
CPU time 232.97 seconds
Started Jul 15 06:33:09 PM PDT 24
Finished Jul 15 06:37:04 PM PDT 24
Peak memory 242248 kb
Host smart-abe1e557-31f2-4888-93f8-12e0b76442e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990984260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2990984260 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.2525879890
Short name T434
Test name
Test status
Simulation time 64247179614 ps
CPU time 826.37 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:46:55 PM PDT 24
Peak memory 232444 kb
Host smart-b931e56f-883b-47db-aac1-ab0b4d0cdfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525879890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2525879890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.3095570749
Short name T485
Test name
Test status
Simulation time 1311245065 ps
CPU time 26.55 seconds
Started Jul 15 06:33:06 PM PDT 24
Finished Jul 15 06:33:36 PM PDT 24
Peak memory 219528 kb
Host smart-5897c8d4-aeb1-4e4a-ae19-03217228862a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095570749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3095570749 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.4165392088
Short name T700
Test name
Test status
Simulation time 5591287642 ps
CPU time 26.78 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:33:38 PM PDT 24
Peak memory 225704 kb
Host smart-ef67fdda-18dc-4c0d-8e7c-994fe07bd86a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4165392088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.4165392088 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.787187978
Short name T692
Test name
Test status
Simulation time 19177075620 ps
CPU time 17.44 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:33:26 PM PDT 24
Peak memory 215656 kb
Host smart-33781f2f-654d-437e-a7d3-082814f13391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787187978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.787187978 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.3498077658
Short name T432
Test name
Test status
Simulation time 41960918943 ps
CPU time 166.77 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 06:35:55 PM PDT 24
Peak memory 235240 kb
Host smart-1b2adf6e-28f5-440f-a96a-845544164322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498077658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3498077658 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.1744379947
Short name T27
Test name
Test status
Simulation time 2357945081 ps
CPU time 47.33 seconds
Started Jul 15 06:33:06 PM PDT 24
Finished Jul 15 06:33:57 PM PDT 24
Peak memory 239504 kb
Host smart-c769e6c0-cd2b-4d3f-b428-df9cd54ecff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744379947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1744379947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.539227928
Short name T846
Test name
Test status
Simulation time 674455440 ps
CPU time 3.5 seconds
Started Jul 15 06:33:07 PM PDT 24
Finished Jul 15 06:33:13 PM PDT 24
Peak memory 207204 kb
Host smart-e4fd1012-0062-4949-ab79-45241c17c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539227928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.539227928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1767382807
Short name T1032
Test name
Test status
Simulation time 228333569 ps
CPU time 1.25 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:33:10 PM PDT 24
Peak memory 215596 kb
Host smart-b2dc9e55-571c-4fb6-bc46-de1fceeb81ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767382807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1767382807 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.3909846985
Short name T715
Test name
Test status
Simulation time 1102105233557 ps
CPU time 2299.73 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 07:11:27 PM PDT 24
Peak memory 415692 kb
Host smart-ddb99278-aad1-44b6-87a8-798894f99c83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909846985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.3909846985 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.2488580350
Short name T552
Test name
Test status
Simulation time 31924111021 ps
CPU time 177.21 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:36:06 PM PDT 24
Peak memory 235268 kb
Host smart-c764b6cd-6b9c-4400-90b6-bd28a9c4461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488580350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2488580350 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.2519168123
Short name T667
Test name
Test status
Simulation time 22681611787 ps
CPU time 313.19 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 06:38:21 PM PDT 24
Peak memory 243912 kb
Host smart-f53295b3-137d-4c4a-927c-c6dcbb6c5bb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519168123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2519168123 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.93568713
Short name T198
Test name
Test status
Simulation time 5860496575 ps
CPU time 14.99 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 219476 kb
Host smart-db269412-b925-4cfd-b6a9-74c1f30ea111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93568713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.93568713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.821051971
Short name T155
Test name
Test status
Simulation time 199669603536 ps
CPU time 1337.61 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 06:55:26 PM PDT 24
Peak memory 395088 kb
Host smart-74541675-4889-40d5-9fdc-dce022e79275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=821051971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.821051971 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.642027144
Short name T601
Test name
Test status
Simulation time 77982368 ps
CPU time 4.09 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:33:10 PM PDT 24
Peak memory 208824 kb
Host smart-a8f08884-6a1a-4ae2-bffb-c3221463c944
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642027144 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.kmac_test_vectors_kmac.642027144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2715677575
Short name T546
Test name
Test status
Simulation time 233051957 ps
CPU time 5.29 seconds
Started Jul 15 06:33:05 PM PDT 24
Finished Jul 15 06:33:14 PM PDT 24
Peak memory 215620 kb
Host smart-0650a95b-8532-48e9-9a0d-c102bd60797c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715677575 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2715677575 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.3469222832
Short name T219
Test name
Test status
Simulation time 66265172898 ps
CPU time 1879.37 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 07:04:28 PM PDT 24
Peak memory 396412 kb
Host smart-94eee0cd-6d30-452d-8c39-833ba7da0890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3469222832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.3469222832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.2132222811
Short name T193
Test name
Test status
Simulation time 147399513341 ps
CPU time 1467.85 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:57:34 PM PDT 24
Peak memory 373540 kb
Host smart-c3aa61a5-d4a7-4b1d-9e8c-a4983c082043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2132222811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.2132222811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.1322692861
Short name T526
Test name
Test status
Simulation time 47383053372 ps
CPU time 1240.14 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:53:46 PM PDT 24
Peak memory 337028 kb
Host smart-412b3e89-c41b-4fbf-9af9-7952e285ed97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1322692861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.1322692861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.1790471290
Short name T208
Test name
Test status
Simulation time 66198679514 ps
CPU time 912.85 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 06:48:20 PM PDT 24
Peak memory 297900 kb
Host smart-0cf30a98-da3c-4658-a023-ba1456db6268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1790471290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1790471290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.368693911
Short name T788
Test name
Test status
Simulation time 180101500504 ps
CPU time 4671.05 seconds
Started Jul 15 06:33:04 PM PDT 24
Finished Jul 15 07:50:58 PM PDT 24
Peak memory 655112 kb
Host smart-99ee8e23-2fcd-4520-98e2-86634a005d8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=368693911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.368693911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.402605186
Short name T330
Test name
Test status
Simulation time 1809538702778 ps
CPU time 4601.14 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 07:49:47 PM PDT 24
Peak memory 558272 kb
Host smart-3ee2bbb0-571b-4f38-af9e-c9d9da15224e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=402605186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.402605186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.2573214635
Short name T423
Test name
Test status
Simulation time 12622329 ps
CPU time 0.76 seconds
Started Jul 15 06:33:15 PM PDT 24
Finished Jul 15 06:33:16 PM PDT 24
Peak memory 205232 kb
Host smart-05e21481-d0d5-4ed9-8507-6b9ecaf5f976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573214635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2573214635 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3360544220
Short name T314
Test name
Test status
Simulation time 87788620006 ps
CPU time 310.04 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:38:22 PM PDT 24
Peak memory 244832 kb
Host smart-9cbed6d6-4f3f-4db2-a977-8043f00c6f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360544220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3360544220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.1369344713
Short name T455
Test name
Test status
Simulation time 5033889938 ps
CPU time 159.93 seconds
Started Jul 15 06:33:03 PM PDT 24
Finished Jul 15 06:35:46 PM PDT 24
Peak memory 237492 kb
Host smart-b3d7aab2-1e57-437f-bdfc-cc9a6efccd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369344713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1369344713 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.2496065570
Short name T1057
Test name
Test status
Simulation time 14493563490 ps
CPU time 446.9 seconds
Started Jul 15 06:33:08 PM PDT 24
Finished Jul 15 06:40:37 PM PDT 24
Peak memory 230404 kb
Host smart-d7a3ba52-9709-40c2-bd36-8d08b18e4a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496065570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2496065570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.30785060
Short name T288
Test name
Test status
Simulation time 5064710997 ps
CPU time 24.42 seconds
Started Jul 15 06:33:08 PM PDT 24
Finished Jul 15 06:33:35 PM PDT 24
Peak memory 223708 kb
Host smart-785d5e98-fd02-41a2-b635-f82e598cd34c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=30785060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.30785060 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2952445215
Short name T183
Test name
Test status
Simulation time 141596589 ps
CPU time 9.86 seconds
Started Jul 15 06:33:09 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 219184 kb
Host smart-cbdeb84c-6a30-41f1-836a-e90d549fc145
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2952445215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2952445215 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.2400567808
Short name T47
Test name
Test status
Simulation time 583757094 ps
CPU time 6.98 seconds
Started Jul 15 06:33:08 PM PDT 24
Finished Jul 15 06:33:17 PM PDT 24
Peak memory 215568 kb
Host smart-dc9c884a-f2b0-4d37-b580-f23303f8df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400567808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2400567808 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.307903210
Short name T520
Test name
Test status
Simulation time 2161670983 ps
CPU time 15.8 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:33:27 PM PDT 24
Peak memory 223780 kb
Host smart-ac32bb4b-ce59-4d8e-b3db-9e3d9b0825a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307903210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.307903210 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_key_error.2516767765
Short name T645
Test name
Test status
Simulation time 9528934660 ps
CPU time 6.74 seconds
Started Jul 15 06:33:11 PM PDT 24
Finished Jul 15 06:33:19 PM PDT 24
Peak memory 215620 kb
Host smart-765ea7eb-4cba-4a4d-ae3a-fc427c5d54d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516767765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2516767765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.2808463373
Short name T259
Test name
Test status
Simulation time 11327003851 ps
CPU time 956.77 seconds
Started Jul 15 06:33:09 PM PDT 24
Finished Jul 15 06:49:08 PM PDT 24
Peak memory 321000 kb
Host smart-36f5c225-8d74-4849-b954-fa5edebf6967
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808463373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.2808463373 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.1342770523
Short name T323
Test name
Test status
Simulation time 12271421524 ps
CPU time 121.79 seconds
Started Jul 15 06:33:07 PM PDT 24
Finished Jul 15 06:35:12 PM PDT 24
Peak memory 232396 kb
Host smart-b5abfeb0-a28c-4200-bfd5-0b14dea30f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342770523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1342770523 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.1242347540
Short name T885
Test name
Test status
Simulation time 23372546787 ps
CPU time 88.45 seconds
Started Jul 15 06:33:06 PM PDT 24
Finished Jul 15 06:34:38 PM PDT 24
Peak memory 226152 kb
Host smart-ca181e69-4e48-4de0-94f2-20df6a50cc77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242347540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1242347540 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.1941720854
Short name T757
Test name
Test status
Simulation time 2351422581 ps
CPU time 41.02 seconds
Started Jul 15 06:33:08 PM PDT 24
Finished Jul 15 06:33:52 PM PDT 24
Peak memory 223844 kb
Host smart-faadcd33-f96c-41c9-b6af-5770792dbda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941720854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1941720854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.2403433531
Short name T752
Test name
Test status
Simulation time 9459372587 ps
CPU time 71.22 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:34:23 PM PDT 24
Peak memory 231212 kb
Host smart-c4a21eca-e4a0-4dfe-973a-6d9524639564
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2403433531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2403433531 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.2656033394
Short name T506
Test name
Test status
Simulation time 417060453 ps
CPU time 4.33 seconds
Started Jul 15 06:33:07 PM PDT 24
Finished Jul 15 06:33:14 PM PDT 24
Peak memory 215608 kb
Host smart-939a5866-d22e-4940-bd94-fc96def264ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656033394 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.2656033394 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2130998144
Short name T347
Test name
Test status
Simulation time 68069799 ps
CPU time 4.22 seconds
Started Jul 15 06:33:06 PM PDT 24
Finished Jul 15 06:33:14 PM PDT 24
Peak memory 215584 kb
Host smart-04103abe-ce5c-4869-ab1f-caecc2756e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130998144 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2130998144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.3000735122
Short name T716
Test name
Test status
Simulation time 201908666564 ps
CPU time 2105.06 seconds
Started Jul 15 06:33:07 PM PDT 24
Finished Jul 15 07:08:15 PM PDT 24
Peak memory 390860 kb
Host smart-9ceba05f-c8ac-43a4-a05d-9fad55159668
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3000735122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.3000735122 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.2680605114
Short name T210
Test name
Test status
Simulation time 89348342497 ps
CPU time 1740.81 seconds
Started Jul 15 06:33:08 PM PDT 24
Finished Jul 15 07:02:11 PM PDT 24
Peak memory 365808 kb
Host smart-da36b525-2ce4-4e8f-9e82-1e05cce53a46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2680605114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2680605114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.2282639169
Short name T689
Test name
Test status
Simulation time 28103627488 ps
CPU time 1133.22 seconds
Started Jul 15 06:33:07 PM PDT 24
Finished Jul 15 06:52:03 PM PDT 24
Peak memory 326616 kb
Host smart-eb66fe8b-d63e-4756-9642-1017fa2e8ac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2282639169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2282639169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.3581668724
Short name T470
Test name
Test status
Simulation time 43111564565 ps
CPU time 944.89 seconds
Started Jul 15 06:33:06 PM PDT 24
Finished Jul 15 06:48:55 PM PDT 24
Peak memory 298444 kb
Host smart-1ebdd9c3-bd6e-4439-b0ac-594d53e8b2a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3581668724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.3581668724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.1454232587
Short name T310
Test name
Test status
Simulation time 50994744157 ps
CPU time 4080.24 seconds
Started Jul 15 06:33:06 PM PDT 24
Finished Jul 15 07:41:10 PM PDT 24
Peak memory 642232 kb
Host smart-145bdece-594f-46af-8a22-4f9ba4e4bb7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1454232587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.1454232587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.1356749056
Short name T318
Test name
Test status
Simulation time 45782153733 ps
CPU time 3239.54 seconds
Started Jul 15 06:33:06 PM PDT 24
Finished Jul 15 07:27:10 PM PDT 24
Peak memory 574864 kb
Host smart-8608b617-32e2-4c09-8ce3-6228d89d58bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1356749056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.1356749056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.4054225560
Short name T579
Test name
Test status
Simulation time 57249391 ps
CPU time 0.82 seconds
Started Jul 15 06:33:16 PM PDT 24
Finished Jul 15 06:33:18 PM PDT 24
Peak memory 205252 kb
Host smart-5176660c-e68e-4d1c-9881-089f37df4e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054225560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.4054225560 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.2467949188
Short name T1078
Test name
Test status
Simulation time 1078603424 ps
CPU time 13.38 seconds
Started Jul 15 06:33:12 PM PDT 24
Finished Jul 15 06:33:26 PM PDT 24
Peak memory 223776 kb
Host smart-84d1219b-9034-43da-a881-1bc12ddfb790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467949188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2467949188 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.1159208154
Short name T921
Test name
Test status
Simulation time 17054486406 ps
CPU time 361.77 seconds
Started Jul 15 06:33:11 PM PDT 24
Finished Jul 15 06:39:14 PM PDT 24
Peak memory 228900 kb
Host smart-f93af67e-98d7-462e-a5f6-0961ab8dfdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159208154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1159208154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.116813899
Short name T444
Test name
Test status
Simulation time 209346908 ps
CPU time 4.09 seconds
Started Jul 15 06:33:13 PM PDT 24
Finished Jul 15 06:33:18 PM PDT 24
Peak memory 216496 kb
Host smart-087b317a-ff79-4b6c-85fa-5cc123deb994
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=116813899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.116813899 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.2606011284
Short name T307
Test name
Test status
Simulation time 700152492 ps
CPU time 8.68 seconds
Started Jul 15 06:33:14 PM PDT 24
Finished Jul 15 06:33:23 PM PDT 24
Peak memory 223696 kb
Host smart-382d57a3-4a63-4655-9955-196f1c3e50a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2606011284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2606011284 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.1012747985
Short name T1023
Test name
Test status
Simulation time 1506652994 ps
CPU time 3.88 seconds
Started Jul 15 06:33:12 PM PDT 24
Finished Jul 15 06:33:17 PM PDT 24
Peak memory 215632 kb
Host smart-11297ee1-7949-4b6a-af7f-06f863422063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012747985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1012747985 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.2353576787
Short name T907
Test name
Test status
Simulation time 15176594854 ps
CPU time 233.15 seconds
Started Jul 15 06:33:11 PM PDT 24
Finished Jul 15 06:37:06 PM PDT 24
Peak memory 242248 kb
Host smart-7da34896-d3e0-476f-ba02-ba4affc97232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353576787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2353576787 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.4171614121
Short name T156
Test name
Test status
Simulation time 61360192213 ps
CPU time 286.13 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:37:58 PM PDT 24
Peak memory 255608 kb
Host smart-691b1451-2b50-4841-a55c-055e27e892b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171614121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.4171614121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.182627134
Short name T597
Test name
Test status
Simulation time 1857564212 ps
CPU time 5.13 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:33:17 PM PDT 24
Peak memory 207380 kb
Host smart-fab24b9c-bd89-4271-b76e-604308882fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182627134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.182627134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.2979347756
Short name T459
Test name
Test status
Simulation time 44209596 ps
CPU time 1.29 seconds
Started Jul 15 06:33:16 PM PDT 24
Finished Jul 15 06:33:18 PM PDT 24
Peak memory 215632 kb
Host smart-3736403b-8031-48a1-954c-4d9f6bfde284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979347756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2979347756 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.1625849904
Short name T548
Test name
Test status
Simulation time 7697823627 ps
CPU time 588.51 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:43:01 PM PDT 24
Peak memory 287172 kb
Host smart-7f1b58de-01ee-4080-ae94-11e242286683
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625849904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.1625849904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.725415427
Short name T474
Test name
Test status
Simulation time 6479519586 ps
CPU time 47.07 seconds
Started Jul 15 06:33:13 PM PDT 24
Finished Jul 15 06:34:01 PM PDT 24
Peak memory 225568 kb
Host smart-90df376f-a76c-4119-abd2-c13d922e99d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725415427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.725415427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.2536215005
Short name T400
Test name
Test status
Simulation time 39578279433 ps
CPU time 239.26 seconds
Started Jul 15 06:33:13 PM PDT 24
Finished Jul 15 06:37:13 PM PDT 24
Peak memory 240172 kb
Host smart-97b27ecf-3b5c-427d-8104-48f63a2b2411
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536215005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2536215005 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.718436514
Short name T346
Test name
Test status
Simulation time 10199510378 ps
CPU time 55.56 seconds
Started Jul 15 06:33:12 PM PDT 24
Finished Jul 15 06:34:08 PM PDT 24
Peak memory 219220 kb
Host smart-f90347be-5461-419d-acc4-aa1f98436056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718436514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.718436514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.1791906207
Short name T90
Test name
Test status
Simulation time 98729164864 ps
CPU time 409.24 seconds
Started Jul 15 06:33:21 PM PDT 24
Finished Jul 15 06:40:11 PM PDT 24
Peak memory 264660 kb
Host smart-f965fba9-60d2-4cf0-b735-3800fb23564b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1791906207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1791906207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3068821021
Short name T544
Test name
Test status
Simulation time 174882885 ps
CPU time 4.65 seconds
Started Jul 15 06:33:12 PM PDT 24
Finished Jul 15 06:33:18 PM PDT 24
Peak memory 209308 kb
Host smart-7572d80e-dc83-4b4e-92ab-3812864902c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068821021 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3068821021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.297241116
Short name T896
Test name
Test status
Simulation time 964319987 ps
CPU time 3.91 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 06:33:16 PM PDT 24
Peak memory 215648 kb
Host smart-34066098-e298-4b0d-a21f-aa4168416688
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297241116 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.kmac_test_vectors_kmac_xof.297241116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1596807926
Short name T1016
Test name
Test status
Simulation time 97390262378 ps
CPU time 1958.42 seconds
Started Jul 15 06:33:09 PM PDT 24
Finished Jul 15 07:05:50 PM PDT 24
Peak memory 393236 kb
Host smart-aabcbf10-c139-43db-96ea-38ee186a9ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1596807926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1596807926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.1816193718
Short name T599
Test name
Test status
Simulation time 386538215400 ps
CPU time 1866.63 seconds
Started Jul 15 06:33:12 PM PDT 24
Finished Jul 15 07:04:20 PM PDT 24
Peak memory 379156 kb
Host smart-c1931c4b-d4da-4b90-961a-d7575f25377e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1816193718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.1816193718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.287218760
Short name T641
Test name
Test status
Simulation time 154162613360 ps
CPU time 1392.9 seconds
Started Jul 15 06:33:12 PM PDT 24
Finished Jul 15 06:56:26 PM PDT 24
Peak memory 337496 kb
Host smart-043d0635-6f09-4dfb-97bb-45c2b64bbaa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=287218760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.287218760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.2426869474
Short name T445
Test name
Test status
Simulation time 38280920532 ps
CPU time 756.85 seconds
Started Jul 15 06:33:13 PM PDT 24
Finished Jul 15 06:45:50 PM PDT 24
Peak memory 296128 kb
Host smart-38dfb3a3-b6a5-4eb3-8ca7-025ebaf78644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2426869474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.2426869474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.3909336808
Short name T74
Test name
Test status
Simulation time 176917373989 ps
CPU time 4438.24 seconds
Started Jul 15 06:33:10 PM PDT 24
Finished Jul 15 07:47:11 PM PDT 24
Peak memory 648856 kb
Host smart-038d5948-7c0e-495e-b5b2-6406a9a05e41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3909336808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.3909336808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.887810409
Short name T161
Test name
Test status
Simulation time 829970261897 ps
CPU time 4091.38 seconds
Started Jul 15 06:33:13 PM PDT 24
Finished Jul 15 07:41:26 PM PDT 24
Peak memory 572916 kb
Host smart-83f5d1ae-8463-4722-b6aa-0a4c53e1b05b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=887810409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.887810409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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