Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100366067	1			T1	146		T2	221739		T3	36
all_values[1]	100366067	1			T1	146		T2	221739		T3	36
all_values[2]	100366067	1			T1	146		T2	221739		T3	36

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619329

1

T1

42

T2

3

T3

9

auto[1]

300478872

1

T1

396

T2

665214

T3

99

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299573958

1

T1

381

T2

663417

T3

96

auto[1]

1524243

1

T1

57

T2

1800

T3

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	200387	1			T1	6		T12	5		T17	61
all_values[0]	auto[0]	auto[1]	2085	1			T1	2		T12	6		T17	6
all_values[0]	auto[1]	auto[0]	99657599	1			T1	121		T2	221139		T3	32
all_values[0]	auto[1]	auto[1]	505996	1			T1	17		T2	600		T3	4
all_values[1]	auto[0]	auto[0]	207745	1			T2	2		T3	8		T12	5
all_values[1]	auto[0]	auto[1]	1638	1			T2	1		T3	1		T12	6
all_values[1]	auto[1]	auto[0]	99650241	1			T1	127		T2	221137		T3	24
all_values[1]	auto[1]	auto[1]	506443	1			T1	19		T2	599		T3	3
all_values[2]	auto[0]	auto[0]	205949	1			T1	30		T14	54		T24	271
all_values[2]	auto[0]	auto[1]	1525	1			T1	4		T14	2		T24	1
all_values[2]	auto[1]	auto[0]	99652037	1			T1	97		T2	221139		T3	32
all_values[2]	auto[1]	auto[1]	506556	1			T1	15		T2	600		T3	4