Summary for Variable key_len
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for key_len
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Key128] |
65759 |
1 |
|
|
T1 |
2 |
|
T2 |
72 |
|
T12 |
474 |
auto[Key192] |
65907 |
1 |
|
|
T1 |
4 |
|
T2 |
80 |
|
T12 |
496 |
auto[Key256] |
79852 |
1 |
|
|
T1 |
2 |
|
T2 |
74 |
|
T3 |
1 |
auto[Key384] |
66020 |
1 |
|
|
T1 |
3 |
|
T2 |
76 |
|
T3 |
2 |
auto[Key512] |
65889 |
1 |
|
|
T1 |
2 |
|
T2 |
88 |
|
T12 |
452 |
Summary for Variable kmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
311553 |
1 |
|
|
T1 |
3 |
|
T2 |
390 |
|
T3 |
1 |
auto[1] |
31874 |
1 |
|
|
T1 |
10 |
|
T3 |
2 |
|
T13 |
45 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
67235 |
1 |
|
|
T1 |
2 |
|
T2 |
390 |
|
T13 |
2 |
auto[Shake] |
241341 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T12 |
2337 |
auto[CShake] |
34851 |
1 |
|
|
T1 |
10 |
|
T3 |
2 |
|
T13 |
60 |
Summary for Variable msg_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for msg_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171340 |
1 |
|
|
T1 |
8 |
|
T2 |
181 |
|
T12 |
1147 |
auto[1] |
172087 |
1 |
|
|
T1 |
5 |
|
T2 |
209 |
|
T3 |
3 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333769 |
1 |
|
|
T1 |
13 |
|
T2 |
390 |
|
T3 |
3 |
auto[1] |
9658 |
1 |
|
|
T13 |
10 |
|
T14 |
150 |
|
T15 |
38 |
Summary for Variable state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171698 |
1 |
|
|
T1 |
7 |
|
T2 |
192 |
|
T3 |
2 |
auto[1] |
171729 |
1 |
|
|
T1 |
6 |
|
T2 |
198 |
|
T3 |
1 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
138305 |
1 |
|
|
T1 |
6 |
|
T3 |
1 |
|
T12 |
2337 |
auto[L224] |
19831 |
1 |
|
|
T1 |
1 |
|
T2 |
390 |
|
T14 |
1 |
auto[L256] |
156883 |
1 |
|
|
T1 |
5 |
|
T3 |
2 |
|
T13 |
46 |
auto[L384] |
15824 |
1 |
|
|
T13 |
1 |
|
T14 |
1 |
|
T37 |
1 |
auto[L512] |
12584 |
1 |
|
|
T1 |
1 |
|
T14 |
1 |
|
T23 |
1 |
Summary for Variable xof_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for xof_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
325383 |
1 |
|
|
T1 |
7 |
|
T2 |
390 |
|
T3 |
3 |
auto[1] |
18044 |
1 |
|
|
T1 |
6 |
|
T13 |
17 |
|
T14 |
78 |
Summary for Cross kmac_cross
Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for kmac_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
31874 |
1 |
|
|
T1 |
10 |
|
T3 |
2 |
|
T13 |
45 |
Summary for Cross cshake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for cshake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
34851 |
1 |
|
|
T1 |
10 |
|
T3 |
2 |
|
T13 |
60 |
Summary for Cross shake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for shake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
241341 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T12 |
2337 |
Summary for Cross sha3_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for sha3_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
67235 |
1 |
|
|
T1 |
2 |
|
T2 |
390 |
|
T13 |
2 |