Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342332 |
1 |
|
|
T1 |
2 |
|
T2 |
780 |
|
T3 |
6 |
auto[1] |
346804 |
1 |
|
|
T1 |
24 |
|
T13 |
198 |
|
T14 |
298 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172516 |
1 |
|
|
T1 |
8 |
|
T2 |
216 |
|
T12 |
1194 |
lower_val |
170767 |
1 |
|
|
T1 |
10 |
|
T2 |
182 |
|
T3 |
2 |
zero_val |
1829 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
344916 |
1 |
|
|
T1 |
10 |
|
T2 |
364 |
|
T12 |
2382 |
lower_val |
344212 |
1 |
|
|
T1 |
16 |
|
T2 |
416 |
|
T3 |
6 |
zero_val |
8 |
1 |
|
|
T150 |
2 |
|
T151 |
2 |
|
T152 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42740 |
1 |
|
|
T2 |
100 |
|
T12 |
597 |
|
T13 |
1 |
higher_val |
higher_val |
auto[1] |
43615 |
1 |
|
|
T1 |
2 |
|
T13 |
17 |
|
T14 |
33 |
higher_val |
lower_val |
auto[0] |
42727 |
1 |
|
|
T2 |
116 |
|
T12 |
597 |
|
T15 |
5 |
higher_val |
lower_val |
auto[1] |
43433 |
1 |
|
|
T1 |
6 |
|
T13 |
19 |
|
T14 |
43 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T152 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
42542 |
1 |
|
|
T2 |
81 |
|
T12 |
589 |
|
T15 |
9 |
lower_val |
higher_val |
auto[1] |
42891 |
1 |
|
|
T1 |
2 |
|
T13 |
32 |
|
T14 |
26 |
lower_val |
lower_val |
auto[0] |
42170 |
1 |
|
|
T2 |
101 |
|
T3 |
2 |
|
T12 |
548 |
lower_val |
lower_val |
auto[1] |
43161 |
1 |
|
|
T1 |
8 |
|
T13 |
42 |
|
T14 |
52 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T151 |
1 |
|
T152 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T153 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
677 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
3 |
zero_val |
higher_val |
auto[1] |
225 |
1 |
|
|
T14 |
1 |
|
T106 |
1 |
|
T154 |
1 |
zero_val |
lower_val |
auto[0] |
661 |
1 |
|
|
T3 |
1 |
|
T12 |
2 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
266 |
1 |
|
|
T14 |
1 |
|
T24 |
1 |
|
T106 |
1 |