Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10353	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9125	1			T2	17		T3	2		T12	30
len_5001_7500	14493	1			T2	17		T12	30		T24	49
len_2501_5000	9318	1			T2	17		T12	30		T24	12
len_1025_2500	5430	1			T2	10		T3	1		T12	16
len_769_1024	5892	1			T2	2		T12	4		T13	21
len_513_768	6370	1			T2	2		T12	2		T13	18
len_257_512	20761	1			T2	2		T12	244		T13	16
len_0_256	256597	1			T1	13		T2	290		T12	1897
len_keccak_block_sizes[72]	723	1			T2	2		T12	3		T13	1
len_keccak_block_sizes[104]	622	1			T2	2		T12	3		T89	3
len_keccak_block_sizes[136]	524	1			T2	2		T12	3		T14	1
len_keccak_block_sizes[144]	420	1			T2	2		T12	3		T13	1
len_keccak_block_sizes[168]	312	1			T12	3		T89	3		T178	3
len_1	756	1			T2	2		T12	3		T23	1
len_0	1187	1			T2	2		T12	3		T24	4