Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100366067	1			T1	146		T2	221739		T3	36
all_pins[1]	100366067	1			T1	146		T2	221739		T3	36
all_pins[2]	100366067	1			T1	146		T2	221739		T3	36

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300276390	1			T1	421		T2	664617		T3	104
values[0x1]	821811	1			T1	17		T2	600		T3	4
transitions[0x0=>0x1]	819901	1			T1	17		T2	600		T3	4
transitions[0x1=>0x0]	819925	1			T1	17		T2	600		T3	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99860071	1			T1	129		T2	221139		T3	32
all_pins[0]	values[0x1]	505996	1			T1	17		T2	600		T3	4
all_pins[0]	transitions[0x0=>0x1]	505986	1			T1	17		T2	600		T3	4
all_pins[0]	transitions[0x1=>0x0]	65	1			T42	6		T166	2		T167	3
all_pins[1]	values[0x0]	100365992	1			T1	146		T2	221739		T3	36
all_pins[1]	values[0x1]	75	1			T42	6		T166	2		T167	3
all_pins[1]	transitions[0x0=>0x1]	65	1			T42	6		T166	2		T167	3
all_pins[1]	transitions[0x1=>0x0]	315730	1			T13	11557		T23	15304		T24	2936
all_pins[2]	values[0x0]	100050327	1			T1	146		T2	221739		T3	36
all_pins[2]	values[0x1]	315740	1			T13	11557		T23	15304		T24	2936
all_pins[2]	transitions[0x0=>0x1]	313850	1			T13	11483		T23	15195		T24	2917
all_pins[2]	transitions[0x1=>0x0]	504130	1			T1	17		T2	600		T3	4