Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101518334	1			T1	8156		T3	16011		T13	570755
all_values[1]	101518334	1			T1	8156		T3	16011		T13	570755
all_values[2]	101518334	1			T1	8156		T3	16011		T13	570755

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

574056

1

T3

494

T13

14

T15

11

auto[1]

303980946

1

T1

24468

T3

47539

T13

171225

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303033624

1

T1

24204

T3

47565

T13

170174

auto[1]

1521378

1

T1

264

T3

468

T13

10521

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	180097	1			T13	3		T16	4		T18	3
all_values[0]	auto[0]	auto[1]	1943	1			T13	4		T16	4		T18	4
all_values[0]	auto[1]	auto[0]	100831111	1			T1	8068		T3	15855		T13	567245
all_values[0]	auto[1]	auto[1]	505183	1			T1	88		T3	156		T13	3503
all_values[1]	auto[0]	auto[0]	228360	1			T3	386		T13	3		T15	7
all_values[1]	auto[0]	auto[1]	1634	1			T3	5		T13	4		T15	4
all_values[1]	auto[1]	auto[0]	100782848	1			T1	8068		T3	15469		T13	567245
all_values[1]	auto[1]	auto[1]	505492	1			T1	88		T3	151		T13	3503
all_values[2]	auto[0]	auto[0]	160402	1			T3	102		T16	4		T18	1
all_values[2]	auto[0]	auto[1]	1620	1			T3	1		T16	4		T18	2
all_values[2]	auto[1]	auto[0]	100850806	1			T1	8068		T3	15753		T13	567248
all_values[2]	auto[1]	auto[1]	505506	1			T1	88		T3	155		T13	3507