Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101518334	1			T1	8156		T3	16011		T13	570755
all_pins[1]	101518334	1			T1	8156		T3	16011		T13	570755
all_pins[2]	101518334	1			T1	8156		T3	16011		T13	570755

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	303694606	1			T1	24124		T3	47877		T13	170876
values[0x1]	860396	1			T1	344		T3	156		T13	3503
transitions[0x0=>0x1]	858186	1			T1	344		T3	156		T13	3503
transitions[0x1=>0x0]	858207	1			T1	344		T3	156		T13	3503

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101013151	1			T1	8068		T3	15855		T13	567252
all_pins[0]	values[0x1]	505183	1			T1	88		T3	156		T13	3503
all_pins[0]	transitions[0x0=>0x1]	505166	1			T1	88		T3	156		T13	3503
all_pins[0]	transitions[0x1=>0x0]	66	1			T39	5		T40	3		T179	4
all_pins[1]	values[0x0]	101518251	1			T1	8156		T3	16011		T13	570755
all_pins[1]	values[0x1]	83	1			T39	5		T40	3		T179	4
all_pins[1]	transitions[0x0=>0x1]	71	1			T39	5		T40	3		T179	4
all_pins[1]	transitions[0x1=>0x0]	355118	1			T1	256		T23	1054		T31	1394
all_pins[2]	values[0x0]	101163204	1			T1	7900		T3	16011		T13	570755
all_pins[2]	values[0x1]	355130	1			T1	256		T23	1054		T31	1394
all_pins[2]	transitions[0x0=>0x1]	352949	1			T1	256		T23	1046		T31	1393
all_pins[2]	transitions[0x1=>0x0]	503023	1			T1	88		T3	156		T13	3503