Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100655945	1			T1	2224		T2	289		T3	1226
all_values[1]	100655945	1			T1	2224		T2	289		T3	1226
all_values[2]	100655945	1			T1	2224		T2	289		T3	1226

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

530841

1

T1

31

T2

98

T3

124

auto[1]

301436994

1

T1

6641

T2

769

T3

3554

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300440352

1

T1

6066

T2

822

T3

3642

auto[1]

1527483

1

T1

606

T2

45

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	192608	1			T2	84		T12	107		T16	4734
all_values[0]	auto[0]	auto[1]	2119	1			T2	8		T12	2		T16	18
all_values[0]	auto[1]	auto[0]	99954176	1			T1	2022		T2	190		T3	1214
all_values[0]	auto[1]	auto[1]	507042	1			T1	202		T2	7		T3	12
all_values[1]	auto[0]	auto[0]	176386	1			T1	30		T2	4		T12	289
all_values[1]	auto[0]	auto[1]	1508	1			T1	1		T2	2		T12	3
all_values[1]	auto[1]	auto[0]	99970398	1			T1	1992		T2	270		T3	1214
all_values[1]	auto[1]	auto[1]	507653	1			T1	201		T2	13		T3	12
all_values[2]	auto[0]	auto[0]	156732	1			T3	123		T12	107		T15	161
all_values[2]	auto[0]	auto[1]	1488	1			T3	1		T12	2		T15	1
all_values[2]	auto[1]	auto[0]	99990052	1			T1	2022		T2	274		T3	1091
all_values[2]	auto[1]	auto[1]	507673	1			T1	202		T2	15		T3	11