Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
327362 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
22 |
auto[1] |
364880 |
1 |
|
|
T1 |
270 |
|
T2 |
16 |
|
T12 |
82 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173156 |
1 |
|
|
T1 |
64 |
|
T2 |
7 |
|
T3 |
4 |
lower_val |
171571 |
1 |
|
|
T1 |
72 |
|
T2 |
2 |
|
T3 |
8 |
zero_val |
1812 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345428 |
1 |
|
|
T1 |
128 |
|
T3 |
12 |
|
T12 |
46 |
lower_val |
346810 |
1 |
|
|
T1 |
144 |
|
T2 |
18 |
|
T3 |
10 |
zero_val |
4 |
1 |
|
|
T145 |
2 |
|
T146 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40540 |
1 |
|
|
T3 |
3 |
|
T14 |
30 |
|
T15 |
2 |
higher_val |
higher_val |
auto[1] |
45903 |
1 |
|
|
T1 |
28 |
|
T12 |
12 |
|
T13 |
55 |
higher_val |
lower_val |
auto[0] |
40848 |
1 |
|
|
T3 |
1 |
|
T14 |
32 |
|
T15 |
7 |
higher_val |
lower_val |
auto[1] |
45864 |
1 |
|
|
T1 |
36 |
|
T2 |
7 |
|
T12 |
13 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T146 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
40616 |
1 |
|
|
T3 |
4 |
|
T14 |
27 |
|
T15 |
3 |
lower_val |
higher_val |
auto[1] |
44874 |
1 |
|
|
T1 |
30 |
|
T12 |
11 |
|
T13 |
43 |
lower_val |
lower_val |
auto[0] |
40821 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T12 |
1 |
lower_val |
lower_val |
auto[1] |
45260 |
1 |
|
|
T1 |
42 |
|
T2 |
1 |
|
T12 |
10 |
zero_val |
higher_val |
auto[0] |
675 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
258 |
1 |
|
|
T16 |
2 |
|
T147 |
4 |
|
T22 |
3 |
zero_val |
lower_val |
auto[0] |
658 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
221 |
1 |
|
|
T16 |
3 |
|
T147 |
4 |
|
T22 |
1 |