Group : kmac_env_pkg::kmac_env_cov::error_cg
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Group : kmac_env_pkg::kmac_env_cov::error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
89.66 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 21 3 18 85.71
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cmd 4 0 4 100.00 100 1 1 0
kmac_err_code 9 3 6 66.67 100 1 1 0
mode 3 0 3 100.00 100 1 1 0
strength 5 0 5 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_invalid_cmd_in_app_active 1 0 1 100.00 100 1 1 0
all_invalid_mode_strength_cfgs 7 0 7 100.00 100 1 1 0


Summary for Variable cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[CmdNone] 0 Excluded
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CmdStart] 694 1 T13 35 T26 32 T27 19
auto[CmdProcess] 125 1 T13 7 T26 3 T27 4
auto[CmdManualRun] 413 1 T13 23 T26 7 T27 12
auto[CmdDone] 1460 1 T13 32 T26 43 T27 35



Summary for Variable kmac_err_code

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 9 3 6 66.67


Automatically Generated Bins for kmac_err_code

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[ErrFatalError] 0 1 1
auto[ErrPackerIntegrity] 0 1 1
auto[ErrMsgFifoIntegrity] 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
auto[ErrNone] 0 Excluded
auto[ErrWaitTimerExpired] 0 Illegal
auto[ErrIncorrectEntropyMode] 0 Illegal
auto[ErrSwHashingWithoutEntropyReady] 0 Illegal
auto[ErrShadowRegUpdate] 0 Illegal
il 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ErrKeyNotValid] 50 1 T19 1 T20 1 T21 1
auto[ErrSwPushedMsgFifo] 50 1 T13 1 T26 2 T27 1
auto[ErrSwIssuedCmdInAppActive] 46 1 T13 3 T26 2 T27 1
auto[ErrUnexpectedModeStrength] 648 1 T13 18 T26 16 T27 13
auto[ErrIncorrectFunctionName] 574 1 T13 28 T26 26 T27 14
auto[ErrSwCmdSequence] 1399 1 T13 50 T26 39 T27 41



Summary for Variable mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[Sha3] 437 1 T13 6 T26 8 T27 12
auto[Shake] 448 1 T13 21 T26 15 T27 10
auto[CShake] 1832 1 T13 73 T26 62 T27 48



Summary for Variable strength

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for strength

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[L128] 937 1 T13 29 T26 26 T27 25
auto[L224] 300 1 T13 15 T26 13 T27 5
auto[L256] 906 1 T13 47 T19 1 T20 1
auto[L384] 337 1 T13 4 T26 6 T27 6
auto[L512] 287 1 T13 5 T26 12 T27 9



Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
invalid_cmds 45 1 T13 3 T26 2 T27 1



Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 7 0 7 100.00


User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sha3_128_cfgs 192 1 T13 6 T26 3 T27 5
shake_224_invalid_cfg 34 1 T13 3 T27 1 T150 1
shake_384_invalid_cfg 46 1 T13 1 T26 2 T28 2
shake_512_invalid_cfg 29 1 T27 1 T150 1 T151 1
cshake_224_invalid_cfg 115 1 T13 4 T26 5 T27 2
cshake_384_invalid_cfg 118 1 T13 1 T27 2 T67 1
cshake_512_invalid_cfg 114 1 T13 3 T26 6 T27 2

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