Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10351	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9028	1			T1	23		T15	2		T16	16
len_5001_7500	14793	1			T1	76		T15	8		T16	31
len_2501_5000	9366	1			T1	14		T16	11		T170	34
len_1025_2500	5435	1			T1	3		T15	1		T16	5
len_769_1024	6152	1			T3	3		T12	5		T13	35
len_513_768	6380	1			T1	1		T3	1		T12	6
len_257_512	21117	1			T1	1		T3	1		T12	7
len_0_256	256612	1			T1	18		T2	9		T3	3
len_keccak_block_sizes[72]	730	1			T170	2		T171	2		T77	3
len_keccak_block_sizes[104]	627	1			T3	1		T171	2		T77	3
len_keccak_block_sizes[136]	527	1			T13	1		T14	1		T171	2
len_keccak_block_sizes[144]	425	1			T171	2		T77	3		T172	2
len_keccak_block_sizes[168]	324	1			T14	1		T77	3		T147	3
len_1	743	1			T17	2		T170	2		T171	2
len_0	1183	1			T1	4		T16	2		T17	5