Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100655945	1			T1	2224		T2	289		T3	1226
all_pins[1]	100655945	1			T1	2224		T2	289		T3	1226
all_pins[2]	100655945	1			T1	2224		T2	289		T3	1226

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301163364	1			T1	6470		T2	860		T3	2572
values[0x1]	804471	1			T1	202		T2	7		T3	1106
transitions[0x0=>0x1]	802702	1			T1	202		T2	7		T3	1099
transitions[0x1=>0x0]	802727	1			T1	202		T2	7		T3	1099

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100148903	1			T1	2022		T2	282		T3	1214
all_pins[0]	values[0x1]	507042	1			T1	202		T2	7		T3	12
all_pins[0]	transitions[0x0=>0x1]	507032	1			T1	202		T2	7		T3	12
all_pins[0]	transitions[0x1=>0x0]	75	1			T157	2		T158	3		T159	3
all_pins[1]	values[0x0]	100655860	1			T1	2224		T2	289		T3	1226
all_pins[1]	values[0x1]	85	1			T157	2		T158	3		T159	3
all_pins[1]	transitions[0x0=>0x1]	71	1			T157	2		T158	3		T159	3
all_pins[1]	transitions[0x1=>0x0]	297330	1			T3	1094		T13	864		T16	6756
all_pins[2]	values[0x0]	100358601	1			T1	2224		T2	289		T3	132
all_pins[2]	values[0x1]	297344	1			T3	1094		T13	864		T16	6756
all_pins[2]	transitions[0x0=>0x1]	295599	1			T3	1087		T13	863		T16	6711
all_pins[2]	transitions[0x1=>0x0]	505322	1			T1	202		T2	7		T3	5