Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	702	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5508	1			T1	17		T12	4		T13	21
len_601_800	12451	1			T1	51		T3	4		T12	7
len_401_600	8355	1			T1	29		T3	1		T12	9
len_201_400	16484	1			T1	18		T12	2		T13	21
len_65_200	73225	1			T1	10		T13	7		T14	10
len_min_for_xof_require_squeeze	996	1			T16	1		T77	10		T147	9
len_keccak_block_sizes[72]	756	1			T77	5		T120	2		T147	9
len_keccak_block_sizes[104]	748	1			T17	2		T77	5		T120	2
len_keccak_block_sizes[136]	747	1			T16	1		T17	1		T77	5
len_keccak_block_sizes[144]	280	1			T17	1		T77	5		T120	1
len_keccak_block_sizes[168]	273	1			T77	5		T174	5		T175	5
len_datapath_width	14039	1			T2	3		T3	1		T13	2
len_2_63	214036	1			T1	8		T2	6		T3	5
len_1	48	1			T17	3		T120	1		T176	1