Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 299 1 T102 7 T103 7 T104 7
all_values[1] 299 1 T102 7 T103 7 T104 7
all_values[2] 299 1 T102 7 T103 7 T104 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 500 1 T102 11 T103 13 T104 14
auto[1] 397 1 T102 10 T103 8 T104 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 404 1 T102 12 T103 5 T104 7
auto[1] 493 1 T102 9 T103 16 T104 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 526 1 T102 15 T103 7 T104 12
auto[1] 371 1 T102 6 T103 14 T104 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 71 1 T102 4 T103 2 T104 2
all_values[0] auto[0] auto[0] auto[1] 30 1 T102 1 T103 1 T104 1
all_values[0] auto[0] auto[1] auto[0] 47 1 T102 1 T144 1 T152 1
all_values[0] auto[0] auto[1] auto[1] 31 1 T153 1 T154 3 T155 1
all_values[0] auto[1] auto[0] auto[1] 69 1 T102 1 T103 2 T104 1
all_values[0] auto[1] auto[1] auto[1] 51 1 T103 2 T104 3 T153 2
all_values[1] auto[0] auto[0] auto[0] 83 1 T102 1 T104 4 T153 2
all_values[1] auto[0] auto[1] auto[0] 85 1 T102 3 T103 1 T104 1
all_values[1] auto[1] auto[0] auto[1] 73 1 T102 2 T103 4 T104 2
all_values[1] auto[1] auto[1] auto[1] 58 1 T102 1 T103 2 T144 1
all_values[2] auto[0] auto[0] auto[0] 70 1 T102 1 T103 1 T153 4
all_values[2] auto[0] auto[0] auto[1] 36 1 T103 1 T104 3 T154 2
all_values[2] auto[0] auto[1] auto[0] 48 1 T102 2 T103 1 T144 4
all_values[2] auto[0] auto[1] auto[1] 25 1 T102 2 T104 1 T156 1
all_values[2] auto[1] auto[0] auto[1] 68 1 T102 1 T103 2 T104 1
all_values[2] auto[1] auto[1] auto[1] 52 1 T102 1 T103 2 T104 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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