Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100943403	1			T1	899		T2	254		T12	20272
all_values[1]	100943403	1			T1	899		T2	254		T12	20272
all_values[2]	100943403	1			T1	899		T2	254		T12	20272

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

505068

1

T1

548

T2

8

T12

828

auto[1]

302325141

1

T1

2149

T2

754

T12

59988

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301304523

1

T1

2664

T2

732

T12

60261

auto[1]

1525686

1

T1

33

T2

30

T12

555

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	172898	1			T1	69		T12	325		T13	76
all_values[0]	auto[0]	auto[1]	2005	1			T1	2		T12	4		T13	6
all_values[0]	auto[1]	auto[0]	100261943	1			T1	819		T2	244		T12	19762
all_values[0]	auto[1]	auto[1]	506557	1			T1	9		T2	10		T12	181
all_values[1]	auto[0]	auto[0]	161561	1			T12	494		T4	7		T13	83
all_values[1]	auto[0]	auto[1]	1493	1			T12	5		T13	7		T77	2
all_values[1]	auto[1]	auto[0]	100273280	1			T1	888		T2	244		T12	19593
all_values[1]	auto[1]	auto[1]	507069	1			T1	11		T2	10		T12	180
all_values[2]	auto[0]	auto[0]	165636	1			T1	472		T2	7		T13	4
all_values[2]	auto[0]	auto[1]	1475	1			T1	5		T2	1		T13	2
all_values[2]	auto[1]	auto[0]	100269205	1			T1	416		T2	237		T12	20087
all_values[2]	auto[1]	auto[1]	507087	1			T1	6		T2	9		T12	185