Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 350654 | 1 |  |  | T1 | 2 |  | T2 | 2 |  | T12 | 2 | 
| auto[1] | 341388 | 1 |  |  | T1 | 20 |  | T2 | 16 |  | T12 | 318 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 172517 | 1 |  |  | T1 | 2 |  | T12 | 56 |  | T13 | 4 | 
| lower_val | 171523 | 1 |  |  | T1 | 6 |  | T2 | 9 |  | T12 | 69 | 
| zero_val | 1722 | 1 |  |  | T1 | 1 |  | T2 | 1 |  | T12 | 3 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 346522 | 1 |  |  | T1 | 14 |  | T2 | 8 |  | T12 | 178 | 
| lower_val | 345510 | 1 |  |  | T1 | 8 |  | T2 | 10 |  | T12 | 142 | 
| zero_val | 10 | 1 |  |  | T166 | 2 |  | T167 | 2 |  | T168 | 2 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 18 | 2 | 16 | 88.89 | 2 | 
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| [zero_val] | [zero_val] | * | -- | -- | 2 |  | 
Covered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | higher_val | auto[0] | 43726 | 1 |  |  | T14 | 591 |  | T15 | 18 |  | T16 | 83 | 
| higher_val | higher_val | auto[1] | 42630 | 1 |  |  | T1 | 1 |  | T12 | 36 |  | T13 | 1 | 
| higher_val | lower_val | auto[0] | 43467 | 1 |  |  | T13 | 1 |  | T14 | 587 |  | T5 | 1 | 
| higher_val | lower_val | auto[1] | 42691 | 1 |  |  | T1 | 1 |  | T12 | 20 |  | T13 | 2 | 
| higher_val | zero_val | auto[0] | 1 | 1 |  |  | T166 | 1 |  | - | - |  | - | - | 
| higher_val | zero_val | auto[1] | 2 | 1 |  |  | T167 | 1 |  | T169 | 1 |  | - | - | 
| lower_val | higher_val | auto[0] | 43303 | 1 |  |  | T14 | 625 |  | T15 | 16 |  | T16 | 87 | 
| lower_val | higher_val | auto[1] | 42641 | 1 |  |  | T1 | 3 |  | T2 | 6 |  | T12 | 35 | 
| lower_val | lower_val | auto[0] | 43604 | 1 |  |  | T14 | 588 |  | T15 | 19 |  | T16 | 91 | 
| lower_val | lower_val | auto[1] | 41972 | 1 |  |  | T1 | 3 |  | T2 | 3 |  | T12 | 34 | 
| lower_val | zero_val | auto[0] | 1 | 1 |  |  | T168 | 1 |  | - | - |  | - | - | 
| lower_val | zero_val | auto[1] | 2 | 1 |  |  | T169 | 1 |  | T170 | 1 |  | - | - | 
| zero_val | higher_val | auto[0] | 651 | 1 |  |  | T1 | 1 |  | T15 | 2 |  | T16 | 1 | 
| zero_val | higher_val | auto[1] | 229 | 1 |  |  | T12 | 2 |  | T171 | 1 |  | T172 | 5 | 
| zero_val | lower_val | auto[0] | 632 | 1 |  |  | T2 | 1 |  | T12 | 1 |  | T4 | 1 | 
| zero_val | lower_val | auto[1] | 210 | 1 |  |  | T171 | 1 |  | T172 | 1 |  | T173 | 3 |