Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100943403	1			T1	899		T2	254		T12	20272
all_pins[1]	100943403	1			T1	899		T2	254		T12	20272
all_pins[2]	100943403	1			T1	899		T2	254		T12	20272

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301983968	1			T1	2688		T2	752		T12	40493
values[0x1]	846241	1			T1	9		T2	10		T12	20323
transitions[0x0=>0x1]	844172	1			T1	9		T2	10		T12	20195
transitions[0x1=>0x0]	844201	1			T1	9		T2	10		T12	20196

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100436846	1			T1	890		T2	244		T12	20091
all_pins[0]	values[0x1]	506557	1			T1	9		T2	10		T12	181
all_pins[0]	transitions[0x0=>0x1]	506549	1			T1	9		T2	10		T12	181
all_pins[0]	transitions[0x1=>0x0]	67	1			T46	4		T176	3		T177	3
all_pins[1]	values[0x0]	100943328	1			T1	899		T2	254		T12	20272
all_pins[1]	values[0x1]	75	1			T46	4		T176	3		T177	3
all_pins[1]	transitions[0x0=>0x1]	68	1			T46	4		T176	3		T177	3
all_pins[1]	transitions[0x1=>0x0]	339602	1			T12	20142		T47	873		T52	830
all_pins[2]	values[0x0]	100603794	1			T1	899		T2	254		T12	130
all_pins[2]	values[0x1]	339609	1			T12	20142		T47	873		T52	830
all_pins[2]	transitions[0x0=>0x1]	337555	1			T12	20014		T47	873		T52	830
all_pins[2]	transitions[0x1=>0x0]	504532	1			T1	9		T2	10		T12	54