Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 10585247 | 1 |  |  | T1 | 1106 |  | T2 | 96 |  | T12 | 23486 | 
| auto[1] | 25509280 | 1 |  |  | T1 | 1828 |  | T2 | 450 |  | T12 | 34380 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 4 | 0 | 4 | 100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 35976289 | 1 |  |  | T1 | 2931 |  | T2 | 546 |  | T12 | 57773 | 
| triple_byte_access | 39356 | 1 |  |  | T1 | 1 |  | T12 | 26 |  | T14 | 279 | 
| halfword_access | 39694 | 1 |  |  | T1 | 2 |  | T12 | 36 |  | T14 | 279 | 
| byte_access | 39188 | 1 |  |  | T12 | 31 |  | T14 | 279 |  | T15 | 22 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 8 | 3 | 5 | 62.50 | 3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | [triple_byte_access , halfword_access , byte_access] | -- | -- | 3 |  | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | word_access | 10467009 | 1 |  |  | T1 | 1103 |  | T2 | 96 |  | T12 | 23393 | 
| auto[0] | triple_byte_access | 39356 | 1 |  |  | T1 | 1 |  | T12 | 26 |  | T14 | 279 | 
| auto[0] | halfword_access | 39694 | 1 |  |  | T1 | 2 |  | T12 | 36 |  | T14 | 279 | 
| auto[0] | byte_access | 39188 | 1 |  |  | T12 | 31 |  | T14 | 279 |  | T15 | 22 | 
| auto[1] | word_access | 25509280 | 1 |  |  | T1 | 1828 |  | T2 | 450 |  | T12 | 34380 |