Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100752305	1			T3	2609		T4	160944		T5	17962
all_values[1]	100752305	1			T3	2609		T4	160944		T5	17962
all_values[2]	100752305	1			T3	2609		T4	160944		T5	17962

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

598273

1

T3

16

T5

605

T14

3846

auto[1]

301658642

1

T3

7811

T4

482832

T5

53281

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300718014

1

T3

7173

T4

481476

T5

53307

auto[1]

1538901

1

T3

654

T4

1356

T5

579

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	184180	1			T3	14		T5	599		T14	2204
all_values[0]	auto[0]	auto[1]	2034	1			T3	2		T5	6		T14	4
all_values[0]	auto[1]	auto[0]	100055158	1			T3	2377		T4	160492		T5	17170
all_values[0]	auto[1]	auto[1]	510933	1			T3	216		T4	452		T5	187
all_values[1]	auto[0]	auto[0]	213206	1			T16	82		T18	99		T36	2
all_values[1]	auto[0]	auto[1]	1671	1			T16	4		T18	3		T36	1
all_values[1]	auto[1]	auto[0]	100026132	1			T3	2391		T4	160492		T5	17769
all_values[1]	auto[1]	auto[1]	511296	1			T3	218		T4	452		T5	193
all_values[2]	auto[0]	auto[0]	195627	1			T14	1636		T18	598		T87	4
all_values[2]	auto[0]	auto[1]	1555	1			T14	2		T18	5		T87	2
all_values[2]	auto[1]	auto[0]	100043711	1			T3	2391		T4	160492		T5	17769
all_values[2]	auto[1]	auto[1]	511412	1			T3	218		T4	452		T5	193