Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 354770 | 1 |  |  | T1 | 2 |  | T3 | 290 |  | T4 | 620 | 
| auto[1] | 342680 | 1 |  |  | T16 | 16 |  | T18 | 108 |  | T36 | 4528 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 174666 | 1 |  |  | T3 | 68 |  | T4 | 160 |  | T5 | 92 | 
| lower_val | 173219 | 1 |  |  | T3 | 86 |  | T4 | 148 |  | T5 | 82 | 
| zero_val | 1821 | 1 |  |  | T1 | 1 |  | T3 | 1 |  | T4 | 1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 349428 | 1 |  |  | T1 | 2 |  | T3 | 154 |  | T4 | 312 | 
| lower_val | 348012 | 1 |  |  | T3 | 136 |  | T4 | 308 |  | T5 | 170 | 
| zero_val | 10 | 1 |  |  | T139 | 2 |  | T140 | 2 |  | T133 | 2 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 18 | 2 | 16 | 88.89 | 2 | 
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| [zero_val] | [zero_val] | * | -- | -- | 2 |  | 
Covered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | higher_val | auto[0] | 44614 | 1 |  |  | T3 | 31 |  | T4 | 75 |  | T5 | 48 | 
| higher_val | higher_val | auto[1] | 42864 | 1 |  |  | T16 | 1 |  | T18 | 5 |  | T36 | 601 | 
| higher_val | lower_val | auto[0] | 44465 | 1 |  |  | T3 | 37 |  | T4 | 85 |  | T5 | 44 | 
| higher_val | lower_val | auto[1] | 42720 | 1 |  |  | T16 | 1 |  | T18 | 14 |  | T36 | 570 | 
| higher_val | zero_val | auto[0] | 1 | 1 |  |  | T133 | 1 |  | - | - |  | - | - | 
| higher_val | zero_val | auto[1] | 2 | 1 |  |  | T139 | 2 |  | - | - |  | - | - | 
| lower_val | higher_val | auto[0] | 44012 | 1 |  |  | T3 | 45 |  | T4 | 80 |  | T5 | 40 | 
| lower_val | higher_val | auto[1] | 42848 | 1 |  |  | T16 | 4 |  | T18 | 23 |  | T36 | 549 | 
| lower_val | lower_val | auto[0] | 43885 | 1 |  |  | T3 | 41 |  | T4 | 68 |  | T5 | 42 | 
| lower_val | lower_val | auto[1] | 42472 | 1 |  |  | T16 | 3 |  | T18 | 15 |  | T36 | 587 | 
| lower_val | zero_val | auto[0] | 1 | 1 |  |  | T133 | 1 |  | - | - |  | - | - | 
| lower_val | zero_val | auto[1] | 1 | 1 |  |  | T141 | 1 |  | - | - |  | - | - | 
| zero_val | higher_val | auto[0] | 658 | 1 |  |  | T1 | 1 |  | T3 | 1 |  | T5 | 1 | 
| zero_val | higher_val | auto[1] | 227 | 1 |  |  | T36 | 4 |  | T37 | 1 |  | T66 | 1 | 
| zero_val | lower_val | auto[0] | 700 | 1 |  |  | T4 | 1 |  | T12 | 6 |  | T13 | 1 | 
| zero_val | lower_val | auto[1] | 236 | 1 |  |  | T18 | 1 |  | T36 | 6 |  | T37 | 1 |