Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10351	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9114	1			T3	28		T4	24		T12	30
len_5001_7500	14544	1			T3	81		T4	24		T12	30
len_2501_5000	9266	1			T3	13		T4	24		T12	30
len_1025_2500	5419	1			T3	8		T4	14		T12	16
len_769_1024	6386	1			T3	3		T4	2		T5	25
len_513_768	6744	1			T4	3		T5	30		T12	2
len_257_512	21327	1			T4	2		T5	35		T12	244
len_0_256	258664	1			T3	12		T4	211		T5	36
len_keccak_block_sizes[72]	711	1			T4	2		T12	3		T13	2
len_keccak_block_sizes[104]	627	1			T4	2		T12	3		T13	2
len_keccak_block_sizes[136]	528	1			T12	3		T13	2		T36	3
len_keccak_block_sizes[144]	426	1			T12	3		T36	3		T37	2
len_keccak_block_sizes[168]	321	1			T12	3		T36	3		T66	3
len_1	766	1			T4	2		T12	3		T13	2
len_0	1239	1			T3	4		T4	2		T5	1