Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	11949000	1			T3	35071		T5	9982		T14	1678
shake	54984258	1			T3	10080		T5	9466		T12	559971
sha3	35413305	1			T3	975		T4	160323		T5	136

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90396457

1

T3

11055

T4

160323

T5

9594

auto[1]

11950106

1

T3

35071

T5

9990

T14

1678

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	100930322	1			T3	18877		T4	156448		T5	19556
depth[0x01]	873166	1			T3	5028		T4	3875		T5	28
depth[0x02]	173539	1			T3	6676		T14	2		T16	8
depth[0x03]	143360	1			T3	5769		T14	3		T16	8
depth[0x04]	91371	1			T3	3714		T14	2		T16	8
depth[0x05]	55119	1			T3	2393		T14	1		T16	4
depth[0x06]	22298	1			T3	1200		T22	179		T39	10
depth[0x07]	428	1			T22	12		T39	1		T41	9
depth[0x08]	1876	1			T3	99		T22	14		T39	2
depth[0x09]	1562	1			T3	57		T22	25		T39	1
depth[0x0a]	53522	1			T3	2313		T22	601		T39	72

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1416241

1

T3

27249

T4

3875

T5

28

auto[1]

100930322

1

T3

18877

T4

156448

T5

19556

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102293041

1

T3

43813

T4

160323

T5

19584

auto[1]

53522

1

T3

2313

T22

601

T39

72