Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100752305	1			T3	2609		T4	160944		T5	17962
all_pins[1]	100752305	1			T3	2609		T4	160944		T5	17962
all_pins[2]	100752305	1			T3	2609		T4	160944		T5	17962

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301446079	1			T3	7611		T4	482380		T5	53699
values[0x1]	810836	1			T3	216		T4	452		T5	187
transitions[0x0=>0x1]	809003	1			T3	216		T4	452		T5	187
transitions[0x1=>0x0]	809029	1			T3	216		T4	452		T5	187

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100241372	1			T3	2393		T4	160492		T5	17775
all_pins[0]	values[0x1]	510933	1			T3	216		T4	452		T5	187
all_pins[0]	transitions[0x0=>0x1]	510917	1			T3	216		T4	452		T5	187
all_pins[0]	transitions[0x1=>0x0]	75	1			T42	4		T148	2		T149	8
all_pins[1]	values[0x0]	100752214	1			T3	2609		T4	160944		T5	17962
all_pins[1]	values[0x1]	91	1			T42	4		T148	2		T149	8
all_pins[1]	transitions[0x0=>0x1]	76	1			T42	4		T148	2		T149	8
all_pins[1]	transitions[0x1=>0x0]	299797	1			T22	2660		T26	1579		T23	4265
all_pins[2]	values[0x0]	100452493	1			T3	2609		T4	160944		T5	17962
all_pins[2]	values[0x1]	299812	1			T22	2660		T26	1579		T23	4265
all_pins[2]	transitions[0x0=>0x1]	298010	1			T22	2638		T26	1578		T23	4240
all_pins[2]	transitions[0x1=>0x0]	509157	1			T3	216		T4	452		T5	187