Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	703	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5629	1			T3	25		T5	18		T17	2
len_601_800	12699	1			T3	49		T5	51		T14	1
len_401_600	8467	1			T3	39		T5	34		T14	1
len_201_400	16620	1			T3	12		T5	10		T17	6
len_65_200	74280	1			T3	11		T5	8		T12	685
len_min_for_xof_require_squeeze	1007	1			T12	9		T36	10		T66	10
len_keccak_block_sizes[72]	760	1			T12	9		T36	5		T66	5
len_keccak_block_sizes[104]	768	1			T12	9		T15	1		T36	5
len_keccak_block_sizes[136]	767	1			T12	9		T15	1		T36	5
len_keccak_block_sizes[144]	292	1			T36	5		T66	5		T22	1
len_keccak_block_sizes[168]	281	1			T36	5		T66	5		T75	5
len_datapath_width	14159	1			T3	1		T12	9		T15	8
len_2_63	214954	1			T3	8		T4	310		T5	42
len_1	55	1			T117	1		T38	1		T118	1