Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 10891370 | 1 |  |  | T3 | 22941 |  | T4 | 3720 |  | T5 | 21909 | 
| auto[1] | 25976934 | 1 |  |  | T3 | 33366 |  | T4 | 15500 |  | T5 | 32594 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 4 | 0 | 4 | 100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 36748022 | 1 |  |  | T3 | 56208 |  | T4 | 19220 |  | T5 | 54409 | 
| triple_byte_access | 39922 | 1 |  |  | T3 | 34 |  | T5 | 36 |  | T12 | 279 | 
| halfword_access | 40265 | 1 |  |  | T3 | 31 |  | T5 | 30 |  | T12 | 279 | 
| byte_access | 40095 | 1 |  |  | T3 | 34 |  | T5 | 28 |  | T12 | 279 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 8 | 3 | 5 | 62.50 | 3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | [triple_byte_access , halfword_access , byte_access] | -- | -- | 3 |  | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | word_access | 10771088 | 1 |  |  | T3 | 22842 |  | T4 | 3720 |  | T5 | 21815 | 
| auto[0] | triple_byte_access | 39922 | 1 |  |  | T3 | 34 |  | T5 | 36 |  | T12 | 279 | 
| auto[0] | halfword_access | 40265 | 1 |  |  | T3 | 31 |  | T5 | 30 |  | T12 | 279 | 
| auto[0] | byte_access | 40095 | 1 |  |  | T3 | 34 |  | T5 | 28 |  | T12 | 279 | 
| auto[1] | word_access | 25976934 | 1 |  |  | T3 | 33366 |  | T4 | 15500 |  | T5 | 32594 |